Afundamentals of logic design 6th 2012

Fundamentals of Logic Design This page intentionally left blank Fundamentals of Logic Design Charles H Roth, Jr University of Texas at Austin Larry L Kinney University of Minnesota, Twin Cities Australia • Brazil • Japan • Korea • Mexico • Singapore • Spain • United Kingdom • United States Fundamentals of Logic Design, Sixth Edition © 2010 and 2004 Cengage Learning Charles H Roth, Jr and Larry L Kinney Senior Developmental Editor: Hilda Gowans ALL RIGHTS RESERVED No part of this work covered by the copyright herein may be reproduced, transmitted, stored, or used in any form or by any means—graphic, electronic, or mechanical, including but not limited to photocopying, recording, scanning, digitizing, taping, Web distribution, information networks, information storage and retrieval systems, or in any other manner—except as may be permitted by the license terms herein Editorial Assistant: Jennifer Dismore For product information and technology assistance, contact us at Cengage Learning Customer & Sales Support, 1-800-354-9706 Director, Global Engineering Program: Chris Carson Marketing Services Coordinator: Lauren Bestos Director, Content and Media Production: Barbara Fuller-Jacobsen Content Project Manager: Cliff Kallemeyn Production Service: RPK Editorial Services, Inc Copyeditor: Fred Dahl Proofreader: Harlan James Indexer: Ron Prottsman Compositor: Integra Senior Art Director: Michelle Kunkler Internal Designer: Carmela Periera Cover Designer: Andrew Adams Cover Image: © Shutterstock/guattie`ro boffi Senior First Print Buyer: Doug Wilke Printed in the United States of America 12 11 10 09 08 For permission to use material from this text or product, submit all requests online at www.cengage.com/permissions Further permissions questions can be emailed to permissionrequest@cengage.com Library of Congress Control Number: 2009920814 Student Edition with CD: ISBN-13: 978-0-495-47169-1 ISBN-10: 0-495-47169-0 Student Edition: ISBN-13: 978-0-495-66804-6 ISBN-10: 0-495-66804-4 Cengage Learning 200 First Stamford Place, Suite 400 Stamford, CT 06902 USA Cengage Learning is a leading provider of customized learning solutions with office locations around the globe, including Singapore, the United Kingdom, Australia, Mexico, Brazil, and Japan Locate your local office at: international.cengage.com/region Cengage Learning products are represented in Canada by Nelson Education Ltd For your course and learning solutions, visit www.cengage.com/engineering Purchase any of our products at your local college store or at our preferred online store www.ichapters.com Brief Contents Introduction Number Systems and Conversion Applications of Boolean Algebra Minterm and Maxterm Expansions 83 Multi-Level Gate Circuits NAND and NOR Gates 184 Combinational Circuit Design and Simulation Using Gates 215 Multiplexers, Decoders, and Programmable Logic Devices 242 Boolean Algebra 27 Boolean Algebra (Continued) 56 Karnaugh Maps 116 Quine-McCluskey Method 159 vi Brief Contents 10 11 12 13 14 15 16 17 18 19 20 A Introduction to VHDL 280 Latches and Flip-Flops 317 Registers and Counters 348 Analysis of Clocked Sequential Circuits 388 Derivation of State Graphs and Tables 427 Reduction of State Tables State Assignment 466 Sequential Circuit Design 511 VHDL for Sequential Logic 549 Circuits for Arithmetic Operations 591 State Machine Design with SM Charts 623 VHDL for Digital System Design 646 Appendices 675 Contents Preface xv How to Use This Book for Self-Study xix Unit Introduction Number Systems and Conversion 1.1 1.2 1.3 1.4 1.5 Objectives Study Guide Digital Systems and Switching Circuits Number Systems and Conversion Binary Arithmetic 12 Representation of Negative Numbers Addition of 2’s Complement Numbers Addition of 1’s Complement Numbers Binary Codes 21 Problems 23 16 17 19 Unit Boolean Algebra 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Objectives 27 Study Guide 28 Introduction 34 Basic Operations 35 Boolean Expressions and Truth Tables 37 Basic Theorems 39 Commutative, Associative, and Distributive Laws Simplification Theorems 42 Multiplying Out and Factoring 44 40 vii viii Contents 2.8 DeMorgan’s Laws 47 Problems 48 Laws and Theorems of Boolean Algebra 55 Unit Boolean Algebra (Continued) 3.1 3.2 3.3 3.4 3.5 Objectives 56 Study Guide 57 Multiplying Out and Factoring Expressions 62 Exclusive-OR and Equivalence Operations 64 The Consensus Theorem 66 Algebraic Simplification of Switching Expressions Proving Validity of an Equation 70 Programmed Exercises 73 Problems 78 68 Unit Applications of Boolean Algebra Minterm and Maxterm Expansions 4.1 4.2 4.3 4.4 4.5 4.6 4.7 Objectives 83 Study Guide 84 Conversion of English Sentences to Boolean Equations Combinational Logic Design Using a Truth Table 92 Minterm and Maxterm Expansions 93 General Minterm and Maxterm Expansions 96 Incompletely Specified Functions 99 Examples of Truth Table Construction 100 Design of Binary Adders and Subtracters 104 Problems 107 Unit Karnaugh Maps 5.1 5.2 5.3 5.4 5.5 5.6 Objectives 116 Study Guide 117 Minimum Forms of Switching Functions Two- and Three-Variable Karnaugh Maps Four-Variable Karnaugh Maps 133 Determination of Minimum Expressions Using Essential Prime Implicants 136 Five-Variable Karnaugh Maps 141 Other Uses of Karnaugh Maps 144 127 129 90 Contents 5.7 Other Forms of Karnaugh Maps Programmed Exercises 147 Problems 152 146 Unit Quine-McCluskey Method 6.1 6.2 6.3 6.4 6.5 6.6 Objectives 159 Study Guide 160 Determination of Prime Implicants 165 The Prime Implicant Chart 168 Petrick’s Method 171 Simplification of Incompletely Specified Functions Simplification Using Map-Entered Variables 174 Conclusion 176 Programmed Exercise 177 Problems 181 173 Unit Multi-Level Gate Circuits NAND and NOR Gates 7.1 7.2 7.3 7.4 7.5 7.6 7.7 Objectives 184 Study Guide 185 Multi-Level Gate Circuits 190 NAND and NOR Gates 195 Design of Two-Level NAND- and NOR- Gate Circuits 197 Design of Multi-Level NAND- and NOR- Gate Circuits 200 Circuit Conversion Using Alternative Gate Symbols 201 Design of Two-Level, Multiple-Output Circuits 204 Determination of Essential Prime Implicants for Multiple-Output Realization 206 Multiple-Output NAND- and NOR-Gate Circuits 208 Problems 208 Unit Combinational Circuit Design and Simulation Using Gates 8.1 8.2 8.3 Objectives 215 Study Guide 216 Review of Combinational Circuit Design 219 Design of Circuits with Limited Gate Fan-In 220 Gate Delays and Timing Diagrams 222 ix VHDL Language Summary 683 process statement (without sensitivity list) [process-label:] process [declarations] signal declarations not allowed begin sequential statements end process [process-label]; Note: This form of process must contain one or more wait statements It starts execution immediately and continues until a wait statement is encountered wait statements wait on sensitivity-list; wait until Boolean-expression; wait for time-expression; if statement (sequential statement only) if condition then sequential statements {elsif condition then sequential statements } or more elsif clauses may be included [else sequential statements] end if; case statement (sequential statement only) case expression is when choice1 > sequential statements when choice2 > sequential statements [when others > sequential statements] end case; for loop statement (sequential statement only) [loop-label:] for index in range loop sequential statements end loop [loop-label]; Note: You may use exit to exit the current loop report declaration report string-expression [severity severity-level]; VHDL Libraries and Packages VHDL libraries and packages are used to extend the functionality of VHDL by defining types, functions, components, and overloaded operators The syntax for libraries and packages is as follows: library declaration library list-of-library names; 684 Appendix B use statement use library_name.package_name.item; (.item may be all) package declaration package package-name is package declarations end [package][package-name]; package body package body package-name is package body declarations end [package body][package name]; When working with bits and bit_vectors, you may use the following declarations: library BITLIB; use BITLIB.bit_pack.all; The bit_pack package includes functions and components that work with signals of type bit and bit_vector For example, the function call vec2int(A) converts a bit_vector A to an integer The CD contains a complete listing of bit_pack When working with std_logic and std_logic_vectors, the following declarations are required: library IEEE; use IEEE.std_logic_1164.all; The std_logic_1164 package defines the types std_logic and std_logic_vector, a resolution function for these types, conversion functions, and overloaded operators for logic operations It does not define overloaded operators for arithmetic operations In order to perform arithmetic operations on std_logic_vectors, you may add the declaration use IEEE.std_logic_unsigned.all; Although this package is found in the IEEE library, it was written by Synopsis and it is not an IEEE standard This package treats std_logic_vectors as if they were unsigned numbers and provides overloaded arithmetic operators for , , *, , /, , , , and For “” and “” if the left operand is a std_logic_vector, the right operand can be the same type, integer type, or std_logic type For the comparison operators, the right operand can be a std_logic_vector or an integer The function call CONV_INTEGER(A) converts a std_logic_vector A to an integer As an alternative to using std_logic_vectors and the overloaded operators defined in the std_logic_unsigned package, type unsigned may be used Unsigned type is defined in the Synopsis package std_logic_arith and in the IEEE package numeric_std To use the former, add the declaration use IEEE.std_logic_arith.all; A vector of type unsigned is similar to a std_logic_vector in that it is an array of std_logic bits, but it has its own overloaded arithmetic operators Operators for , , *, , /, , , , and are defined in the std_logic_arith package for various combinations of left and right operands Unfortunately, logic operators AND, OR, and NOT are not defined for unsigned vectors in this package, so C A B; VHDL Language Summary 685 works for unsigned vectors, but C A and B; is not allowed without calling type conversion functions Some type conversion functions available in this package are as follows: conv_integer(A) converts an unsigned vector A to an integer conv_std_logic_vector(A) converts an unsigned vector A to a std_logic_vector conv_unsigned(B, N) converts an integer B to an unsigned vector of length N Conversion of a std_logic_vector to unsigned is not defined The IEEE numeric_std package, which actually is an IEEE standard, overcomes a number of the deficiencies in the std_logic_arith package The statement use IEEE.numeric_std.all; invokes this package It defines unsigned type and overloaded operators for arithmetic and comparison operations in a way similar to the std_logic_arith package, but in addition it defines overloaded operators for logic operations on unsigned vectors Useful conversion functions in the package include TO_INTEGER(A) converts an unsigned vector A to an integer TO_UNSIGNED(B, N) converts an integer to an unsigned vector of length N The only significant deficiency is that this package does not define an overloaded operator for adding a std_logic bit to an unsigned type Thus, a statement of the form sum A B carry; is not allowed when carry is of type std_logic The carry must be converted to an integer before it can be added to the unsigned vector A B We have used the std_logic_unsigned package in many examples in this book because it is easy to use For complex VHDL projects, we recommend using the numeric_std package Most VHDL simulators and synthesizers work well with either package ACPHPAE PNTDEIRX C 00 Tips for writing Synthesizable VHDL Code One of our goals throughout this text is to write VHDL code that not only simulates correctly but also synthesizes correctly to implement hardware that works correctly First and foremost, always remember that when you write VHDL code you are not writing a computer program; you are describing hardware If you are designing a multiplier for binary numbers, not simply write a program to multiply binary numbers Instead think in terms of what registers are required and what sequence of operations on these registers will produce the desired result VHDL code that simulates correctly will not always implement correctly in hardware A frequent cause of problems is the creation of unintended latches Even though code simulates correctly, the presence of latches may cause timing problems when the code is actually implemented in hardware After synthesizing your code, check the synthesis report to make sure no latches are present If latches are present, check your code for the following: Counters, shift registers, flip-flops, and other devices that change state in response to a clock edge must be updated only in a clocked process The state of these devices should never be changed in a combinational process or in a concurrent statement All state changes for a given device must be specified within the same process Example: count count 1; should not appear in a combinational process When this statement, which increments a counter, is placed in a clocked process, any statement that clears the counter must be placed in the same process If a combinational process sets control signals to '1' at various places in a case statement, all of these signals should be set to '0' before the start of the case statement For every if statement in a combinational process, check each signal that is assigned a value in the then clause If such a signal is not assigned a value in step 2, then make sure that it is assigned a value in the else clause Example: if St '1' then nextstate 1; load '1'; end if; will create a latch because nextstate is not defined when St '0' To eliminate the latch write if St '1' then nextstate 1; load '1'; else nextstate 0; end if; This assumes that load is set to '0' in step (2) Do not attempt to set the same signal to two different values in two different processes or in a process and in a concurrent statement 686 Tips for writing Synthesizable VHDL Code Example 687 A '0'; is a concurrent statement, and A B; is another concurrent statement or a sequential statement in a process These statements can attempt to set A to two different values at the same time If A and B are bit signals, when you try to simulate, you will get an error message that a signal has multiple drivers That means a conflict exists because A could be driven to '0' and to '1' at the same time If A and B are std_logic, the conflict still exists, but you will not get the error message Instead, during simulation A will assume the value 'X' (unknown) if the simulator tries to set A to '0' and '1' at the same time In both cases, the code will not synthesize properly because it does not correspond to any real hardware Also consider the following example: Example of what NOT TO DO: output A is assigned values in a concurrent statement and in a processes entity two_drivers is port (B,clk,reset : in bit; A : out bit); end two_drivers; architecture arch of two_drivers is begin A ‘0’ when reset ‘0’; process (clk) begin if clk’event and clk ‘0’ then A B; end if; end process; end arch; In this example, A is supposed to represent a flip-flop that is reset to '0' when the signal reset is '0' and set equal to B on the falling clock edge Although this code has correct syntax, it will not simulate properly because the two statements that change A occur as a concurrent statement and also as a sequential statement in a process so that A has two drivers If the signals are std_logic instead of bits, A will assume a value of 'X' at times during the simulation The code will not synthesize because all statements that change the output of flip-flop A must be placed in the same process This also would apply if A were a register or a counter Excercise Change the preceding code so that the reset signal will work properly An easy way to write synthesizable VHDL code to perform arithmetic operations is to represent binary numbers as std_logic_vectors so that overloaded operators can be used This is explained on pages 305–306 of the text 688 Appendix C Overloaded and – operators cannot be used with bit vectors If you use overloaded operators with std_logic_vectors in your VHDL code, place the following declarations at the start of your code: library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; this library contains several useful packages this package defines std_logic, std_logic_vectors and logic operations on these types this package defines overloaded operators for std_logic_vectors Remember that the VHDL operators , , and & have the same precedence and will be applied from left to right as they appear in a VHDL statement Thus A B C&D; is treated as A (BC)&D; If you want to concatenation first, you must use parentheses A B (C&D); Proofs of Theorems ACPHPAE PNTDEIRX D 00 Finding Essential Prime Implicants Section 5.4 presents a method for finding all of the essential prime implicants which is based on finding adjacent 1’s on a Karnaugh map The validity of the method is based on the following theorem: If a given minterm mj of F and all of its adjacent minterms are covered by a single term pj, then pj is an essential prime implicant of F Proof: Assume pj is not a prime implicant Then, it can be combined with another term pk to eliminate some variable xi and form another term which does not contain xi Therefore, xi in pj and xi in pk, or vice versa Then, pk covers a minterm mk which differs from mj only in the variable xi This means that mk is adjacent to mj, but mk is not covered by pj This contradicts the original assumption that all minterms adjacent to mj are covered by pj; therefore, pj is a prime implicant Assume pj is not essential Then, there is another prime implicant ph which covers mj Because ph is not contained in pj, ph must contain at least one minterm which is adjacent to mj and not covered by pj This is a contradiction, so pj must be essential State Equivalence Theorem The methods for determining state equivalence presented in Unit 15 are based on Theorem 15.1: Two states p and q of a sequential network are equivalent if and only if for every single input x, the outputs are the same and the next states are equivalent Proof: We must prove both part 1, the “if” part of the theorem, and part 2, the “only if” part 689 689 690 Appendix D Assume that (p, x) (q, x) and (p, x) ≡ (q, x) for every input x Then, from Definition 15.1, for every input sequence X, [(p, x), X] [(q, x), X] For the input sequence Y x followed by X, we have (p, Y) (p, x) followed by [(p, x), X)] (q, Y) (q, x) followed by [(q, x), X)] Hence, (p, Y) (q, Y) for every input sequence Y, and p ≡ q by Definition 15.1 Assume that p ≡ q Then, by Definition 15.1, (p, Y) (q, Y) for every input sequence Y Let Y x followed by X Then, (p, x) (q, x) and [(p, x), X] [(q, x), X] for every sequence X Hence, from Definition 15.1, (p, x) ≡ (q, x) APPENDIX E Answers to Selected Study Guide Questions and Problems UNIT Study Guide Answers (e) Two of the rows are: 1110 16 14 E 1111 17 15 F (b) 11002 1012 [1 23 22 21 20] [ 22 21 20] note borrow from column ↓ ↓ [1 23 22 (0 1) 21 (10 0) 20] [ 22 21 20] note borrow from column ↓ ↓ [1 23 (1 1) 22 (10 1) 21 10 20] [ 22 21 20] note borrow from column ↓ ↓ [(1 1) 23 (10 0) 22 21 10 20] [ 22 21 20] [ 2 22 21 20] 1112 (f) sign & mag: 0, 2’s comp: 32, 1’s comp: 31 (g) Overflow occurs when adding n-bit numbers and the result requires n bits for proper representation You can tell that an overflow has occurred when the sum of two positive numbers is negative or the sum of two negative numbers is positive A carry out of the last bit position does not indicate that an overflow has occurred (a) BCD: 0001 1000 0111 excess-3: 0100 1011 1010 6-3-1-1: 0001 1011 1001 2-out-of-5: 00101 10100 10010 UNIT Answers to Problems 1.1 (a) (b) (c) (d) 2F5.4016 001011110101.010000002 7B.2B16 01111011.001010112 164.E316 000101100100.111000112 427.816 010000100111.10002 691 691 692 Appendix E 1.2 (a) 7261.38 3761.410, EB1.616 3761.410 (b) 2635.68 1437.810, 59D.C16 1437.810 1.3 3252.10026 1.4 (a) 5B1.1C16 (b) 010110110001.000111002 2661.0708 (c) 112301.01304 (d) 3564.610 1.5 (a) Add: 11001 Subtract: 0101 Multiply: 10010110 (b) Add: 1010011 Subtract: 011001 Multiply: 11000011110 (c) Add: 111010 Subtract: 001110 Multiply: 1100011000 1.6 (a) 1111 11110100 1000111 10101101 1.7 2’s complement: (a) 010101 001011 100000 OVERFLOW! (d) 110100 001101 (1) 000001 1’s complement: (a) 010101 001011 100000 OVERFLOW! (d) 110011 001101 (1) 000000 000001 (b) 111 1110110 111101 0111001 (c) 11111 10110010 111101 01110101 (b) (c) 110010 100000 (1) 010010 OVERFLOW! 100111 010010 111001 (e) 110101 101011 (1) 100000 (b) not assigned because –32 cannot be represented in bits (c) 100110 010010 111000 (e) 110100 101010 (1) 011110 011111 OVERFLOW! 1.8 For a word length of N, the range of 2’s complement numbers that can be represented is 2N1 to 2N1 So, for a word length of 8, the range is 27 to 27 1, or 128 to 127 Because 1’s complement has a “negative zero” (11111111) in addition to zero (00000000), the values that can be represented range from (27 1) to 27 1, or 127 to 127 1.9 Dec 7-3-2-1 0000 0001 0010 0011 or 0100 0101 0110 0111 0011 0111 0110 1010 or 0100 Answers to Selected Study Guide Questions and Problems 693 1000 1001 1010 UNIT Study Guide Answers (d) 1; 0; 1; (e) 1, 1; 0, 0; 0; (a) four variables, 10 literals (d) F (A B) (e) F (A B )C (f) Circuit should have two OR gates, three AND gates, and three inverters (b) A, 0, 0, A; A, 1, A, (c) Z ABC (a) Sum of products Neither Product of sums (Here, A and B are each considered to be separate terms in the product.) Neither (b) Fewer terms are generated (c) D[A B (C E)] D(A B )(A C E) (a) AE B C C D (b) C DE AB CD E 10 (a) a b c (b) ab c d (c) a(b c ) (d) (a b)(c d ) (e) a b(c d ) UNIT Answers to Problems 2.1 (a) (b) (c) (d) X(X Y ) XX XY XY XY X XY X(1 Y) X(1) X XY XY X(Y Y ) X(1) X (A B)(A B ) AA AB AB BB A AB AB BB A(1 B B ) A(1) A 2.2 X X = Y Y (a) 2.3 (a) (b) (c) (e) 2.4 (a) (b) 2.5 (a) 2.6 (a) (c) X = X Z X X Y Z (b) (Theorem 5) CD AB E (Theorem 8D) (technically, we also used Theorem 3D) AF (Theorem 9) (d) C D B A (Theorem 11D) A B D (Theorem 10D) (f) A BC DE F (Theorem 11D) F A E BCD (one AND gate and one OR gate with three inputs) YAB ACD BE (b) A B A D C B C D (A C )(A D )(B C )(B D ) (b) X(W Z)(W Y ) (A E)(B E)(C E)(A D F)(B D F)(C D F) 694 Appendix E (d) Z(W X)(Q W Y) (e) (A D )(C D ) (f) (A B D)(A C D)(A B E)(A C E) 2.7 D E F A B C + U V W (a) 2.8 (a) ABC ABD (b) A B A CD 2.9 (a) F A B (b) G T + X Y Z (b) (c) A BC UNIT Study Guide Answers (b) (c) (b) (c) (b d)(b a)(b c) (a d)(b d)(a b c) w y x y z xy wyz A B C BC D AB D BCD Add BCD; eliminate A BD, ABC UNIT Answers to Problems 3.6 (a) WY X WY Z W X Y W X Z (b) A D AC 3.7 (a) (C D)(C D B ) (b) (D A B )(D C B )(D A C )(D A B) 3.8 F (AB) ⊕ [(A ≡ D) D] A BD B D 3.9 No Consider A 1, B 1, C or A 1, B 0, C 3.10 (a) W X WY Z WYZ (b) BD A BC AB AC (c) (A C D)(A C D )(B C D) 3.11 AE AC B CD D E 3.12 A CD E A B D ABCE ABD A CD E BCD E A B D ABCE ABD A B D ABD BCD E UNIT Study Guide Answers ab c d (e) a b c d (a b c)(a b c )(a b c)(a b c ) m0 m1 m3 m4 m(0, 1, 3, 4) M2M5M6M7 M(2, 5, 6, 7) m19 (c) A BCD E M19 (f) (A B C D E ) 65536 (a0m0 a1m1 a2m2 a3m3)(b0m0 b1m1 b2m2 b3m3) a0b0m0 a1b1m1 a2b2m2 a3b3m3 (f) f M(2, 5, 6) f m(2, 5, 6) M(0, 1, 3, 4, 7) (b) m(0, 5) d(1, 3, 4) (d) (g) (c) (b) (e) (a) (d)