Fundamentals of Digital Logic with Verilog Design THIRD EDITION Stephen Brown and Zvonko Vranesic Department of Electrical and Computer Engineering University of Toronto FUNDAMENTALS OF DIGITAL LOGIC WITH VERILOG DESIGN, THIRD EDITION Published by McGraw-Hill, a business unit of The McGraw-Hill Companies, Inc., 1221 Avenue of the Americas, New York, NY 10020 Copyright © 2014 by The McGraw-Hill Companies, Inc All rights reserved No part of this publication may be reproduced or distributed in any form or by any means, or stored in a database or retrieval system, without the prior written consent of The McGraw-Hill Companies, Inc., including, but not limited to, in any network or other electronic storage or transmission, or broadcast for distance learning Some ancillaries, including electronic and print components, may not be available to customers outside the United States This book is printed on acid-free paper DOC/DOC ISBN 978–0–07–338054–4 MHID 0–07–338054–7 Managing Director: Thomas Timp Director: Michael Lange Global Publisher: Raghothaman Srinivasan Developmental Editor: Vincent Bradshaw Marketing Manager: Curt Reynolds Director, Content Production: Terri Schiesl Senior Project Manager: Melissa M Leick Buyer: Susan K Culbertson Media Project Manager: Prashanthi Nadipalli Cover Design: Studio Montage, St Louis, Missouri (USE) Cover Image: Steven Brown and Zvonko Vranesic Compositor: Techsetters, Inc Typeface: 10/12 Times Roman Printer: R R Donnelley, Crawfordsville, IN Library of Congress Cataloging-in-Publication Data Brown, Stephen Fundamentals of digital logic with Verilog design / Stephen Brown and Zvonko Vranesic — Third edition pages cm ISBN 978–0–07–338054–4 (alk paper) Logic circuits—Design and construction—Data processing Verilog (Computer hardware description language) Computer-aided design I Vranesic, Zvonko G II Title TK7868.L6B76 2014 621.39′ 2–dc23 www.mhhe.com 2012042163 To Susan and Anne This page intentionally left blank About the Authors Stephen Brown received his B.A.Sc degree in Electrical Engineering from the University of New Brunswick, Canada, and the M.A.Sc and Ph.D degrees in Electrical Engineering from the University of Toronto He joined the University of Toronto faculty in 1992, where he is now a Professor in the Department of Electrical & Computer Engineering He is also the Director of the worldwide University Program at Altera Corporation His research interests include field-programmable VLSI technology and computer architecture He won the Canadian Natural Sciences and Engineering Research Council’s 1992 Doctoral Prize for the best Ph.D thesis in Canada and has published more than 100 scientific research papers He has won five awards for excellence in teaching electrical engineering, computer engineering, and computer science courses He is a coauthor of two other books: Fundamentals of Digital Logic with VHDL Design, 3rd ed and Field-Programmable Gate Arrays Zvonko Vranesic received his B.A.Sc., M.A.Sc., and Ph.D degrees, all in Electrical Engineering, from the University of Toronto From 1963–1965 he worked as a design engineer with the Northern Electric Co Ltd in Bramalea, Ontario In 1968 he joined the University of Toronto, where he is now a Professor Emeritus in the Departments of Electrical & Computer Engineering and Computer Science During the 1978–1979 academic year, he was a Senior Visitor at the University of Cambridge, England, and during 1984–1985 he was at the University of Paris, From 1995 to 2000 he served as Chair of the Division of Engineering Science at the University of Toronto He is also involved in research and development at the Altera Toronto Technology Center His current research interests include computer architecture and field-programmable VLSI technology He is a coauthor of four other books: Computer Organization and Embedded Systems, 6th ed.; Fundamentals of Digital Logic with VHDL Design, 3rd ed.; Microcomputer Structures; and Field-Programmable Gate Arrays In 1990, he received the Wighton Fellowship for “innovative and distinctive contributions to undergraduate laboratory instruction.” In 2004, he received the Faculty Teaching Award from the Faculty of Applied Science and Engineering at the University of Toronto He has represented Canada in numerous chess competitions He holds the title of International Master v Preface This book is intended for an introductory course in digital logic design, which is a basic course in most electrical and computer engineering programs A successful designer of digital logic circuits needs a good understanding of basic concepts and a firm grasp of the modern design approach that relies on computer-aided design (CAD) tools The main goals of the book are (1) to teach students the fundamental concepts in classical manual digital design and (2) illustrate clearly the way in which digital circuits are designed today, using CAD tools Even though modern designers no longer use manual techniques, except in rare circumstances, our motivation for teaching such techniques is to give students an intuitive feeling for how digital circuits operate Also, the manual techniques provide an illustration of the types of manipulations performed by CAD tools, giving students an appreciation of the benefits provided by design automation Throughout the book, basic concepts are introduced by way of examples that involve simple circuit designs, which we perform using both manual techniques and modern CAD-tool-based methods Having established the basic concepts, more complex examples are then provided, using the CAD tools Thus our emphasis is on modern design methodology to illustrate how digital design is carried out in practice today Technology The book discusses modern digital circuit implementation technologies The emphasis is on programmable logic devices (PLDs), which is the most appropriate technology for use in a textbook for two reasons First, PLDs are widely used in practice and are suitable for almost all types of digital circuit designs In fact, students are more likely to be involved in PLDbased designs at some point in their careers than in any other technology Second, circuits are implemented in PLDs by end-user programming Therefore, students can be provided with an opportunity, in a laboratory setting, to implement the book’s design examples in actual chips Students can also simulate the behavior of their designed circuits on their own computers We use the two most popular types of PLDs for targeting of designs: complex programmable logic devices (CPLDs) and field-programmable gate arrays (FPGAs) We emphasize the use of a hardware description language in specifying the logic circuits, because the HDL-based approach is the most efficient design method to use in practice We describe in detail the IEEE Standard Verilog HDL language and use it extensively in examples vi Preface Scope of the Book This edition of the book has been extensively restructured All of the material that should be covered in a one-semester course is now included in Chapters to More advanced material is presented in Chapters to 11 Chapter provides a general introduction to the process of designing digital systems It discusses the key steps in the design process and explains how CAD tools can be used to automate many of the required tasks It also introduces the representation of digital information Chapter introduces the logic circuits It shows how Boolean algebra is used to represent such circuits It introduces the concepts of logic circuit synthesis and optimization, and shows how logic gates are used to implement simple circuits It also gives the reader a first glimpse at Verilog, as an example of a hardware description language that may be used to specify the logic circuits Chapter concentrates on circuits that perform arithmetic operations It discusses numbers and shows how they can be manipulated using logic circuits This chapter illustrates how Verilog can be used to specify the desired functionality and how CAD tools provide a mechanism for developing the required circuits Chapter presents combinational circuits that are used as building blocks It includes the encoder, decoder, and multiplexer circuits These circuits are very convenient for illustrating the application of many Verilog constructs, giving the reader an opportunity to discover more advanced features of Verilog Storage elements are introduced in Chapter The use of flip-flops to realize regular structures, such as shift registers and counters, is discussed Verilog-specified designs of these structures are included Chapter gives a detailed presentation of synchronous sequential circuits (finite state machines) It explains the behavior of these circuits and develops practical design techniques for both manual and automated design Chapter is a discussion of a number of practical issues that arise in the design of real systems It highlights problems often encountered in practice and indicates how they can be overcome Examples of larger circuits illustrate a hierarchical approach in designing digital systems Complete Verilog code for these circuits is presented Chapter deals with more advanced techniques for optimized implementation of logic functions It presents algorithmic techniques for optimization It also explains how logic functions can be specified using a cubical representation as well as using binary decision diagrams Asynchronous sequential circuits are discussed in Chapter While this treatment is not exhaustive, it provides a good indication of the main characteristics of such circuits Even though the asynchronous circuits are not used extensively in practice, they provide an excellent vehicle for gaining a deeper understanding of the operation of digital circuits in general They illustrate the consequences of propagation delays and race conditions that may be inherent in the structure of a circuit Chapter 10 presents a complete CAD flow that the designer experiences when designing, implementing, and testing a digital circuit vii viii Preface Chapter 11 introduces the topic of testing A designer of logic circuits has to be aware of the need to test circuits and should be conversant with at least the most basic aspects of testing Appendix A provides a complete summary of Verilog features Although use of Verilog is integrated throughout the book, this appendix provides a convenient reference that the reader can consult from time to time when writing Verilog code The electronic aspects of digital circuits are presented in Appendix B This appendix shows how the basic gates are built using transistors and presents various factors that affect circuit performance The emphasis is on the latest technologies, with particular focus on CMOS technology and programmable logic devices What Can Be Covered in a Course Much of the material in the book can be covered in one-quarter courses A good coverage of the most important material can be achieved in a single one-semester, or even a onequarter course This is possible only if the instructor does not spend too much time teaching the intricacies of Verilog and CAD tools To make this approach possible, we organized the Verilog material in a modular style that is conducive to self-study Our experience in teaching different classes of students at the University of Toronto shows that the instructor may spend only three to four lecture hours on Verilog, describing how the code should be structured, including the use of design hierarchy, using scalar and vector variables, and on the style of code needed to specify sequential circuits The Verilog examples given in the book are largely self-explanatory, and students can understand them easily The book is also suitable for a course in logic design that does not include exposure to Verilog However, some knowledge of Verilog, even at a rudimentary level, is beneficial to the students, and it is a great preparation for a job as a design engineer One-Semester Course The following material should be covered in lectures: • • • • • • Chapter 1—all sections Chapter 2—all sections Chapter 3—Sections 3.1 to 3.5 Chapter 4—all sections Chapter 5—all sections Chapter 6—all sections One-Quarter Course In a one-quarter course the following material can be covered: • • Chapter 1—all sections Chapter 2—all sections Preface • • • • Chapter 3—Sections 3.1 to 3.3 and Section 3.5 Chapter 4—all sections Chapter 5—all sections Chapter 6—Sections 6.1 to 6.4 Verilog Verilog is a complex language, which some instructors feel is too hard for beginning students to grasp We fully appreciate this issue and have attempted to solve it It is not necessary to introduce the entire Verilog language In the book we present the important Verilog constructs that are useful for the design and synthesis of logic circuits Many other language constructs, such as those that have meaning only when using the language for simulation purposes, are omitted The Verilog material is introduced gradually, with more advanced features being presented only at points where their use can be demonstrated in the design of relevant circuits The book includes more than 120 examples of Verilog code These examples illustrate how Verilog is used to describe a wide range of logic circuits, from those that contain only a few gates to those that represent digital systems such as a simple processor All of the examples of Verilog code presented in the book are provided on the Authors’ website at www.eecg.toronto.edu/∼brown/Verilog_3e Solved Problems The chapters include examples of solved problems They show how typical homework problems may be solved Homework Problems More than 400 homework problems are provided in the book Answers to selected problems are given at the back of the book Solutions to all problems are available to instructors in the Solutions Manual that accompanies the book PowerPoint Slides and Solutions Manual PowerPoint slides that contain all of the figures in the book are available on the Authors’ website Instructors can request access to these slides, as well as access to the Solutions Manual for the book, at: www.mhhe.com/brownvranesic ix Answers 6.22 833 The desired circuit is T Q Q T Q Q w z1 6.29 z0 The state table is Present state A B C D Next state w=0 A A A A w=1 Output z C D D B 0 The circuit produces z = whenever the input sequence on w comprises a followed by an even number of 1s Chapter 8.1 8.2 8.5 8.8 f = (x3 ↑ g) ↑ ((g ↑ g) ↑ x4 ) where g = (x1 ↑ (x2 ↑ x2 )) ↑ ((x1 ↑ x1 ) ↑ x2 ) f = (((x3 ↓ x3 ) ↓ g) ↓ ((g ↓ g) ↓ (x4 ↓ x4 )), where g = ((x1 ↓ x1 ) ↓ x2 ) ↓ (x1 ↓ (x2 ↓ x2 )) Then, f = f ↓ f f = x1 (x2 + x3 )(x4 + x5 ) + x1 (x2 + x3 )(x4 + x5 ) f = g · h + g · h, where g = x1 x2 and h = x3 + x4 834 Answers 8.12 The BDD is x1 0 x2 x2 x3 0 x3 1 x4 1 x4 0 8.18 1 f = x x x + x x x + x x x + x x3 x Chapter 9.1 The flow table is Present state Next state w2 w1 = 00 01 10 11 z2 z1 A D C D C 11 B D C D D D B♠ B♠ C♠ D C♠ D♠ C B C 10 01 00 The behavior is the same as described in the flow table in Figure 9.21a, if the state interchanges A ↔ D and B ↔ C are made 835 Answers 9.8 Using the merger diagram in Figure 9.40a, the FSM in Figure 9.39 becomes Present state Next state w2 w1 = 00 01 10 11 B♠ G E − D − C E A D♠ D C♠ D G B D B A♠ C B A 9.10 Output z B♠ C C♠ E E E♠ − G♠ − The minimum-cost hazard-free implementation is f = x x x + x x2 x4 + x x3 x4 9.12 The minimum-cost hazard-free POS implementation is f = (x1 +x2 +x4 )(x1 +x2 +x3 )(x1 +x3 +x4 )(x2 +x3 +x4 ) 9.14 If A = B = D = E = and C changes from to 1, then f changes → → and g changes → → → Therefore, there is a static hazard on f and a dynamic hazard on g 9.17 The excitation table is Present state y Next state wc = 00 01 Output 10 11 0♠ Y 0♠ 0♠ 1♠ 1♠ 1♠ 00 01 10 11 z 0 0 1 The next-state expression is Y = wc + cy + wy Note that the term wy is included to prevent a static hazard The output expression is z = cy 836 Answers Chapter 11 11.1 A minimal test set must include the tests w1 w2 w3 = 011, 101, and 111, as well as one of 000, 010, or 100 11.3 The two functions differ only in the vertex x1 x2 x3 x4 = 0111 Therefore, the circuits can be distinguished by applying this input valuation 11.5 The tests are w1 w2 w3 w4 = 1111, 1110, 0111, and 1111 11.9 11.11 Cannot detect if the input wire w1 is stuck-at-1 The reason is that this circuit is highly redundant It realizes the function f = w3 (w1 + w2 ), which can be implemented with a simpler circuit Test set = {0000, 0111, 1111, 1000} It would work with XORs implemented as shown in Figure 4.26c For n bits, the same patterns can be used; thus Test set = {00 00, 011 1, 11 1, 100 0} 11.12 In the decoder circuit in Figure 6.16c the four AND gates are enabled only if the En signal is active The required test set has to include all four valuations of w1 and w2 when En = It is also necessary to test if the En wire is stuck at 1, which can be accomplished with the test w1 w2 En = 000 Therefore, a complete test set comprises w1 w2 En = 000, 001, 011, 101, and 111 Appendix B B.4 Using the circuit The number of transistors needed is 16 Answers B.8 The complete circuit is VDD Vx Vx Vx Vf B.12 Vx Vx Vx The required circuit is VDD VDD Vf Vx Vy Vz 837 838 Answers B.14 B.17 B.25 B.28 B.32 B.45 (a) ID = 800 µA (b) ID = 78 µA (a) NM H = 0.5 V NM L = 0.7 V RDS = 947 ! (a) PNOT_gate = 163 µW (b) Ptotal = 8.2 W NM L = 0.2 V The two NMOS transistors in a CMOS NOR gate are connected in parallel The worst case current to drive the output low happens when only one of these transistors is turned “ON” Thus each transistor has to have the same dimensions as the NMOS transistor in the inverter, namely Wn /Ln = The two PMOS transistors are connected in series If each of these transistors had the ratio Wp /Lp , then the two transistors could be thought of as one transistor with a Wp /2Lp ratio Thus each PMOS transistor must be made twice as wide as that in the inverter, namely Wn /Ln = f = x2 + x1 x3 The corresponding circuit is x1 x3 x2 B.55 (b) VOL = 0.8 V 0 x1 x3 1 x2 + x1 x3 The circuit in Figure PB.11 is a two-input XOR gate This circuit has two drawbacks: when both inputs are the PMOS transistor must drive f to 0, resulting in f = VT volts Also, when x1 = and x2 = 0, the NMOS transistor must drive the output high, resulting in f = VDD − VT I N D E X A overflow, 143 (See also Addition; Division; Multiplication; Subtraction) Arithmetic and logic unit (ALU), 218 Arithmetic assignment (Verilog), 159 Array multiplier (see Multiplication) ASCII code, 14 ASIC, 5, 769 ASM chart (see Algorithmic state machine) Aspect ratio, 794 assign (Verilog), 70 Associative property, 35 Asynchronous clear (reset), 263 Asynchronous clear (in Verilog), 294, 718 Asynchronous counter, 269 Asynchronous inputs, 482 Asynchronous sequential circuit (see Sequential circuits) Axioms of Boolean algebra, 33 ABC system, 536 Absorption property, 35 Accumulator, 272 Active clock edge, 332 Active-low signal, 201 Adder: BCD, 176 carry lookahead, 146 carry-save array, 183 full-adder, 127 half-adder, 32, 125 in Verilog code, 152–163, 641 propagation delay, 129, 151 ripple-carry, 129 serial, 363 Adder/subtractor, 139 Addition, 32, 125 BCD, 174 carry, 125 generate function, 146 overflow, 143, 648 propagate function, 146 sum, 125 Verilog, 159–163 Address, 796 Aliasing problem in testing, 673 Algorithm, 441 Algorithmic state machine (ASM): ASM charts, 401 ASM block, 404 conditional output box, 402 decision box, 402 implied timing, 404 state box, 401 Alphanumeric characters, 14 Altera Corporation, always block (Verilog), 74, 698 Analog information, 16 Analysis, 29, 504 AND function, 23 AND gate (see Gates) And-or-invert cells, 807 AND plane (also AND array), 754 Anode terminal, 304 Arbiter circuit, 393, 571 Arithmetic: floating-point (see Floating point) operators (Verilog), 226 B Barrel shifter, 238, 687 BCD (see Binary-coded decimal), 96, 176 BCD-to-7-segment converter, 96 BDD (see binary decision diagram) BDD packages, 520 begin (Verilog), 156, 699 begin-end block (Verilog), 156, 699 Behavioral Verilog code, 70, 699 BGA package, 766 BILBO (Built-in Logic Block Observer), 673 Binary-coded decimal (BCD), 174 addition, 174 counter, 280 digits, 174 Binary decision diagram (BDD), 514 Binary numbers, 12 in Verilog code, 166, 687 Binary variable, 23 BIST (Built-in Self Test), 669 Bit, 12 Bit-counting circuit, 441 Bit-select (Verilog), 689 Bitwise operators (Verilog), 223 Blocking assignment (Verilog), 288, 700 Body effect, 785 Boolean algebra, 33 Boundary scan, 676 Branching heuristic, 91, 527 839 840 Index Buffer (see Driver) Bus, 422 Bypass capacitor, 677 Byte, 13 C CAD (see Computer aided design) Canonical expressions: canonical product-of-sums, 52 canonical sum-of-products, 49 Capacitance, 779 Carry: carry-in, 125 carry-out, 126 Carry chain, 645 Carry lookahead adder, 146 Carry-save adder, 183 case statement, 215, 702 casex statement, 220, 703 casez statement, 220, 703 Cathode terminal, 304 Channel (in MOSFET), 774 Character codes, 14 Characteristic impedance, 678 Characteristic table, 249 Chip configuration, 68 Circuit size, 764 Clear input, 260 Clock, 251 Clock divider, 304 Clock enable, 301 Clock network, 480 Clock skew, 312 Clock synchronization, 478 Clock-to-Q delay (tcQ ), 263 Clock-to-output time (tco ), 285 CMOS technology, 655 Code: BCD, 96 converter, 208 error-detecting, 241 Gray, 82, 235 One-hot, 201, 281 Cofactor, 198, 516 Coincidence operation, 128 Column dominance, 524 Combinational circuits, 190–242 Combining property, 35, 79 Comment (Verilog), 72 Commutative property, 35 Comparator, 208, 227 Compatible states, 581 Complement: diminished radix, 142 of a logic variable, 26 1’s, 133 radix, 139 2’s, 133 Complementary metal-oxide semiconductor (see CMOS technology) Complex gate (CMOS), 715 Complex programmable logic device (CPLD), 761 Compressor circuit, 671 Computer-aided design (CAD), 65 chip configuration, 68 design entry, 65 functional simulation, 67 layout synthesis (physical design), 67 logic synthesis (optimization), 67 technology mapping, 537, 640 timing simulation, 67 Concatenation (Verilog), 161, 227 Conditional operator (Verilog), 210 Consensus property, 40 Consistency check, 659 Constant (in Verilog), 166 Continuous assignment (Verilog), 70, 696 Control circuit, 422 Cost, 50, 89 Counter: asynchronous, 269 BCD, 280 down, 271 enable and clear capability, 274 Johnson, 283 modulo-n, 278 parallel load of, 276 reset of, 278 ring, 281 ripple, 271 synchronous, 272 up, 270 up/down, 272 Verilog code, 298–300, 721 Cover, 88 minimal, 88 table, 522 Critical path, 145, 310 Crossbar, 193 Cross-coupled gates, 249 Crosstalk, 677 Cubical representation, 510 Current flow: dynamic, 731 gate, 726 leakage, 777 short circuit, 784 static, 731 Custom chips, 5, 769 Cut-off region, 726 Cut set, 564 Index D D flip-flop (see Flip-flop) D-algorithm, 661 Datapath, 422 DC-set, 94 Debouncing, 483 Decimal numbers, 12 Decision tree, 514 Decoder, 201, 433 tree, 203 Decomposition (see Functional decomposition) default case alternative (Verilog), 215 defparam (Verilog), 163 Delay (see Propagation delay) Delay (in Verilog), 694, 698 DeMorgan’s theorem, 35, 42 Demultiplexer, 203 Design, Design entry, 65 Design for testability, 665 Design process, Digital hardware, Digital information, 16 Digital system, 422 Diminished radix complement, 142 Disjoint decomposition, 500 Distributive property, 35 Division, 455 Don’t-care condition, 94 in Verilog code, 704 Double precision (see Floating point) Down-counter, (see Counter) Drain (in MOSFET transistor), 735 Driver, 751, 791 inverting, 793 tri-state, 792 Duality, 34 Duty cycle, 489 Dynamic hazard, 609, 613 E Edge (in signals), 257 Edge-triggered, 256, 267 Electrically-erasable programmable read-only memory (EEPROM), 799 Enable input, 201, 274, 301 Encoder, 205 binary, 205 priority, 205 end (Verilog), 699 Energy (capacitor), 732 Equality operators (Verilog), 226 Equivalence: of logic expressions, 31 of states, 374 Equivalent-gates metric, 764 Erasable programmable read-only memory (EPROM), 801 Errors in Verilog code, 706 Escaped identifier, 687 Espresso, 536 Essential prime implicant, 89 Event expression (Verilog), 24, 703 Excess-127 format, 173 Excess-1023 format, 173 Excitation table, 388, 556 Exclusive-NOR (XNOR) gate (see Gates) Exclusive-OR (XOR) gate (see Gates) Expansion theorem (Shannon’s), 198, 515 F Factoring, 493 Fall time, 781 Fan-in, 151, 493, 788 Fan-out, 790 Fault: detection, 659 model, 654 propagation, 659 stuck-at, 654 Feedback, 248 Field-programmable gate array (FPGA), 5, 764, 804 Finite state machine (FSM), 333 incompletely specified, 381 summary of design procedure, 340 Fixed-point numbers, 170 Flip-flop, 258 Flip-flops: clear and preset inputs, 260 clock-to-Q delay (tcQ ), 263 configurable (in PLDs), 285 D, 256–262 edge-triggered, 256, 258, 267 JK, 264 hold time, 263 master-slave, 256, 558 setup time, 263 SR, 322 T, 263 Timing parameters, 263 Verilog code for, 288, 717 Floating gate, 799 Floating point, 172 double precision, 173 exponent, 172 format, 172 IEEE standard, 172 mantissa, 172 normalized, 172 representation, 172 single precision, 172 841 842 Index Flow table, 556 primitive, 578 state reduction, 577 Fmax , 310 for loop statement, 156, 221, 704 Fowler-Nordheim tunneling, 799 FPLA (see PLA) FSM (see Finite state machine) Full-adder, 127 function (Verilog), 231, 713 Functional behavior, 29 Functional decomposition, 493 Functional equivalence, 31 Functional simulation, 67 Fundamental mode, 552, 608 Fuse map, 720 G Gate (in MOSFET transistor), 735 Gate array, 770 Gate delay (see Propagation delay) Gate optimization, 638 Gated D latch, 253, 285, 717, 788 Gated SR latch, 251 Gates: AND, 27, 738 NAND, 54, 738, 741 NOR, 54, 738, 743 NOT, 27 OR, 27, 738 XNOR, 128 XOR, 32, 128 generate (Verilog), 157, 228, 712 genvar (Verilog), 157, 228, 712 Glitch, 561 Global signals, 480 Gray code, 82, 235 H H tree, 480 Half-adder, 32, 125 Hamming distance, 592 Handshake signaling, 571 Hardware description language (HDL), 65 Hazard, 556, 608 dynamic, 609, 613 static, 609 Heuristic approach, 90 Hexadecimal numbers, 123 Hierarchical design, 65 Hierarchical Verilog code, 163 High-level behavioral Verilog code, 309 High-impedance output, 220, 422 Hold time, 256, 263 Huntington’s postulates, 35 Hypercube, 513 I Identifier (Verilog), 687 IEEE, 65 IEEE standards (see Standards) if-else statement, 212, 700 Implicant, 87 Implied memory (Verilog), 286, 702 Incompletely specified FSM, 381 Incompletely specified functions, 94 initial block (Verilog), 699 Input variable, 23 Instantiation (of Verilog gates), 71, 110, 694 Instantiation (of Verilog modules), 76, 78, 164, 165, 709 Instrumentation, 679 In-system programming (ISP), 760 Integer: in Verilog, 159, 689 signed, 132 unsigned, 132 Integrated circuit (IC), International Technology Roadmap for Semiconductors (ITRS), Intersection, 38 Inversion, 26 Inverter (NOT gate), 27, 738 J JK flip-flop, 264 Johnson counter, 283 JTAG port, 764 K Karnaugh map, 79 k-cube, 513 k-successor, 374 L Large scale integration (LSI), 753 Latch: basic SR, 249 gated D, 253, 285 gated SR, 251 set-dominant SR, 322 Verilog code, 287, 717 Leakage current, 777 Least-significant bit, 13 LED (Light emitting diode), 304 Level-sensitive element, 254, 258 Level-sensitive scan design, 669 Index Libraries, 65 Linear feedback shift register (LFSR), 326, 670 Linear region (see Triode region) Literal, 87 Logic analyzer, 679 Logic block, 545 Logic circuit, 22, 29 Logic expression, 23 Logic functions, 23 AND, 27 NAND, 54 NOR, 54 NOT, 27 OR, 27 synthesis, 29 XNOR, 128 XOR, 128 Logic gates, 27 drive capability, 791 dynamic operation, 729 fall time, 781 fan-in, 493, 788 fan-out, 790 noise margin, 778 power dissipation, 731 propagation delay, 780 rise time, 781 transfer characteristic, 777 Verilog gates, 695 Logic network, 28 Logic values, 22 Logical operators (Verilog), 225 Logical product (AND), 43 Logical sum (OR), 43 Lookup table (LUT), 766 Loop statement (see for loop) M Macrocell, 758 Magnitude, 132 Majority function, 115 Master (see Flip-flop, master-slave) Master-slave (see Flip-flop) Maxterm, 52 Mealy FSM, 332, 349 Verilog code, 363, 724 Mealy output, 402 Mean operation, 466 Medium-scale integration (MSI), 753 Memory, 795 implied memory (Verilog), 286, 436, 702, 690 Merger diagram, 581 Merging, 578 procedure, 581 Metal-oxide semiconductor, 734 Metastability, 263, 483 Minimization: of logic functions, 89 of states, 372, 577 Minterm, 48 Mixed logic, 748 module (Verilog), 70, 692 Moore FSM, 332 Verilog code, 355, 723 Moore output, 401 Moore’s law, MOSFET transistor, 734 on-resistance, 776 Most-significant bit, 13 Motherboard, Multibit assignment (in Verilog), 160 Multilevel circuits, 492, 502 Multiple-output circuits, 96 Multiplexer, 62, 190 Multiplexer (Verilog code), 211 Multiplication, 167 array implementation, 167 carry-save array, 183 partial product, 167 sequential implementation, 446 signed-operand, 169 Mutual exclusion element (ME), 577 N Named port connection, 165, 709 Names (Verilog), 687 NAND circuits, 502, 738, 741 NAND gate (see Gates) n-cube, 513 Negative edge, 257 Negative logic, 733, 747 Negative numbers, 133 negedge (Verilog), 287, 717 Net (in Verilog), 158, 686, 688 Network, 27 Next state, 336, 552 Nibble, 13 9’s complement, 140 NMOS technology, 736 NMOS transistor, 734 Noise, 778 margin, 778 power supply, 677 Non-blocking assignment (Verilog), 289, 700 Non-disjoint decomposition, 500 Nonvolatile programming, 764 NOR gate (see Gates) NOR circuits, 502, 738, 741 NOR plane, 798 NOT function, 27 843 844 Index NOT gate (see Gates) Number conversion, 13 Number representation: binary coded decimal, 174 fixed-point, 170 floating-point, 172 hexadecimal, 123 octal, 123 1’s-complement, 133 positional notation, 122 sign and magnitude, 133 signed integer, 132 10’s-complement, 140 2’s-complement, 133 unsigned integer, 122 in Verilog, 166, 687 O Octal numbers, 123 Odd function, 128 One-hot encoding, 203, 281, 347, 607 1’s-complement representation, 133 1149.1 Standard, 676 On-resistance, 776 ON-set, 534 Operations (see Logic functions) Operators (Verilog), 223, 690 Optimization (see Minimization) OR function, 23 OR gate (see Gates) OR plane, 754 Ordered port connection, 165, 709 Ordering of statements, 292 Oscilloscope, 679 Output delay time (tod ), 481 Overflow (see Arithmetic overflow) P Packages (physical): ball grid array (BGA), 766 dual inline (DIP), 749 pin grid array (PGA), 765 plastic-leaded chip carrier (PLCC), 763 quad flat pack (QFP), 762 small-outline integrated circuit (SOIC), 751 PAL, 757 Parallel-to-serial converter, 268, 415 Parallel transfer, 267 parameter (Verilog), 156, 688 Parasitic capacitance, 780 Parity, 240, 413, 565 Partial product, 167 Part-select (Verilog), 689 Pass transistor, 804 Path sensitizing, 657 Physical design, 644 Pins, 646 PLA, 754, 799 Placement, 646, 676 PLD, 5, 753 PMOS transistor, 734 Polysilicon, 772 Port (Verilog), 70, 692 Portability, 66 posedge (Verilog), 287, 717 Positional number representation, 12, 122 Positive logic, 733 Power dissipation, 782 Precedence of operations, 43 Present state, 336, 552 Preset input, 260 Price/performance ratio, 145 Prime implicant, 88 Primitive flow table, 578 Printed circuit board (PCB), 3, 676 Priority: encoder, 205 in Verilog code, 221, 223 Procedural statements (Verilog), 74, 698 Process transconductance parameter, 774 Processor, 432 Product-of-sums form (POS), 52 Programmable array logic (see PAL) Programmable logic array (see PLA) Programmable logic device (see PLD) Programmable ROM (PROM), 768 Propagation delay, 67, 129, 151 Properties of Boolean algebra, 34 Pseudo-NMOS technology, 777 Pseudorandom tests, 670 Pseudorandom binary sequence generator (PRBSG), 670 Pull-down network, 473 Pull-up network, 473 Pull-up resistor, 738 Pulse mode, 552 Q Quine-McCluskey method, 521 R Race condition, 567 Radix complement, 139 RAM (see Static random access memory) Random testing, 662 Read-only memory (ROM), 804 Reaction timer, 302 Reduction operators (Verilog), 225 Reflections, 677 Index reg (Verilog), 156, 689 Register, 267 Verilog code, 295, 718 Register-Transfer Level (RTL) code, 309, 726 Relational operators (Verilog), 226 Reliability, 679 Replication operator (Verilog), 167, 227 Reset input, 335 Reset state, 335 Resistance (transistor channel), 776 Ring counter, 281 Ring Oscillator, 324 Ripple-carry adder, 129 Ripple counter, (see Counter) Rise time, 781 ROM (see Read only memory) Routing, 647, 677 channel, 769 Row dominance, 523 S Saturation region, 774 Scalar (Verilog), 159, 688 Scan path, 666 Schematic, 27 Schematic capture, 65, 151 Sea-of-gates technology, 771 Semiconductor, 772 Semi-custom chips, Sensitivity list (Verilog), 74, 699 Sequence detector, 341 Sequential circuits, 248, 332 analysis, 397, 556 asynchronous, 551–630 definition of, 332 excitation table, 388 finite state machine, 333 flow table, 556 formal model, 405 merger diagram, 581 reset, 335 state, 332 state assignment, 336, 344, 592 state assignment in Verilog, 361 state diagram, 334 state reduction, 372, 577 state table, 335 synchronous, 332–415 testing, 665 transition diagram, 595 Sequential statement (Verilog), 698 Serial adder, 363 Serial parity generator, 565 Serial transfer, 267 Series-to-parallel converter, 268 Set input, 260 Setup time, 256, 263 7400-series chips, 749 7-segment display, 63 BCD-to-7-segment converter, 96 hex-to-7-segment converter, 208 Shannon’s expansion, 198, 515 Sharp-operation (#-operation), 529 Shift operators (Verilog), 226 Shift register, 267 Verilog code, 295, 720 Sign bit, 132 Signal value (Verilog), 687 Sign-and-magnitude representation, 133 Signature, 671 Signature analysis, 675 Sign extension, 167, 697 Signed numbers, 132 Silicon wafer, Simplification (see Minimization) Simulation, 67 Single-precision (see Floating point) Skew (see Clock skew) Slack (timing), 649 Slave (see Flip-flop, master-slave) Small-scale integration (SSI), 753 Socket, 760 Sort operation, 470 Source (in MOSFET transistor), 735 SR latch (see Latch) Stable state, 552 Standard cells, 769 Standard chips, Standards: IEEE floating-point, 172 1149.1 (Testing), 676 Verilog 1364-1995, 68 Verilog 1364-2001, 68 VHDL, 65 Star-operation (∗-operation), 529 Starting state, 334 State, 248, 332 assignment, 336, 344, 592, 607 assignment in Verilog, 361 compatibility, 581 diagram, 334 equivalence, 374 reduction, 372, 577 definition of, 332 table, 335 variables, 336 State-adjacency diagram, 595 State-assigned table, 337 State machine (see Finite state machine) Static hazard, 609 Static random access memory (SRAM), 794 845 846 Index Structural Verilog code, 70 Stuck-at fault, 654 Substrate, 734 Subtraction, 137 Sum, 125 Sum-of-products form (SOP), 49 Synchronize (to clock), 482 Synchronous clear, 263 Synchronous clear (Verilog), 294, 718 Synchronous counter, 272 Synchronous sequential circuits (see Sequential circuits) Synthesis, 29, 45 multilevel, 492 T T flip-flop, 263 tcQ , 263, 310 tco , 285 th , 256, 263 tsu , 256, 263 task (Verilog), 229, 715 Technology mapping, 537 10’s complement, 140 Terminal node (in BDD), 514 Terminations, 678 Test, 654 Test generation, 656–665 Test set, 655 Test vectors (see Test generation) Testing, 653–680 Theorems of Boolean algebra, 34 Three-state output (see Tri-state) Threshold voltage, 733, 774 Timer, 488 Timing analysis, 310, 320, 648 Timing Analyzer, 648 Timing constraints, 649 Timing diagram, 29, 339 Timing simulation, 67 Transfer characteristic, 777 Transistor: EEPROM, 799 EPROM, 801 MOSFET, 734 size, 773 Transition diagram, 595 Transition table (see Excitation table) Transmission gate, 786 Transmission line effects, 678 Triode region, 774 tri (Verilog), 427 Tri-state: driver, 792 Verilog code, 427 Truth table, 26 2’s-complement representation, 133 U Union, 39 Unsigned numbers, 122 Unstable state, 561 Up-counter (see Counter) Up/down-counter (see Counter) User-programmable device (see PLD) Universal shift register, 323 Valuation, 26 Variable, 23 in Verilog, 75, 159, 689 Vector (Verilog), 155, 688 Venn diagram, 37 Verilog HDL, 685–729 assign keyword, 70 asynchronous clear, 294, 718 always block, 74, 698 arithmetic assignment, 159 arithmetic operators, 226 blocking assignment, 288, 700 begin-end block, 156, 699 bit-select, 689 bitwise operators, 223 case statement, 215, 702 casex statement, 220, 703 casez statement, 220, 703 comment, 72, 686 concatenation, 167, 227 concurrent statement, 696 conditional operator, 210 constant, 166 continuous assignment, 70, 696 default case alternative, 215 defparam, 163 delay, 694, 698 don’t care, 220 end, 699 equality operators, 226 escaped identifier, 687 for loop, 156, 221, 704 function, 231, 713 gate level primitives, 694 generate, 157, 228, 712 genvar, 157, 228, 712 hierarchical code, 163 identifier, 687 if-else statement, 212, 700 implied memory, 286, 702 initial block, 699 integer type, 159, 689 instantiation of gates, 71, 110, 694 instantiation of modules, 76, 78, 164, 165, 709 VQMPBEFECZ logic gates, 695 logical operators, 225 memories, 690 module, 70, 692 multibit assignment, 160 named port connection, 165, 709 names, 687 negedge, 287, 717 net, 158, 686, 688 non-blocking assignment, 289, 700 number representation, 166, 687 operators, 223, 690 ordered port connection, 165, 709 parameter, 156, 688 parameter override, 163, 710 part-select, 689 posedge, 287, 717 precedence, 228 procedural statements, 74, 698 port, 70, 692 radix, 687 range, 686, 689 reduction operators, 225 reg, 156, 689 relational operators, 226 repeat loop, 706 replication, 167, 227 scalar, 159 sensitivity list, 74, 699 # operator, 163 shift operators, 226 Index sign extension, 167, 697 signal, 686 signal value, 687 synchronous clear, 294, 718 task, 229, 715 tri type, 689 truth tables, 704 variable, 75, 159, 689 vector, 155, 689 while loop, 706 white space, 686 wire type, 78, 158, 688 Vertex, 510 Very large-scale integration (VLSI), 753 VHDL, 65 Via, 769 Volatile programming, 768 Voltage levels substrate bias, 785 high, low, 734, 776 Voltage transfer characteristic, 777 W while loop (Verilog), 706 wire (Verilog), 78, 158, 688 X XNOR (Exclusive-NOR) gate (see Gates) XOR (Exclusive-OR) gate (see Gates) 847