Multiplier architectures and algorithms

Multiplier Architectures and Algorithms Digital Circuits Design with HDL Course CE Undergraduate – 1st, 2010 2011 Multiplier Architectures and Algorithms Pham Quoc Cuong http //www cse hcmut edu vn/~c[.]

Digital Circuits Design with HDL Course CE Undergraduate – 1st, 2010-2011 Multiplier Architectures and Algorithms Pham Quoc Cuong http://www.cse.hcmut.edu.vn/~cuongpham CE Undergraduate – 1st, 2010-2011 Digital Circuits Design with HDL Course Combinational Binary Multiplier Multiplicand 1 1 1 21510 Multiplier 0 1 1 2310 Shift copies of the multiplicand 1 1 1 1 1 1 1 1 1 1 1 1 Double shift 0 1 1 0 494510 • A combinational Circuit can be developed to implement the product • Require hardware with multiple adders for each column • Ordinary adder operates on only two words at a time Multiplier Algorithms and Architectures 24/12/2010 Pham Quoc Cuong CE Undergraduate – 1st, 2010-2011 Digital Circuits Design with HDL Course Combinational Binary Multiplier Multiplicand 1 1 1 21510 Multiplier 2310 0 1 1 Accumulated Partial Products 1 1 1 Shift copies of the multiplicand 1 1 1 1 0 0 1 1 1 1 1 1 0 0 Double shift 1 1 1 0 1 1 0 494510 • Combinational Binary Multiplier operate fast, but require a significant amount of silicon area Multiplier Algorithms and Architectures 24/12/2010 Pham Quoc Cuong CE Undergraduate – 1st, 2010-2011 Digital Circuits Design with HDL Course Sequential Binary Multiplier • Choose a data-path architecture • Design state machine for controller Word1 [-:0] Word2 [-:0] 15 Start Clock Reset Sequential Binary Multiplier Ready Products [-:0] 0 0 0 0 0 0 0 16 + 15 0 0 0 product 0 1 0 multiplier 1 1 multiplicand Datapath architecture of sequential 8-bit multiplier Interface signals and block diagram Multiplier Algorithms and Architectures 24/12/2010 Pham Quoc Cuong CE Undergraduate – 1st, 2010-2011 Digital Circuits Design with HDL Course Register transfers product multiplier 0 0 0 0 0 1 0 15 0 0 0 0 0 0 0 0 multiplicand 0 0 0 0 0 1 1 1 0 0 0 0 1 1 1 Shift Multiplicant 0 0 0 1 1 1 0 0 0 1 0 0 1 0 0 0 1 1 1 0 0 0 1 1 0 0 0 0 1 1 1 0 0 1 Shift Multiplicant 0 Shift Multiplicant + + + Not add Multiplier Algorithms and Architectures 24/12/2010 Pham Quoc Cuong CE Undergraduate – 1st, 2010-2011 Digital Circuits Design with HDL Course Structural Units • Top-level module: Multiplier_STG_0 • m0: LSB of Multiplier, used to control state transaction word1 word2 Load_words Start Shift m0 Add Controller Datapath Clock Reset m0 Ready Multiplier Algorithms and Architectures 24/12/2010 Product Pham Quoc Cuong CE Undergraduate – 1st, 2010-2011 Digital Circuits Design with HDL Course STGs for 4-bit Seq Multiplier !Reset/ Ready !Reset/ Ready Reset S_Idle Start/Load_word, Ready S_1 [0]/Add S_8 Ready ![0] Start/Load_word, Ready S_2 ![0]/shift [0]/Add S_7 Start/Load_word, Ready S_1 [0]/Add S_8 Ready ![0] -/Shift Reset S_Idle S_2 ![0]/shift [0]/Add -/Shift S_7 S_3 -/Shift ![0]/Shift ![0]/Shift S_3 -/Shift ![0]/Shift ![0]/Shift [0]/Add S_6 S_4 [0]/Add [0]/Add S_6 S_5 [0]/Add -/Shift Multiplier Algorithms and Architectures S_4 24/12/2010 S_5 -/Shift Pham Quoc Cuong Digital Circuits Design with HDL Course CE Undergraduate – 1st, 2010-2011 Module Decleration module Multiplier_STG_0 (product, Ready, word1, word2, Start, clock, reset); parameter L_word = 4; // Datapath size output [2*L_word -1: 0] product; output Ready; input [L_word -1: 0] word1, word2; input Start, clock, reset; wire m0, Load_words, Shift; Datapath M1 (product, m0, word1, word2, Load_words, Shift, Add, clock, reset); Controller M2 (Load_words, Shift, Add, Ready, m0, Start, clock, reset); endmodule Multiplier Algorithms and Architectures 24/12/2010 Pham Quoc Cuong Digital Circuits Design with HDL Course CE Undergraduate – 1st, 2010-2011 Controller (1) module Controller (Load_words, Shift, Add, Ready, m0, Start, clock, reset); parameter L_word = 4; // Datapath size parameter L_state = 4; // State size output Load_words, Shift, Add, Ready; input m0, Start, clock, reset; reg [L_state -1: 0] state, next_state; parameter S_idle = 0, S_1 = 1, S_2 = 2; parameter S_3 = 3, S_4 = 4, S_5 = 5, S_6 = 6; parameter S_7 = 7, S_8 = 8; reg Load_words, Shift, Add; wire Ready = ((state == S_idle) && !reset) || (state == S_8); always @ (posedge clock or posedge reset) // State transitions if (reset) state