design course vlsi lecture notes ch3-5

ECE 410, Prof. A. Mason Lecture Notes Page 3.1 Review: CMOS Logic Gates • NOR Schematic x x y g(x,y) = x y x x y g(x,y) = x + y •NAND Schematic • parallel for OR • series for AND • INV Schematic + Vgs - Vout Vin pMOS nMOS + Vsg - = Vin • CMOS inverts functions • CMOS Combinational Logic • use DeMorgan relations to reduce functions • remove all NAND/NOR operations • implement nMOS network • create pMOS by complementing operations • AOI/OAI Structured Logic • XOR/XNOR using structured logic ECE 410, Prof. A. Mason Lecture Notes Page 3.2 Review: XOR/XNOR and TGs •Exclusive-OR (XOR) –a ⊕ b = a • b + a • b •Exclusive-NOR –a ⊕ b = a • b + a • b • Transmission Gates • MUX Function using TGs b a b a XOR/XNOR in AOI Form y = x s, for s=1 F = Po • s + P1 • s ECE 410, Prof. A. Mason Lecture Notes Page 3.3 CMOS Technology • Properties of microelectronic materials – resistance, capacitance, doping of semiconductors • Physical structure of CMOS devices and circuits – pMOS and nMOS devices in a CMOS process – n-well CMOS process, device isolation • Fabrication processes • Physical design (layout) – layout of basic digital gates, masking layers, design rules –LOCOS process – planning complex layouts (Euler Graph and Stick Diagram) Part I: CMOS Technology ECE 410, Prof. A. Mason Lecture Notes Page 3.4 Integrated Circuit Layers • Integrated circuits are a stack of patterned layers – metals, good conduction, used for interconnects – insulators (silicon dioxide), block conduction – semiconductors (silicon), conducts under certain conditions • Stacked layers form 3-dimensional structures • Multi-layer metals – background assumed to be silicon covered by silicon dioxide silicon silicon dioxide Part I: CMOS Technology ECE 410, Prof. A. Mason Lecture Notes Page 3.5 Interconnect Parasitics • Parasitic = unwanted natural electrical elements • Metal Resistance – metals have a linear resistance and obey Ohm’s law •V = IR – generate parasitic interconnect resistance, R line •R line = l = ρ l –A = wt – ρ = resistivity, σ = conductivity – defined by sheet resistance • Rs = 1 = ρ , resistance per unit length [ohms, Ω] •Rline= Rs l , Rs determined by process, l & w by designer σA A l t w σ t t w Rline = Rs when l = w Part I: CMOS Technology ECE 410, Prof. A. Mason Lecture Notes Page 3.6 Metal Resistance: Measuring ‘squares’ • From top view of layout, can determine how many ‘squares’ of the layer are present – ‘square’ is a unit length equal to the width –R line = Rs n, where n = l is the number of ‘squares’ – Get a unit of resistance, Rs, for each square, n. l w w w n = 8 Part I: CMOS Technology ECE 410, Prof. A. Mason Lecture Notes Page 3.7 Parasitic Line Capacitances • Capacitor Basics –Q = CV, C in units of Farads [F] –I = C d V/ d t • Parallel plate capacitance –C line = ε ox wl [F], w l = Area – ε ox = permittivity of oxide • ε ox = 3.9 ε o • ε o = 8.85X10 -14 [F/cm] •RC time constant of an interconnect line – τ = R line C line t ox Part I: CMOS Technology ECE 410, Prof. A. Mason Lecture Notes Page 3.8 Electrical Properties of Silicon • Silicon is a semiconductor… does it conduct or insulate? –doping= adding impurities (non-silicon) to Si: will be covered later • doping concentration and temperature determine resistivity • Conduction/Resistance – generally, the Si we see in CMOS is doped • at room temp., doped silicon is a weak conductor = high resistance • Capacitance – doped, room temp. Si is conductive –conduction Æ free charge carriers Æ no electric field Æ no capacitance (within bulk silicon) – exception: if free carries are removed (e.g., depletion layer of a diode) silicon becomes an insulator with capacitance Part I: CMOS Technology ECE 410, Prof. A. Mason Lecture Notes Page 3.9 Conduction in Semiconductors -Review • Intrinsic (undoped) Semiconductors – intrinsic carrier concentration ≡ n i = 1.45x10 10 cm -3 , at room temp. – n = p = n i , in intrinsic (undoped) material •n ≡ number of electrons, p ≡ number of holes – mass-action law, np = n i 2 applies to undoped and doped material • Extrinsic (doped) Semiconductors – dopants added to modify material/electrical properties P BP B + + + + - - group V element group III element ion electron hole n-type Donor p-type Acceptor ion free carrier free carrier •n-type (n+), add elements with extra an electron –N d ≡ conc. of donor atoms [cm -3 ] –n n = N d , n n ≡ conc. of electrons in n-type material –p n = n i 2 /N d , using mass-action law, –p n ≡ conc. of holes in n-type material –always a lot more n than p in n-type material •p-type = p+, add elements with an extra hole –N a ≡ concentration of acceptor atoms [cm -3 ] –p p = N a , p p ≡ conc. of holes in p-type material –n p = ni 2 /N a , using mass-action law, –n p ≡ conc. of electrons in p-type material –always a lot more p than n in p-type material Part I: CMOS Technology ECE 410, Prof. A. Mason Lecture Notes Page 3.10 Conduction in Silicon Devices • doping provides free charge carriers, alters conductivity • conductivity in semic. w/ carrier densities n and p – σ = q(μ n n + μ p p) •q≡ electron charge, q = 1.6x10 -19 [Coulombs] • μ≡mobility [cm 2 /V-sec], μ n ≅ 1360, μ p ≅ 480 (typical values in bulk Si) • in n-type region, n n >> p n – σ≈qμ n n n • in p-type region, p p >> n p – σ≈qμ p p p • resistivity, ρ = 1/σ • Can now calculate the resistance of an n+ or p+ region μ n > μ p electrons more mobile than holes conductivity of n+ > p+ Mobility often assumed constant but is a function of Temperature and Doping Concentration Part I: CMOS Technology [...]... Prof A Mason in out Lecture Notes Page 3.26 Design Rules: Intro Part II: Layout Basics • Why have Design Rules – fabrication process has minimum/maximum feature sizes that can be produced for each layer – alignment between layers requires adequate separation (if layers unconnected) or overlap (if layers connected) – proper device operation requires adequate separation • “Lambda” Design Rules – lambda,... lambda, λ, = 1/2 minimum feature size, e.g., 0 6μm process -> λ =0.3μm – can define design rules in terms of lambdas • allows for “scalable” design using same rules • Basic Rules – minimum layer size/width – minimum layer separation – minimum layer overlap ECE 410, Prof A Mason Lecture Notes Page 3.27 Part II: Layout Basics Design Rules: 1 • n-well MOSIS SCMOS rules; λ =0.3μm for AMI C5N – required everywhere... active poly gate contacts (active & gate) metal1 via metal2 ECE 410, Prof A Mason Lecture Notes Page 3.16 Part I: CMOS Technology CMOS Cross Section View • Cross section of a 2 metal, 1 poly CMOS process Typical MOSFET Device (nMOS) • Layout (top view) of the devices above (partial, simplified) ECE 410, Prof A Mason Lecture Notes Page 3.17 Inverter Layout Part II: Layout Basics • Features – VDD & Ground... CMOS process flow – should be viewed as a slide show, not designed for printing ECE 410, Prof A Mason Lecture Notes Page 3.19 Series MOSFET Layout Part II: Layout Basics • Series txs – 2 txs share a S/D junction • Multiple series transistors – draw poly gates side-by-side ECE 410, Prof A Mason Lecture Notes Page 3.20 Parallel MOSFET Layout Part II: Layout Basics • Parallel txs – one shared S/D junction... layout strategy – horizontal gates ECE 410, Prof A Mason Lecture Notes Page 3.21 Part II: Layout Basics NAND/NOR Layouts • One layout option with horizontal transistors (L runs horizontally) – ignore the size (W) for now 2-input NAND 2-input NOR pMOS 2 parallel tx pMOS 2 series tx nMOS 2 series txs nMOS 2 parallel txs ECE 410, Prof A Mason Lecture Notes Page 3.22 Layout Cell Definitions • Cell Pitch =... boundary to avoid breaks in higher level cells ECE 410, Prof A Mason Lecture Notes Page 3.24 Part II: Layout Basics Layout CAD Tools • Layout Editor – draw multi-vertices polygons which represent physical design layers – Manhattan geometries, only 90º angles • Manhattan routing: run each interconnect layer perpendicular to each other • Design Rules Check (DRC) – checks rules for each layer (size, separation,... A Mason Lecture Notes Page 3.12 Lower CMOS Layers Part I: CMOS Technology • Visible Features – – – – – – p-substrate n-well n+ S/D regions p+ S/D regions gate oxide polysilicon gate • Mask Layers active – n-well – active (S/D regions) p+ • active = not FOX – n+ doping – p+ doping – poly patterning n+ • gate oxide aligned to gate poly, no oxide mask ECE 410, Prof A Mason poly n-well Lecture Notes Page... same mask layer (active) • different layout layers help differentiate nMOS/pMOS ECE 410, Prof A Mason Lecture Notes Page 3.14 Part I: CMOS Technology CMOS Device Dimensions • Physical dimensions of a MOSFET – L = channel length – W = channel width • Side and Top views ECE 410, Prof A Mason Lecture Notes Page 3.15 Upper CMOS Layers Part I: CMOS Technology • Cover lower layers with oxide insulator, Ox1... insulator called Field Oxide, FOX ECE 410, Prof A Mason Lecture Notes Page 3.35 Part III: Fabrication Overview of CMOS Fabrication Topics: •Wafer Growth •Photolithography •Doping •Diffusion •Implantation •Oxidation •Deposition •Dielectric •Polysilicon •Metals •Etching •Chemical •Chemical-Mechanical •Mechanical •Epitaxial Growth ECE 410, Prof A Mason Lecture Notes Page 3.36 ... 5λ • Active – required everywhere a transistor is needed – any non-Active region is FOX – rules • minimum width 3λ • minimum separation to other Active ECE 410, Prof A Mason 3λ Lecture Notes Page 3.28 Part II: Layout Basics Design Rules: 2 • n/p Select – – – – defines regions to be doped n+ and p+ tx S/D = Active AND Select NOT Poly tx gate = Active AND Select AND Poly rules 2λ • minimum overlap of . Rs determined by process, l & w by designer σA A l t w σ t t w Rline = Rs when l = w Part I: CMOS Technology ECE 410, Prof. A. Mason Lecture Notes Page 3.6 Metal Resistance: Measuring. Mason Lecture Notes Page 3.15 CMOS Device Dimensions • Physical dimensions of a MOSFET –L = channel length –W = channel width • Side and Top views Part I: CMOS Technology ECE 410, Prof. A. Mason Lecture. CMOS process flow – should be viewed as a slide show, not designed for printing Part II: Layout Basics ECE 410, Prof. A. Mason Lecture Notes Page 3.20 Series MOSFET Layout •Series txs – 2 txs