VHDL and verilog user manual

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VHDL and Verilog Simulation User Manual Version 7.2 Technical Support Line: 1- 800-LATTICE or (408) 428-6414 pDS1131-UM Rev 7.2.1 Copyright This document may not, in whole or part, be copied, photocopied, reproduced, translated, or reduced to any electronic medium or machine-readable form without prior written consent from Lattice Semiconductor Corporation The software described in this manual is copyrighted and all rights are reserved by Lattice Semiconductor Corporation Information in this document is subject to change without notice The distribution and sale of this product is intended for the use of the original purchaser only and for use only on the computer system specified Lawful users of this product are hereby licensed only to read the programs on the disks, cassettes, or tapes from their medium into the memory of a computer solely for the purpose of executing them Unauthorized copying, duplicating, selling, or otherwise distributing this product is a violation of the law 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period, contact Lattice Semiconductor Corporation at: Phone: 1-800-LATTICE Fax: (408) 944-8450 E-mail: applications@latticesemi.com If the Lattice Semiconductor support personnel are unable to solve your problem over the phone, we will provide you with instructions on returning your defective software to us The cost of returning the software to the Lattice Semiconductor Service Center shall be paid by the purchaser Limitations on Warranty Any applicable implied warranties, including warranties of merchantability and fitness for a particular purpose, are hereby limited to ninety days from the date of purchase and are subject to the conditions set forth herein In no event shall Lattice Semiconductor be liable for consequential or incidental damages resulting from the breach of any expressed or implied warranties Purchaser’s sole remedy for any cause whatsoever, regardless of the form of action, shall be limited to the price paid to Lattice Semiconductor for the Lattice Semiconductor software The provisions of this limited warranty are valid in the United States only Some states not allow limitations on how long an implied warranty lasts, or exclusion of consequential or incidental damages, so the above limitation or exclusion may not apply to you This warranty provides you with specific legal rights You may have other rights that vary from state to state VHDL and Verilog Simulation User Manual Table of Contents Preface What Is In This Manual Where to Look for Information Documentation Conventions Related Documentation Lattice Semiconductor Cadence Mentor Viewlogic Synopsys IEEE OVI Model Technology Inc Frontline PureSpeed 10 10 12 13 13 13 13 13 13 13 14 14 14 Part I: VHDL Simulation 15 Chapter Introduction to VHDL Simulation 16 VHDL Directory Structure The VHDL Simulation Library Directory Structure on the UNIX Platform Examples Directory Library Directory The VHDL Simulation Library Directory Structure on the PC Platform Examples Directory Library Directory VHDL Simulation Libraries VHDL Functional Simulation Library VHDL Timing Simulation Library VHDL Module Simulation Library VHDL Functional Simulation Overview Functional Simulation Steps Functional Simulation Process Flow VHDL Timing Simulation Overview VHDL Timing Simulation Steps VHDL Timing Simulation Process Flow VHDL and Verilog Simulation User Manual 17 17 18 18 20 20 21 22 22 23 23 24 25 26 27 27 28 Chapter VHDL Simulation with Cadence Leapfrog 29 Cadence Leapfrog Simulation Library Environment Prerequisites Environment Setup Files for Schematic Capture Files for Schematic to VHDL Conversion Files for Simulations and Library Compilation Library Compilation VHDL Functional Library Compilation VHDL VITAL Timing Library Compilation VHDL Module Simulation Library Compilation VHDL Functional Simulation with Cadence LeapFrog Functional Simulation Steps Command-Line Quick Reference List Schematic to VHDL Design Conversion Command Design Compilation Command Functional Simulation Command VHDL Timing Simulation with Cadence LeapFrog Timing Simulation Steps Command-Line Quick Reference List VHDL Netlist Generation Command Design Elaboration Command Device-Specific Notes for Timing Simulation GXRESET XTEST_OE 30 30 30 30 31 32 33 33 33 34 35 35 36 36 36 36 37 37 38 38 38 40 40 40 Chapter VHDL Simulation with Mentor Graphics QuickVHDL 41 Mentor Graphics QuickVHDL Simulation Library Environment Prerequisites Environment Setup Files for Schematic Capture Files for Schematic to VHDL Conversion Files for Simulation and Library Compilation Library Compilation VHDL Functional Library Compilation VHDL VITAL Timing Library Compilation VHDL Module Simulation Library Compilation VHDL Functional Simulation with Mentor Graphics QuickVHDL Functional Simulation Steps Command-Line Quick Reference List Schematic to VHDL Design Conversion Command Work Library Creation Command Design Compilation Command Functional Simulation Command VHDL Timing Simulation with Mentor Graphics QuickVHDL Timing Simulation Steps Command-Line Quick Reference List Design Compilation Command VHDL and Verilog Simulation User Manual 42 42 42 42 42 43 44 44 44 45 46 46 47 47 47 47 47 48 48 49 49 Timing Simulation Command Device-Specific Notes for Timing Simulation GXRESET XTEST_OE 49 51 51 51 Chapter VHDL Simulation with Synopsys VSS 52 Synopsys VSS Simulation Library Environment Prerequisites Environment Setup Files for Simulation and Library Compilation Library Compilation VHDL Functional Library Compilation VHDL VITAL Timing Library Compilation VHDL Module Simulation Library Compilation VHDL Functional Simulation with Synopsys VSS Functional Simulation Steps VHDL Timing Simulation with Synopsys VSS Timing Simulation Steps Command-Line Quick Reference List Design Compilation Command Timing Simulation Command Device-Specific Notes for Timing Simulation GXRESET XTEST_OE 53 53 53 53 54 54 55 56 57 57 58 58 59 59 59 61 61 61 Chapter VHDL Simulation with Viewlogic Vantage 62 Viewlogic Vantage Simulation Library Environment Prerequisites Environment Setup Library Compilation VHDL Functional Library Compilation VHDL Functional Simulation with Viewlogic Vantage Functional Simulation Steps Command-Line Quick Reference List Schematic to VHDL Design Conversion Command Work Library Creation Command Design Compilation Command Functional Simulation Command VHDL Timing Simulation with Viewlogic Vantage Timing Simulation Steps Command-Line Quick Reference List Work Library Creation Command Design Compilation Command Functional Simulation Command Device-Specific Notes for Timing Simulation GXRESET XTEST_OE VHDL and Verilog Simulation User Manual 63 63 63 65 65 66 66 67 67 67 67 67 68 68 69 69 69 69 70 70 70 Chapter VHDL Simulation with Model Technology V-System/VHDL 71 Model Technology V-System Simulation Library Compilation VHDL Functional Library Compilation Steps: VHDL Timing Library Compilation Steps VHDL Module Simulation Library Compilation Steps VHDL Functional Simulation Using Model Technology Functional Simulation Steps VHDL Timing Simulation using Model Technology V-System Timing Simulation Steps Command-Line Quick Reference List Timing Simulation Command Device-Specific Notes for Timing Simulation GXRESET XTEST_OE 72 72 72 73 74 75 76 77 79 79 79 79 79 Chapter VHDL Simulation with Viewlogic Speedwave 80 Viewlogic Speedwave Simulation Library Environment Prerequisites Library Compilation VHDL Functional Library Compilation Steps VHDL Timing Library Compilation Steps VHDL Module Simulation Library Compilation Steps VHDL Functional Simulation Using Viewlogic Speedwave Functional Simulation Steps VHDL Timing Simulation using Viewlogic Speedwave Timing Simulation Steps Device-Specific Notes for Timing Simulation GXRESET XTEST_OE 81 81 82 82 82 83 84 84 85 85 87 87 87 Part II: Verilog Simulation 88 Chapter Introduction to Verilog Simulation 89 Verilog Directory Structure Examples Directory Library Directory Verilog Simulation Libraries Verilog Functional Simulation Library Verilog Timing Simulation Library Verilog Module Simulation Library Verilog Functional Simulation Overview Verilog Timing Simulation Overview VHDL and Verilog Simulation User Manual 90 90 90 91 91 91 91 92 93 Chapter Verilog Simulation with Cadence Verilog-XL 94 Verilog Functional Simulation with Cadence Verilog-XL Functional Simulation Steps Test Fixture File Verilog Netlist Creation Command-Line Quick Reference List Functional Simulation Command Verilog Timing Simulation with Cadence Verilog-XL Timing Simulation Steps Command Line Quick-Reference List Create Simulation Input Files Command Timing Simulation Command System Task Device-Specific Notes for Timing Simulation GXRESET XTEST_OE 95 95 95 95 95 95 96 96 97 97 97 98 99 99 99 Chapter 10 Verilog Simulation with Frontline PureSpeed 100 Verilog Functional Simulation with Frontline PureSpeed Functional Simulation Steps Test Fixture File Verilog Timing Simulation with Frontline PureSpeed Timing Simulation Steps Test Fixture File Back-Annotation SDF File Header Entries Cell Entries System Task Device-Specific Notes for Timing Simulation GXRESET XTEST_OE 101 101 101 102 102 102 103 103 103 103 104 105 105 105 Appendix A Bus/Vector Reconstruction 106 Bus/Vector Reconstruction Design Flow EDIF Constructs Interpretation EDIF Rename Syntax EDIF Array Syntax EDIF Member Syntax User-Controlled Options for EDIF Array Interpretation Specifying Index Ordering Specifying Least Significant Bit (LSB) Array Definition File Syntax Examples VHDL and Verilog Simulation User Manual 107 108 108 108 109 110 110 112 114 116 Preface The LSC HDL Simulation Library Package from Lattice™ Semiconductor Corporation (LSC, Lattice) contains VHDL and Verilog-compatible libraries for functional and timing simulation It also includes the Module Simulation library to support the 6000 family of devices This manual describes how to use the VHDL and Verilog Simulation Libraries from Lattice to perform functional and timing simulation using one of the following simulators: Cadence LeapFrog™, Mentor QuickVHDL®, Viewlogic Vantage®, Synopsys® VSS™, Cadence Verilog XL, Frontline PureSpeed™, or any OVIcompliant Verilog™ simulator Simulation can be performed on schematic designs that have been created in Cadence Concept™, Mentor’s Design Architect®, and Viewlogic’s Viewdraw® environment and then converted to VHDL or Verilog Simulation can also be performed on VHDL or Verilog designs created using Lattice Semiconductor macros The VHDL libraries are designed for use with: s s s s s s Cadence Leapfrog VHDL simulator Mentor QuickVHDL simulator Viewlogic Vantage VHDL simulator Synopsys VSS (VHDL System Simulator) Model Technology V-System/VHDL simulator Any IEEE 1076-87 compliant VHDL simulator The Verilog libraries are designed for use with: s s s Cadence Verilog-XL Frontline PureSpeed Any OVI-compliant simulator This manual is intended for use by engineers who are knowledgeable in VHDL and Verilog system design and architecture It also assumes that you are familiar with the ispEXPERT™ software and a VHDL or Verilog simulator For additional information on VHDL and Verilog, refer to the appropriate reference material listed under “Related Documentation.” VHDL and Verilog Simulation User Manual What Is In This Manual What Is In This Manual This user manual contains information on the following topics for each supported simulator: s s s s s Environment Setup Prerequisite Files Required Files and Libraries Compiling the Lattice VHDL and Simulation Libraries Design Flows for Functional and Timing Simulation Where to Look for Information Part I, VHDL Simulation Chapter 1, Introduction to VHDL Simulation – Describes the VHDL functional and timing simulation flow It also identifies the directory structure of the files in the VHDL Simulation Libraries Chapter 2, VHDL Simulation with Cadence Leapfrog – Provides information on the environment setup, prerequisite files, compiling the simulation libraries, and simulation steps for the Cadence Leapfrog simulator Chapter 3, VHDL Simulation with Mentor Graphics QuickVHDL – Provides information on the environment setup, prerequisite files, and compiling the simulation libraries Chapter 4, VHDL Simulation with Synopsys VSS – Provides information on the environment setup, prerequisite files, compiling the simulation libraries, and simulation steps for the Synopsys VSS simulator Chapter 5, VHDL Simulation with Viewlogic Vantage – Provides information on the environment setup, prerequisite files, compiling the simulation libraries, and simulation steps for the Viewlogic Vantage simulator Chapter 6, VHDL Simulation with Model Technology V-Tech – Provides information on the environment setup, prerequisite files, compiling the simulation libraries, and simulation steps for the Model Technology V-Tech simulator Chapter 7, VHDL Simulation with Viewlogic Speedwave – Provides information on the environment setup, prerequisite files, compiling the simulation libraries, and simulation steps for the Viewlogic Speedwave simulator VHDL and Verilog Simulation User Manual 10 Bus/Vector Reconstruction Design Flow Bus/Vector Reconstruction Design Flow Bus/vector reconstruction is independent of the design capture system used as long as an array definition file is created See Figure A-1 for the array/bus reconstruction process EDIF file ispEXPERT Compiler EDIF Reader design.ary created by EDIF Reader or by user design.laf ispEXPERT Compiler design.sim ispEXPERT Compiler VHDL Writer ispEXPERT Compiler Verilog Writer VHDL netlist* Verilog netlist* *netlists with reconstructed buses and vectors Figure A-1 Design Flow VHDL and Verilog Simulation User Manual 107 EDIF Constructs Interpretation EDIF Constructs Interpretation Buses/Vectors are represented using array and member constructs in an EDIF file Array is used to define the Bus/Vector and the member construct is used to reference elements of the array EDIF Rename Syntax The rename construct is similar to translating from one language to another Object names that are not valid in EDIF need to be translated into valid EDIF names so that they can be referenced by other EDIF constructs Once the name is out of the EDIF file, the original names should be kept The syntax is defined as: (rename identifier|name stringToken|stringDisplay) where s s s rename is the keyword identifier or name specifies the name used within the EDIF file when referencing the object of interest stringToken or stringDisplay defines the original object name used outside the EDIF file context The followings are examples of rename construct: (rename dog "cat") (rename n10 "$n10") In the first example, the name dog refers to cat Whenever dog is referenced in the EDIF file, the actual object being referenced is cat The object cat is renamed to dog by the program that created the EDIF file When this EDIF file is processed and converted into another format such as LSC’s LAF format, the object name remains cat EDIF Array Syntax EDIF arrays are defined in an EDIF file using the following syntax: (array nameDef integerValue {integerValue}) where s s s array is the keyword nameDef is the name of the array integerValue specifies the size of the array The dimension of the array is defined by the number of integerValues used in the array construct The integerValues must be positive There is no limit to the size or number of dimensions Individual elements of the array can be accessed using the member construct VHDL and Verilog Simulation User Manual 108 EDIF Constructs Interpretation The following are all valid array definitions: (array (array (array (array (array (array (array BUS 8) (rename (rename (rename (rename (rename (rename BUS_A BUS_B BUS_C BUS_D BUS_E BUS_F "BUS[0:7]") 8) "BUS[7:0]") 8) "BUS(7:0)") 8) "BUS(0:7)") 8) "BUS") 8) "BUS") 8) These arrays all define a bus/vector with eight elements The interpretation of each statement can vary depending on the EDIF Reader options selected  NOTE The ispEXPERT Compiler EDIF reader only supports single dimension arrays EDIF Member Syntax The member construct is used to reference elements of an array with the following syntax: (member nameRef integerValue {integerValue}) where s s s member is a keyword nameRef refers to the corresponding array name in the array construct integerValue represents the indices to the array dimensions Since the ispEXPERT Compiler EDIF reader supports arrays with one dimension only, there should be only one index reference for each member construct The indices of an EDIF array always start at zero Therefore, the first element of an array is referenced with index zero The following are all valid references to the arrays defined in the previous section: (member (member (member (member (member (member (member BUS 3) BUS_A 3) BUS_B 3) BUS_C 3) BUS_D 3) BUS_E 3) BUS_F 3) VHDL and Verilog Simulation User Manual 109 User-Controlled Options for EDIF Array Interpretation User-Controlled Options for EDIF Array Interpretation When reading an EDIF file with arrays into the LSC design environment, carefully choose the proper options to process the EDIF file correctly The LSC EDIF reader provides two options to process EDIF arrays properly: Index ordering and Least Significant Bit specification These options can be specified using the Design Manager or through command-line options You can specify the index ordering and the least significant bit using the Design Manager When you are creating or updating a project, click the EDIF Reader Settings button to access the EDIF Reader Settings dialog box In the Bus Reconstruction area, select the radio buttons to reflect the settings needed You can set Array Index Ordering to be Up or Down The Least Significant Bit can be Left (the leftmost bit) or Right (the rightmost bit) Figure A-2 EDIF Reader Settings Dialog Box Specifying Index Ordering When an array name is in the form of "root [#:#], root (#:#), or root" such as "BUS[0:7]", the ispEXPERT Compiler EDIF reader correctly interprets the proper components of the bus and expands the array into single bit elements with the proper naming style If the array name does not follow the above style, the individual element names are created using the root name with the member index number appended For example, (array BUS 3) expands into BUS0, BUS1, and BUS2 Since the range of the indices is not implied in the name itself, the user needs to specify how the names should be created By default, the index number goes from low to high However, if you want to generate the names in descending order, the command line option -array_index_down should be used or Array Indexing Order should be set to Down in the Design Manager EDIF Reader Settings dialog box When this option is used, (array BUS 3) expands into BUS2, BUS1, and BUS0 VHDL and Verilog Simulation User Manual 110 User-Controlled Options for EDIF Array Interpretation s The following array expansion examples use the default index ordering option: (array bus 8) bus0 bus1 bus2 bus3 bus4 bus5 bus6 bus7 (array (rename bus_a "bus[0:7]") 8) bus[0] bus[1] bus[2] bus[3] bus[4] bus[5] bus[6] bus[7] (array (rename bus_b "bus[7:0]") 8) bus[7] bus[6] bus[5] bus[4] bus[3] bus[2] bus[1] bus[0] (array (rename bus_c "bus(7:0)") 8) bus(7) bus(6) bus(5) bus(4) bus(3) bus(2) bus(1) bus(0) (array (rename bus_d "bus(0:7)") 8) bus(0) bus(1) bus(2) bus(3) bus(4) bus(5) bus(6) bus(7) (array (rename bus_e "bus") 8) bus bus bus bus bus bus bus bus (array (rename bus_f "bus") 8) s bus bus bus bus bus bus bus bus The following array expansion examples use the -array_index_down option: (array bus 8) bus7 bus6 bus5 bus4 bus3 bus2 bus1 bus0 (array (rename bus_a "bus[0:7]") 8) bus[0] bus[1] bus[2] bus[3] bus[4] bus[5] bus[6] bus[7] (array (rename bus_b "bus[7:0]") 8) bus[7] bus[6] bus[5] bus[4] bus[3] bus[2] bus[1] bus[0] (array (rename bus_c "bus(7:0)") 8) bus(7) bus(6) bus(5) bus(4) bus(3) bus(2) bus(1) bus(0) (array (rename bus_d "bus(0:7)") 8) bus(0) bus(1) bus(2) bus(3) bus(4) bus(5) bus(6) bus(7) (array (rename bus_e "bus") 8) bus bus bus bus bus bus bus bus (array (rename bus_f "bus") 8) bus bus bus bus bus bus bus bus As these examples show, the -array_index_down option affects only buses/vectors that not have the range implied in the names VHDL and Verilog Simulation User Manual 111 User-Controlled Options for EDIF Array Interpretation  NOTE When specifying the bus/vector range, the range does not have to start or end with zero You may have an array name like "bus[8:15]" Specifying Least Significant Bit (LSB) Arrays are defined before they are referenced The ispEXPERT Compiler EDIF reader generates the individual bits for the arrays according to the rules specified in the above section The elements of an array are referenced by the indices, and it is often ambiguous as to which member is the least or most significant bit The EDIF file does not contain information on whether the array is arranged in descending or ascending orders By default, the ispEXPERT Compiler EDIF reader assumes the least significant bit of the members is the leftmost element of the expanded bits This default is compatible with most of the CAE vendors that generate EDIF files with array constructs If the EDIF file being processed contains arrays with the LSB as the rightmost member, the command line option -array_lsb_right can be used to have the EDIF reader process array members properly Alternately, you can set Least Significant Bit to Right in the Design Manager EDIF Reader Settings dialog box The following examples show the usage of the combined effects of the index ordering and LSB options: s With default index ordering and default LSB: BUS3 is the member referenced by (member BUS 3) in (array BUS 8) BUS[3] is the member referenced by (member BUS_A 3) in (array (rename BUS_A "BUS[0:7]") 8) BUS[4] is the member referenced by (member BUS_B 3) in (array (rename BUS_B "BUS[7:0]") 8) BUS(4) is the member referenced by (member BUS_C 3) in (array (rename BUS_C "BUS(7:0)") 8) BUS(3) is the member referenced by (member BUS_D 3) in (array (rename BUS_D "BUS(0:7)") 8) BUS is the member referenced by (member BUS_E 3) in (array (rename BUS_E "BUS") 8) BUS is the member referenced by (member BUS_F 3) in (array (rename BUS_F "BUS") 8) s With default index ordering and -array_lsb_right: BUS4 is the member referenced by (member BUS 3) in (array BUS 8) BUS[4] is the member referenced by (member BUS_A 3) in (array (rename BUS_A "BUS[0:7]") 8) VHDL and Verilog Simulation User Manual 112 User-Controlled Options for EDIF Array Interpretation BUS[3] is the member referenced by (member BUS_B 3) in (array (rename BUS_B "BUS[7:0]") 8) BUS(3) is the member referenced by (member BUS_C 3) in (array (rename BUS_C "BUS(7:0)") 8) BUS(4) is the member referenced by (member BUS_D 3) in (array (rename BUS_D "BUS(0:7)") 8) BUS is the member referenced by (member BUS_E 3) in (array (rename BUS_E "BUS") 8) BUS is the member referenced by (member BUS_F 3) in (array (rename BUS_F "BUS") 8) s With -array_index_down and default LSB specification: BUS4 is the member referenced by (member BUS 3) in (array BUS 8) BUS[3] is the member referenced by (member BUS_A 3) in (array (rename BUS_A "BUS[0:7]") 8) BUS[4] is the member referenced by (member BUS_B 3) in (array (rename BUS_B "BUS[7:0]") 8) BUS(4) is the member referenced by (member BUS_C 3) in (array (rename BUS_C "BUS(7:0)") 8) BUS(3) is the member referenced by (member BUS_D 3) in (array (rename BUS_D "BUS(0:7)") 8) BUS is the member referenced by (member BUS_E 3) in (array (rename BUS_E "BUS") 8) BUS is the member referenced by (member BUS_F 3) in (array (rename BUS_F "BUS") 8) s With -array_index_down and -array_lsb_right: BUS3 is the member referenced by (member BUS 3) in (array BUS 8) BUS[4] is the member referenced by (member BUS_A 3) in (array (rename BUS_A "BUS[0:7]") 8) BUS[3] is the member referenced by (member BUS_B 3) in (array (rename BUS_B "BUS[7:0]") 8) BUS(3) is the member referenced by (member BUS_C 3) in (array (rename BUS_C "BUS(7:0)") 8) BUS(4) is the member referenced by (member BUS_D 3) in (array (rename BUS_D "BUS(0:7)") 8) BUS is the member referenced by (member BUS_E 3) in (array (rename BUS_E "BUS") 8) BUS is the member referenced by (member BUS_F 3) in (array (rename BUS_F "BUS") 8) VHDL and Verilog Simulation User Manual 113 Array Definition File Syntax Array Definition File Syntax The following is the BNF definition of the array definition file array_file :: = lsb_spec exp_order array_definition+ lsb_spec ::= LSB_SPEC left; ||= LSB_SPEC right; exp_order::=index_order up; ||=index_order down; array_definition ::= array_def member_def+ array_port_def ::= ARRAY_DEF design_name PIN array_name num_bits port_dir; array_net_def ::= ARRAY_DEF design_name NET array_name num_bits; member_def ::= ARRAY_MEMBER design_name array_type array_name bit_number bit_name; design_name ::= identifier array_type ::= PIN ||= NET array_name ::= identifier bit_name ::= port_name || net_name num_bits ::= integer port_dir ::= input ||= output ||= inout bit_number ::= integer port_name ::= identifier net_name ::= identifier Figure A-3 Array File Syntax Format Definition VHDL and Verilog Simulation User Manual 114 Array Definition File Syntax When generating Verilog or VHDL netlists, the VHDL or Verilog writer automatically reads in an array definition file if one is in the project directory The array definition file is typically created automatically by the LSC EDIF reader when the EDIF file contains arrays If the EDIF file does not contain arrays and the bus/vector notation is required for post-route verification, an array file can be manually created prior to compiling the design Follow these guidelines when creating an array definition file: s s s s s s When grouping multiple bits into a bus/vector, the bits must be of the same type Ports must be of the same direction lsc_spec must be specified before arrays can be defined The bit number of an array member must be in the range of to number of bits minus The identifier for an array name or port name must be a valid LSC LAF identifier The exp_order must be specified before an array can be defined The exp_order specification is only effective when the EDIF Reader cannot extract the explicitly bit order information This means this option is not effective in the following cases: name[#:#], name (#:#), and name  NOTE The array definition file must have the same name as the top-level design name, which is not necessarily the EDIF file name VHDL and Verilog Simulation User Manual 115 Examples Examples The following examples show array definition files based on different array handling options used when processing an EDIF file If the entry format is not an EDIF file or if the design entry system used does not support array construct, an array definition file can be created manually to achieve the desired effect Based on different index ordering and LSB options, the array definition file can be different For the following array definition in an EDIF file, the expected array definition files are listed under different processing options (In these examples, “compare” is the name of the design.) (port (array (rename a_4_0_ "a[4:0]") 5) (direction INPUT)) (port (array (rename b_4_0_ "b[4:0]") 5) (direction INPUT)) (port (array (rename equal_4_0_ "equal[4:0]") 5) (direction OUTPUT)) s With default index ordering and default LSB: lsb_spec left; index_order up; array_def compare pin equal[4:0] OUTPUT ; array_member compare pin equal[4:0] equal[0]; array_member compare pin equal[4:0] equal[1]; array_member compare pin equal[4:0] equal[2]; array_member compare pin equal[4:0] equal[3]; array_member compare pin equal[4:0] equal[4]; array_def compare pin b[4:0] INPUT ; array_member compare pin b[4:0] b[0]; array_member compare pin b[4:0] b[1]; array_member compare pin b[4:0] b[2]; array_member compare pin b[4:0] b[3]; array_member compare pin b[4:0] b[4]; array_def compare pin a[4:0] INPUT ; array_member compare pin a[4:0] a[0]; array_member compare pin a[4:0] a[1]; array_member compare pin a[4:0] a[2]; array_member compare pin a[4:0] a[3]; array_member compare pin a[4:0] a[4]; VHDL and Verilog Simulation User Manual 116 Examples s With default index ordering and -array_lsb_right: lsb_spec right; index_order up; array_def compare pin equal[4:0] OUTPUT ; array_member compare pin equal[4:0] equal[4]; array_member compare pin equal[4:0] equal[3]; array_member compare pin equal[4:0] equal[2]; array_member compare pin equal[4:0] equal[1]; array_member compare pin equal[4:0] equal[0]; array_def compare pin b[4:0] INPUT ; array_member compare pin b[4:0] b[4]; array_member compare pin b[4:0] b[3]; array_member compare pin b[4:0] b[2]; array_member compare pin b[4:0] b[1]; array_member compare pin b[4:0] b[0]; array_def compare pin a[4:0] INPUT ; array_member compare pin a[4:0] a[4]; array_member compare pin a[4:0] a[3]; array_member compare pin a[4:0] a[2]; array_member compare pin a[4:0] a[1]; array_member compare pin a[4:0] a[0]; s With -array_index_down and default LSB specification: lsb_spec left; index_order down; array_def compare pin equal[4:0] OUTPUT ; array_member compare pin equal[4:0] equal[0]; array_member compare pin equal[4:0] equal[1]; array_member compare pin equal[4:0] equal[2]; array_member compare pin equal[4:0] equal[3]; array_member compare pin equal[4:0] equal[4]; array_def compare pin b[4:0] INPUT ; array_member compare pin b[4:0] b[0]; array_member compare pin b[4:0] b[1]; array_member compare pin b[4:0] b[2]; array_member compare pin b[4:0] b[3]; array_member compare pin b[4:0] b[4]; array_def compare pin a[4:0] INPUT ; VHDL and Verilog Simulation User Manual 117 Examples array_member compare pin a[4:0] a[0]; array_member compare pin a[4:0] a[1]; array_member compare pin a[4:0] a[2]; array_member compare pin a[4:0] a[3]; array_member compare pin a[4:0] a[4]; s With -array_index_down and -array_lsb_right: lsb_spec right; index_order down; array_def compare pin equal[4:0] OUTPUT ; array_member compare pin equal[4:0] equal[4]; array_member compare pin equal[4:0] equal[3]; array_member compare pin equal[4:0] equal[2]; array_member compare pin equal[4:0] equal[1]; array_member compare pin equal[4:0] equal[0]; array_def compare pin b[4:0] INPUT ; array_member compare pin b[4:0] b[4]; array_member compare pin b[4:0] b[3]; array_member compare pin b[4:0] b[2]; array_member compare pin b[4:0] b[1]; array_member compare pin b[4:0] b[0]; array_def compare pin a[4:0] INPUT ; array_member compare pin a[4:0] a[4]; array_member compare pin a[4:0] a[3]; array_member compare pin a[4:0] a[2]; array_member compare pin a[4:0] a[1]; array_member compare pin a[4:0] a[0]; VHDL and Verilog Simulation User Manual 118 Index A Array construct 108 Array Definition File 106 Array file naming 115 syntax 114 Array Indexing Order 110 Array name 110 B Back-annotation 27, 103 Bus reconstruction 106 C Cadence Simulation Files compiler.cmd 31 global.cmd 30 master.local 30 vhdllink.cmd 31 vlibs 32 Commands Cadence compiling your design 36 converting a schematic 36 elaborating your design 38 generating a VHDL netlist 38 invoking LeapFrog 36, 95 quick reference 36, 38, 95 Mentor compiling your design 47, 49 converting your schematic 47 creating a work library 47 invoking QuickVHDL 47, 49 quick reference 47, 49 Model Technology compiling the libraries 72, 73, 75, 77, 78 creating a work library 84 quick reference 79 Synopsys compiling your design 59 creating a design 57 creating the work library 57 invoking VSS 59, 79 quick reference 59 simulating the design 57 Verilog creating a test fixture file 95, 101, 102 creating a Verilog netlist 95 creating simulation input files 97 invoking the simulator 97 quick reference 97 Viewlogic compiling your design 67, 69 converting your design 67 creating a work library 67, 69 invoking ViewSim 67, 69 quick reference 67, 69 Constructs 109 Array 108 Rename 108 D Directory examples 18, 20, 90 library 18, 21 verilog 90 Directory Structure Verilog 90 VHDL 17 E EDIF Array Definition File 106 constructs 108 Environment Variables Cadence 30 Mentor 42, 53 Viewlogic 63 Examples Directory 18, 20, 90 F Files cshrc 63 synopsys_vss.setup 53 compiler.cmd 31 csd.lib 37 design.sdf 93 design.vhd 35 design.vlo 93 expt1076.ini 63 VHDL and Verilog Simulation User Manual 119 Index global.cmd 30 hdl.var 32, 37 master.local 30 mgc_location_map 42 quickvhdl.ini 43 vhdllink.cmd 31 vhdlwrite.options 43 viewdraw.ini 63 vlibs 32 vsslib.ini 63 Functional Library Cadence 33, 44 Mentor 54 Model Technology 72 Overview 22 Viewlogic 65 Functional Simulation Examples Frontline 101 Model Technology 75 Viewlogic Speedwave 84 Functional Simulation Overview 22, 91, 94, 100 Functional Simulation Process Flow 26 Functional Simulation Steps Cadence 35 Mentor 46 Verilog 95, 101 Viewlogic 66 Module Library Cadence 34 Mentor 56 Mentor Graphics 45 Overview 23 P Platforms supported 16, 89 Q Quick Reference Cadence 36, 38, 95 Cadence_XL 97 Mentor 47, 49 Model Technology 79 Synopsys 59, 79 Verilog 97 Viewlogic 67, 69 R Rename construct 108 S Index ordering 110 Simulation, timing back-annotation 103 non-VITAL 77, 85 Standards conformance to 16 Synopsys Simulation Files synopsys_vss.setup 53 L T I Least Significant Bit 112 Library Compilation Cadence 33, 44 Mentor 54 Viewlogic 65 Library Directory 18, 21 M Member 109 Member construct 109 Mentor Environment Variables mgc_location_map 42 Mentor Simulation Files quickvhdl.ini 43 vhdlwrite.options 43 Module simulation library 91, 93, 95 Test fixture 95 Test fixture file 95, 101, 102 Timing Library Cadence 33 Mentor 44, 55 Overview 23 Synopsys 55, 56 Timing Simulation back-annotation 103 Timing Simulation Overview 23, 27, 91, 93, 94, 100 Timing Simulation Process Flow 28 Timing Simulation Signals XTEST_OE 40, 51, 61, 70, 79, 87, 99, 105 VHDL and Verilog Simulation User Manual 120 Index Timing Simulation Steps Cadence 37 Frontline Purespeed 102 Mentor Graphics (VITAL/non-VITAL) 48 Model Technology 78, 85 Synopsys 58 Verilog 96 Viewlogic 68 V Vector reconstruction 106 Verilog Directory 90 Verilog Timing Simulation Files design.sdf 97 design.vlo 97 Viewlogic Simulation Files cshrc 63 expt1076.ini 63 viewdraw.ini 63 vsslib.ini 64 VITAL Timing Simulation 37, 48, 58 X XTEST_OE 40, 51, 61, 70, 79, 87, 99, 105 VHDL and Verilog Simulation User Manual 121 ... Reference Manual LeapFrog VHDL User Guide LeapFrog VHDL Simulator Reference Manual VHDLLink User Guide Mentor s s s QuickSim II User? ??s and Reference Manual QuickVHDL User? ??s and Reference Manual VHDLwrite... VHDLwrite User? ??s and Reference Manual Viewlogic s Viewsim /VHDL User Guide Synopsys s VHDL System Simulator Tutorial VHDL System Simulator Command Reference Manual VHDL System Simulator User? ??s Manual. .. (Version 2.1) Verilog HDL Reference (version 1.0) Model Technology Inc s V-System /VHDL Windows User? ??s Manual Frontline PureSpeed s PureSpeed User? ??s Manual VHDL and Verilog Simulation User Manual 14