Mechanisms of the performance enhancement by hetero gate dielectric in tunnel field effect transistors

KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018 3 MECHANISMS OF THE PERFORMANCE ENHANCEMENT BY HETERO GATE DIELECTRIC IN TUNNEL FIELD EFFECT TRANSISTORS Nguyen Dang Chiena, Ngo Th[.]

KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018 MECHANISMS OF THE PERFORMANCE ENHANCEMENT BY HETERO-GATE DIELECTRIC IN TUNNEL FIELD-EFFECT TRANSISTORS Nguyen Dang Chiena, Ngo Thi Muaa, Tran Huu Duya, Chun-Hsing Shihb a b Faculty of Physics, Dalat University, Lam Dong, Vietnam Department of Electrical Engineering, National Chi Nan University, Nantou 54561, Taiwan * Corresponding author: Email: chiennd@dlu.edu.vn Abstract The hetero-gate dielectric (HGD) structure has recently been demonstrated experimentally in tunnel field-effect transistors (TFETs) to enhance their electrical performance In this paper, we adequately examine the mechanisms that the HGD works to ameliorate the electrical characteristics of TFETs A typical bulk p-i-n TFET structure is used to exclude the uncertain effects of body factors on the role of HGD It is showed that the subthreshold swing is improved by the presence of a conduction band well near the source/channel junction, but the swing improvement is limited by the appearance of the hump effect when the local potential well approaches the source By analyzing the roles of dielectric heterojunctions at source- and channel-sides separately, it is found that the on-current enhanced by the source-side heterojunction is about times larger than by the channel-side one The reason is that the source-side heterojunction directly modulates the on-state tunnel width, whereas the channel-side heterojunction indirectly affects the on-current through modulating the subthreshold-state tunnel width Exactly understanding the mechanisms of the performance enhancement by HGD is important in studying the optimal design of HGDTFETs Keywords: Hetero-gate dielectric; high-k gate insulator; band-to-band tunneling; tunnel field-effect transistor (TFET) KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018 CƠ CHẾ NÂNG CAO ĐẶC TÍNH HOẠT ĐỘNG NHỜ ĐIỆN MÔI CỰC CỔNG DỊ CHẤT TRONG TRANSISTOR TRƯỜNG XUYÊN HẦM Nguyễn Đăng Chiếna*, Ngô Thị Mùaa, Trần Hữu Duya, Chun-Hsing Shihb a b Khoa Vật lý, Trường Đại học Đà Lạt, Lâm Đồng, Việt Nam Khoa Kỹ Thuật Điện, Đại học Quốc lập Ký Nam, Nam Đầu, Đài Loan * Tác giả liên hệ: Email: chiennd@dlu.edu.vn Tóm tắt Cấu trúc điện mơi cực cổng dị chất (HGD) gần chứng minh thực nghiệm transistor trường xuyên hầm (TFET) để nâng cao đặc tính điện chúng Trong báo này, nghiên cứu chi tiết chế giúp cho điện mơi cực cổng dị chất cải thiện đặc tính điện TFET Cấu trúc p-i-n TFET khối đặc trưng sử dụng để loại trừ ảnh hưởng không xác định yếu tố thân linh kiện đến vai trò HGD Nghiên cứu độ dốc ngưỡng cải thiện nhờ có mặt hố định xứ gần chuyển tiếp nguồn/kênh, cải thiện bị giới hạn xuất hiệu ứng bướu hố tiến gần tới cực nguồn Bằng việc phân tích vai trị chuyển tiếp dị chất phía nguồn kênh cách riêng rẽ, nghiên cứu dòng mở tăng lên nhờ chuyển tiếp dị chất phía nguồn lớn khoảng lần nhờ chuyển tiếp dị chất phía kênh Nguyên nhân chuyển tiếp dị chất phía nguồn hiệu chỉnh trực tiếp độ rộng xuyên hầm trạng thái mở, chuyển tiếp dị chất phía kênh ảnh hưởng gián tiếp tới dịng mở thơng qua hiệu chỉnh độ rộng xuyên hầm trạng thái ngưỡng Việc hiểu xác chế làm nâng cao đặc tính hoạt động TFET nhờ cấu trúc HGD quan trọng trình thiết kế tối ưu cho TFET có điện mơi cực cổng dị chất Từ khóa: Điện mơi cực cổng dị chất; chất cách điện có độ điện thẩm cao; xuyên hầm qua vùng cấm; transistor trường xuyên hầm (TFET) KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018 INTRODUCTION Traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) have exhibited the unsuitability for use in ultra-low power applications since they are subjected to the physical limit of 60 mV/decade subthreshold swing at room temperature (International Technology Roadmap for Semiconductors, 2015) To overcome this fundamental limit of MOSFETs, one has proposed tunnel field-effect transistors (TFETs) whose steep on-off switching with sub-60 mV/decade subthreshold swing has been experimentally demonstrated (Appenzeller et al., 2004; Choi et al., 2007) Other significant advantages of TFETs over MOSFETs are small power dissipation (Koswatta et al., 2009) and high dimensional scalability (Bardon et al., 2010) However, the bandto-band tunneling, which makes the breakthrough of the kT/q limit, is also responsible for low on-current in TFETs because the tunneling probability is relatively small (Seabaugh & Zhang, 2010) Therefore, enhancing on-current has become the most challenge of TFET devices and attracted much attention since the last 2000s In order to enhance the conduction current of TFETs, many methods relating to both material and structure techniques have been proposed to reduce the tunnel barrier and/or to increase the tunneling area at on-state (Nayfeh et al., 2009; Kao et al., 2012; Chien et al., 2013) Since the tunneling probability is exponentially increased with decreasing the height of tunnel barrier, using low-bandgap materials has been realized as one of most effective techniques to boost the on-current (Nayfeh et al., 2009) In the other hand, because of the same dependences of the tunneling probability on the width and the height of tunnel barrier, narrowing the tunnel barrier has always be concerned largely While the tunnel barrier height is basically determined by the material bandgap, there are so many factors that affect the tunnel barrier width such as source/drain doping profile (Chien & Shih, 2017), gate insulator and spacer (Choi et al., 2016), gate materials (Noor et al., 2017), body thickness (Toh et al., 2007), structure of source/channel junction (Mohata et al., 2011), overall device structure that determines the way of tunneling motions (Vendenberghe et al., 2008), dimensions of device parameters (Chien & Shih, 2016), supply voltage (Chien et al., 2016), etc Despite the complexity, the basic principle of controlling the tunnel width by gate voltage is applied in all cases Since the gate is insulated from the channel by a gate insulator, properly designing gate-oxide layer is an important method to increase the gate control and thus the on-current The simplest way to that is scaling down equivalent-oxide thickness (EOT) by using high-k dielectric and/or decreasing physical oxide thickness (Boucart & Ionescu, 2007; Chien & Shih, 2017) To further improve the electrical performance of TFETs, both structure and material techniques have been combined to propose an advanced structure of hetero-gate dielectric (HGD) which consists of different gate dielectric materials at the source, channel and drain (Choi et al., 2010; Choi et al., 2016) However, the mechanisms of the performance enhancement in HGD-TFETs have not been adequately elucidated, particularly the roles of the local potential well and the source-side heterojunction have not been clearly understood yet KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018 In this paper, the mechanisms that make the subthreshold swing decreased and the on-current increased are properly elucidated to provide an adequate understanding on the device physics and design of HGD-TFETs In order to so, two-dimensional device simulations based on the simulator Medici (Synopsys MEDICI User’s Manual, 2010) are performed to produce the electrical characteristics of TFETs The paper is organized into main sections, including the first introduction and the last conclusion After describing the structure and simulation models in section 2, the ambipolar behavior, subthreshold swing and on-current improvements are presented in sections 4, and 6, respectively DEVICE STRUCTURE AND SIMULATION SETUP Figure sketches the schematic structure of hetero-gate dielectric TFETs that are investigated in this study Generally, there are two low-k/high-k heterojuctions presented in the gate insulator layer which has a fixed physical thickness of nm The locations of source- and channel-side heterojunctions were specified by parameters X sh and Xch, respectively SiO2 with a dielectric constant of 3.9 was typified for the low-k insulator whereas the permittivity of high-k dielectric was varied and stated clearly in each investigation A typical bulk TFET structure based on the point-tunneling was employed to avoid the impacts of body parameters on the device performance that can make changes in the major role of HGD In all TFETs, low-bandgap Ge was used to get high on-currents for practical significance of the study Both the source and drain regions were respectively doped with equally high acceptor and donor concentrations of 1020 cm-3 To exactly investigate the effects of the heterojunction positions, the ideal abruptness of doping profiles was assumed at the source and the drain A small donor concentration of 10 17 cm3 was specified in the channel which was assigned a long length of 100 nm to exclude possible short-channel effects which may cause difficulties in studying the effects of HGD layer on device characteristics Aluminium with a workfunction of 4.27 eV was applied at the gate terminal Hetero-Gate Dielectric TFET Drain Gate Source High-k Low-k Low-k p+ n+  n 1020 cm-3 17 -3 10 cm Xsh 20 10 cm-3 x Xch Channel-Side Heterojunction Source-Side Heterojunction Bulk Figure Schematic structure of hetero-gate dielectric TFETs used in the study KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018 Examining the operation, mechanism and design of HGD is based on the electrical characteristics of TFETs such as current-voltage curves, energy-band diagrams, tunneling rate contour which are obtained by carrying out the simulations of two-dimensional devices The total tunneling current in Ge-based TFETs is contributed by both direct and indirect tunneling processes However, if noting that, at comparable bandgaps, the direct tunneling probability is much greater than the indirect one, the direct tunneling dominates the on-current of Ge TFETs because the difference between direct and indirect bandgaps is rather small (0.14 eV) (Kao et al., 2012) In simulations, the direct tunneling rate (Gdir) is generated by the nonlocal approach of the Kane model to calculate the TFET current as (Kane, 1961): Gdir  A 2 E 1g / exp( B E g3 /  (1) ) -3 10 0.4 (b) Uniform-Gate Dielectric TFETs -5 Electron Energy (eV) Drain Current (A/mm) 10 -7 10 -9 10 -11 10 Decrease EOT: 3, 2, 1, 0.5, 0.3 nm -13 10 Vds = 0.7 V -15 10 -0.4 -0.2 0.0 0.2 0.4 0.6 0.0 -0.4 -0.8 -1.2 (a) 0.8 -1.6 -60 1.0 : EOT = nm : EOT = 0.5 nm Channel Tunnel Width Vgs = 0.1 V Vds = 0.7 V Drain Uniform-Gate Dielectric TFETs -40 -20 20 40 Distance to Drain (nm) Gate-to-Source Voltage (V) Figure (a) Current-voltage characteristics of uniform-gate dielectric TFETs with various EOTs; (b) Energy-band diagrams at off-state of uniform-gate dielectric TFETs with different EOTs where Eg is the bandgap of semiconductor; ξ is the nonlocal electric field; A and B are material parameters which have been calculated to get 1.6×10 20 eV1/2/cm.s.V2 and 9.5×106 V/cm.eV3/2, respectively The band gap narrowing due to heavy-doping, the Fermi-Dirac distribution and Shockley-Read-Hall recombination were also included in simulations AMBIPOLAR CURRENT SUPPRESSION In a typical p-i-n TFET structure, both the source/channel and drain/channel junctions can play a role of tunnel junction because their tunneling window can be open up by appropriate gate voltages Expectedly, the tunneling window at source/channel junction is largely open up at on-state and completely closed down at off-state to engender favourable on-off transition Because of the symmetry between the n- and p-type operation modes, the ambipolar current always presents in any p-i-n TFETs Many factors can affect the ambipolar current, for example, gate-oxide thickness, material bandgap, gate-drain alignment, drain concentration, length and voltage KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018 To observe the effect of EOT on the ambipolar behavior, figure 2(a) shows the current-voltage curves of TFETs whose gate dielectric layer is uniform for various EOT values It is seen that although the on-current is largely enhanced, the ambipolar offcurrent is also increased severely with decreasing the EOT The serious increase of ambipolar current limits the exploitation of scaling EOT for ameliorating the on-current of TFETs To explain the variation trend of ambipolar current, figure 2(b) plots the offstate energy-band diagrams at the drain-channel junction of TFETs with different EOTs The thinner EOT results in the stronger gate control to bend the energy-band diagram at the drain/channel junction more largely As a result, the tunnel width is narrowed and thus the tunneling current is increased with scaling EOT Although some methods have been suggested to effectively suppress the ambipolar current, they also lead to considerable disadvantages For example, the drain engineering, which includes decreasing the concentration, increasing the length or gate-drain underlap, causes the on-current degradation because of the increase in resistance -3 0.9 10 Hetero-Gate Dielectric TFETs 0.6 -5 -7 10 -9 10 Xsh = Source Length Xch = 50 nm Electron Energy (eV) Drain Current (A/mm) 10 EOT of Low-k Dielectric: nm Decrease EOT of High-k Layer: 3, 2, 1, 0.5, 0.3 nm -11 10 -13 10 0.3 0.0 -0.3 -0.6 -0.9 -15 10 -0.4 Vds = 0.7 V (a) -0.2 0.0 0.2 0.4 0.6 0.8 -1.2 1.0 Hetero-Gate Dielectric TFETs Source Xsh = Source Length Xch = 50 nm Tunnel Width Vds = 0.7 V Vgs = 0.8 V High-k Dielectric: : EOT = 0.5 nm : EOT = nm (b) -20 Channel 20 40 Distance to Drain (nm) Gate-to-Source Voltage (V) Figure (a) Current-voltage curves of HGD-TFETs with single dielectric heterojunction structure for various EOTs of high-k layers; (b) Energy-band diagrams at on-state of HGD-TFETs with different EOTs of high-k layers It is reminded that the on-state tunneling occurs at the source/channel junction whereas the off-state tunneling generates at the drain/channel junction of TFETs Because the purpose of introducing high-k dielectric into TFETs is to shorten the on-state tunnel path at source/channel junction, replacing the gate insulator layer at drain side by a lowk dielectric does not change the action of high-k dielectric at source side on the on-current This is an important idea from which the HGD has been introduced into TFET devices To inspect above reasoning, Figure 3(a) shows the input characteristics of HGD-TFETs with a single dielectric heterojunction (i.e., corresponding to Xsh = source length, Xch = half of channel length) for various EOTs of high-k layer Because the EOT of low-k layer is fixed, the ambipolar current is remained unchanged at a low level regardless of decreasing the EOT of high-k layer In the other hand, the increase of the on-current by scaling EOT in the single dielectric heterojunction TFETs is completely similar to that in the uniform-gate dielectric TFETs As shown in figure 3(b), the on-state energy-band diagram at the source/channel junction of the HGD-TFET with the thinner EOT is curved KỶ YẾU HỘI NGHỊ KHOA HỌC THƯỜNG NIÊN TRƯỜNG ĐẠI HỌC ĐÀ LẠT NĂM 2018 more strongly than that with the thicker EOT to form the shorter tunnel path and thus attain the higher on-current SUBTHRESHOLD SWING IMPROVEMENT The advantage of HGD is not only in the ambipolar current but also in the subthreshold swing if the HGD structure is properly designed (Choi et al., 2010) It has been demonstrated that the improvement of subthreshold swing in HGD-TFETs is originated from the formation of a local minimum of conduction band near the source/channel junction which makes a more abrupt decrease of tunnel width Choi et al (2010) explained that the decrease in the profitability of HGD at small Xch (< nm) is due to the shallowing of the conduction band well However, this section will show that it is not a main reason -3 10 1.0 Hetero-Gate Dielectric TFETs Hetero-Gate Dielectric TFETs 0.8 -5 -7 Electron Energy (eV) Drain Current (A/mm) 10 Xsh = Source Length 10 -9 10 Vds = 0.7 V -11 10 Position of ChannelSide Heterojunction: Xch = 20, 12, 8, 6, 4, nm -13 10 -15 10 -0.4 0.0 0.2 0.4 0.6 0.8 0.2 Tunneling 0.0 -0.2 -0.4 Vgs = 0.3 V Vds = 0.7 V Channel -0.6 -1.0 -30 1.0 Position of Right Heterojunction: : Xch = nm : Xch = nm Source 0.4 -0.8 (a) -0.2 0.6 Xsh = Source Length (b) -20 -10 10 20 30 40 50 Distance to Source (nm) Gate-to-Source Voltage (V) Figure (a) Input transfer characteristics of HGD-TFETs with various X ch; (b) Energy-band diagrams at subthreshold state of HGD-TFETs with different X ch Figure 4(a) shows the current-voltage characteristics of HGD-TFETs with various positions of the channel-side heterojunctions (Xch) To exactly investigate the effects of Xch on the device characteristics, the structure of single dielectric heterojunction (Xsh = source length) is used to exclude any influences of the second dielectric heterojunction When the position of the channel-side heterojunction is far from the source (X ch ≥ nm), the subthreshold swing decreases along with decreasing the X ch However, when the Xch decreases smaller than nm, the overall subthreshold swing starts increasing Notably, the subthreshold region is clearly divided into high and low swing regions which are separated by a hump voltage (Vhump) This hump effect makes the average subthreshold swing increased To understand the appearance of the hump effect in short-Xch HGDTFETs, figure 4(b) displays the energy-band diagrams at subthreshold state of HGDTFETs with Xch = and nm As seen in the figure, the conduction band well is higher in the Xch=4nm than in the Xch=8nm TFET This makes the abrupt change of tunnel width triggered more lately in the short-Xch than in the long-Xch device Before the abrupt decrease of tunnel width occurs (Vgs ≤ Vhump), the tunnel width is small and thus the tunneling current is high (higher than 0.1 pA/µm) in the Xch=4nm TFET, whereas those ... cases Since the gate is insulated from the channel by a gate insulator, properly designing gate- oxide layer is an important method to increase the gate control and thus the on-current The simplest... junction of TFETs Because the purpose of introducing high-k dielectric into TFETs is to shorten the on-state tunnel path at source/channel junction, replacing the gate insulator layer at drain side by. .. the increase of the on-current by scaling EOT in the single dielectric heterojunction TFETs is completely similar to that in the uniform -gate dielectric TFETs As shown in figure 3(b), the on-state