A highly digital vco based adc for iot applications on skywater 130nm

2021 8th NAFOSTED Conference on Information and Computer Science (NICS) A Highly Digital VCO-based ADC for IoT Applications on Skywater 130nm Duc-Manh Tran, Ngo-Doanh Nguyen, Duy-Hieu Bui and Xuan-Tu Tran The Information Technology Institute Vietnam Nation University 144 Xuan Thuy street, Cau Giay, Hanoi, Vietnam 16020772, doanhnn, hieubd, tutx{@vnu.edu.vn} Today, the IoT device requires various data nearby like humidity, temperature, speech, and so forth for complicated applications Therefore, analog-to-digital circuits play an essential role in each IoT node, which converts the signals of sensors to data for other process steps There are many sensors and MEMS devices like thermistor bridges, MEMS microphones, and so on Most of them require high precision for a few hundred microvolts from several hertz to fifteen kilohertz Moreover, to reach the IoT requirements, the ADC must be a low-cost and low-power circuit As a result, lowcost, low-power, high-resolution ADCs are essential for SoCs that serve advanced IoT applications In recent years, the Voltage Control Oscillator (VCO)based ADC has been developed to solve the problem of the CMOS scaling However, the advantages of performances, like consuming low-power and occupying a small area [1], [2], are more attractive These advantages of the VCO-based ADC are suitable for IoT applications Moreover, the timeencoding technique applied in this ADC allows the digital circuits to execute a lot of analog functions Thus, the VCObased ADCs are more scalable than pure analog circuits and can be deployed at the new technology nodes in the less time For the reasons below, the VCO-based ADC is appropriate to integrate into low-power SoCs designed for IoT devices The non-linearity of the Voltage Control Oscillator (VCO) limits the Signal-to-Noise and Distortion Ratio (SNDR) of the ADC In the prior work, VCO-based ADCs were typically 978-1-6654-1001-4/21/$31.00 ©2021 IEEE 549 II BACKGROUND Vin(t) VCO φ(t) RST n bit φn(t) Register I I NTRODUCTION deploys the pseudo-differential architecture to reduce the ADC distortion However, this architecture performs in two branches of ADC; thus, it spends twice the power and die size compared to the single-ended mode By customizing circuits, the works in [3], [4] increase the linearity of the VCO to decrease total harmonic distortion of the VCO-based ADC Our work applied this method instead of pseudo-differential to reduce hardware complexity and power consumption; while the SNDR of ADC is improved in the single-ended mode for the bandwidth below 50 KHz This paper introduces a continuous delta-sigma VCO-based ADC and the techniques to increase the resolution: customizing VCO and applying the special decimation filter This ADC is designed to adapt to the desires of IoT similarly audio recording, sensor measuring, and any application for the bandwidth below 50 kilohertz The rest of this paper is organized as follows Section II introduces the concept of the VCObased ADC and applying the delta-sigma modulation for this ADC Section III briefs the research related to sensor readout circuits, VCO-base ADC and concludes with a few opinions about VCO-based ADC for IoT After that, in section IV, we propose a VCO-based ADC structure and Ring Oscillator customization Section V presents the post-layout simulation results, also comparisons between our work and priory art Finally, section VI concludes our work and defines the future work Counter Abstract—This paper proposes a highly digital Analog-toDigital Converter (ADC) for various internet of things applications, which operates at the bandwidth below 50 kHz Our goal is a highly digital ADC that can be integrated into the lowpower System-on-Chip (SoC) to adapt to IoT demands like audio recording or sensor measuring The ADC is implemented using only ring-oscillator and digital circuits that is based on timeencoding technique and Delta-Sigma modulation In this work, we optimize the Voltage Control Oscillator (VCO) for high linearity and apply a Cascaded Integrator Comb (CIC) filter with the aim of increasing the ADC’s resolution Our work is implemented and verified by fully open-source tools on the Skywater 130 − nm technology The ADC produces more significant than 12 effective bits at the cost of 0.97 mW and occupies 0.08 mm2 Index Terms—VCO-based ADC, Sensor Readout, Open-source IC design CLK Sampling Clock Fig 1: Basic structure of the VCO-based ADC n bit φq(n) R1 2021 8th NAFOSTED Conference on Information and Computer Science (NICS) VCO 11 R2 Analog Time-encoding is an exciting technique,phases which converts the signal Magnitude (dB) voltage domain in analog processing to the time domain in digital processing One is the VCO-base ADC, which shows the fundamental conversion mechanism in Fig Thanks to the Voltage Control Oscillator (VCO), especially the ring oscillators, the voltage of Vin (t) is modulated to the oscillation frequencies of a square wave ϕ(t) After that, the number of ϕ(t) pulses is accumulated by the counter to ϕn (t) values Finally, for each sampling clock, these values are dumped into the register to ϕq (n) and the counter is reset -20 -40 -60 10-3 10-2 10-1 Normalized Frequency ( DFF x(t) DFF VCO Phase Readout Sampling clock rad/sample) (a) Noise transfer function response 1bit VCO 100 φ(t) φ [n] φ q[n] 1-Z-1 y[n] Fs Fig 2: Phase readout circuit (b) Block diagram In order to reach high resolutions, the number of pulses per sampled time should cover all values of bit levels exactly As a consequence, the principal method requires the VCO to operate at a wide-range frequency However, that raises the phase noise and the non-linearity of the oscillator, also 21 creates error bits in the the flip-flop’s processes The deltasigma(∆ Σ) modulator is applied to shape quantization noise rather than increasing the VCO frequency range Instead of using a counter to accumulate the numbers of pulse, the ∆ Σ modulation uses the phase readout to catch the edges of pulse (falling, raising edge) In Fig 2, the phase readout includes two D flip-flops and an XOR gate that captures raising or falling pulses, then dumps them into high logic bits at the output This structure is first-order noise shaping, which is evidenced by the below equations and the frequency response in Fig Z (ω0 , kV CO x(t)) dt Z nTs (ω0 , kV CO x(t)) dt + q[n] ϕq [n] = ωq nTs + kV CO ϕ= Fig 3: Delta sigma modulation principle bandwidth of readout circuits is below one kilohertz in [5], [6] It is also between a kilohertz and ten kilohertz such as [7], [8], and also up to hundred kilohertz in [9] Additionally, in speech recording applications, the bandwidth of ADC is either 20 KHz or 24 KHz [10] The VCO-based ADC has been becoming popular, along with plenty of applications Five main classes are mentioned in [11] In this context, these ADCs are allocated to two main applications: 1) The first are high-speed ADCs, the bandwidth above ten megahertz, and that is usually put into wireless operations [11], [12] 2) The second are low-speed ADCs, the bandwidth between a few hertz and hundred kilohertz, that are applied in sensor readout and speech recording [10], [13] V ∞ y[n] = ϕq [n] − ϕq [n − 1] = q[n] − q[n − 1] + ω0 Ts + Z (ω0 , kV CO x(t)) dt V N T F = q[n] − q[n − 1] = q[n](1 − Z −1 ) Where: x(t) is input signal kvco is sensitive coefficient ω0 is offset frequency ϕ[∗] is phase of signal III R ELATED W ORK In IoT devices, the output signals of sensors are lowspeed; thus, sensor readout circuits have low bandwidth The The ∆ Σ modulation is applied to increase the signal to noise (SNR) ratio in the whole low-speed VCO-basedADCs The close-loop δ σ structure gain SNR of the ADCs; it also gains the implementation’s complexity Moreover, the non-linear voltage control oscillator is a critical problem that limits the effective resolution of ADCs by distortion In the hardware implementation, the whole priory work approached the architecture method to reduce distortion In [10], [13], [14] design the ADCs based on closed-loop differential structure As mentioned before, this structure spends twice the power and die size compared to the single-ended mode and gains the complexity in the hardware implementation In this work, we focus on increasing the effective resolution without the complex architecture for low-bandwidth ADC The next section presents a detailed proposal of our VCO-based ADC 550 2021 8th NAFOSTED Conference on Information and Computer Science (NICS) IV P ROPOSAL A Proposed structure The structure of the proposed VCO-based ADC is presented in In this structure, the ring oscillator, which includes 11 delay cells, is used to convert input signal x(t) to 11 pulse signals from ϕ0 (t) to ϕ10 (t) with different delay time The phase readouts, which is mentioned in section II are combined into a multi-phase readout to read 11 pulses from the oscillator After that, all digital output from multi-phase readout from y0 (n) to y10 (n) are summed by an adder tree that becomes a 4bit signal Y (n) Finally, A Cascade Integrated Combine (CIC) filter is applied to reduce the sampling rate and increase the signal-to-noise ratio (SNR) of the ADC The final output D(n) is 32-bit data written out to the memory for testing The whole system operates at 25 M Hz, while the data D(n) frequency is 24.4 KHz and 48.8 KHz at the oversampling rate 512 and 256, respectively x(t) Ring oscillator 11 delay cells φ10(t) φ1(t) φ0(t) Clk 25 MHz 11 phase readout circuits y9(n) y10(n) y0(n) Adder tree Y(n) for encoding, one needs to care about the number of delay stages and delay time of each inverter Unfortunately, at the normal supply voltage (1.8 V ), the simple inverter (Inv) has an exceedingly small delay time, unfitting for low-speed circuits As an alternative, the cross-coupling Inv is suitable for this case It could obtain a longer delay time and low-power consumption at low speed As shown in Fig 5, the crosscoupling delay cell is constructed based on differential inv, which includes two main Invs (Inv1) and two auxiliary Invs (Inv2) In our design, the PMOS and NMOS transistors of Inv1 are W/L = 10 µm/1.9 µm, whereas the PMOS and NMOS transistors of Inv2 are W/L = µm/1.9 µm The RO includes 11 delay elements, that operate from 2.5 M Hz to 10 M hz with tail supplies voltage of 0.5 V and 0.1 V respectively The ring oscillators (RO) are non-linear devices that inject distortion into output signals and reduce effective bits There are two ways to resolve this issue In the first way, the research approach architectural level solutions, e.g by calibration, feedback or signal swing reduction [12], [15], [16] The second approach is less common; it performs a circuit level optimization of the VCO core [3] Although the second way is less common, it has obtained significant results [3] According to the method mentioned in a second way, our work uses two resistors R1 = R2 = 100Ω to feed the input signal into RO Fig 6a illustrates the ring oscillator; an input signal feeds that through two resistors The simulations and measurements were done using NGSPICE based on Skywater’s PDK The measured voltage to frequency conversion curve of the VCO for 0.2V to 1.1V input voltage sweep is shown in Fig 6b Clearly, the curve is visually linear The deviation of this curve from a best-fit line (i.e., the non-linearity error) is also shown in Fig 6b By the results are shown above, the linearity range of VCO from 2.5 M Hz to 10 M Hz The worst-case nonlinearity is 30 KHz , corresponding to 0.3% of the full scale inn 4bit@25MHz outn Inv1 Inv2 CIC filter Inv2 32bit@(