Đang tải... (xem toàn văn)
VLSI CLC design thiết kế vi mạch
9/25/13 1 VLSI Combinational Circuit Design !"#$%&$!'()$ Hanoi University of Science and Technology Dr. Le Dung Hanoi University of Science and Technology *$+,")&$ )./,+$+0).1$1."1'./$ 1,($2&$.34+&3&(/&-$25$$$$ SSI, MSI and LSI “off-the-shelf” parts VLSI Application-specific integrated circuit (ASIC) 6.()+&$78$ 9'+:4+&$78;$ 9/25/13 2 Dr. Le Dung Hanoi University of Science and Technology An example of the “off-the-shelf” parts design Dr. Le Dung Hanoi University of Science and Technology Designing with “off-the-shelf” parts • $<=&$>0?@/=&@;=&+AB$4,"/;$C$8033&"1.,+$667D$967$,(-$%67$ 30-'+,"$+0).1$.(/&)",/&-$1."1'./;$EFGHHHD$GHHH$I$J$ • $K'.1L+5$,;;&32+.()$,$1."1'./$20,"-$$ • $<=&$('32&"$0A$4,"/;$,(-$/=&$10;/$4&"$),/&$1,($2&103&$ '(,11&4/,2+5$+,")&$ 9/25/13 3 Dr. Le Dung Hanoi University of Science and Technology VLSI ASIC design • $M;.()$;.()+&$N%67$78$$ $O$P&-'1&$Q8R$;4,1&$,(-$40S&"$"&T'."&3&(/;$$ $O$P&-'1&$/0/,+$10;/$ • $M;.()$=,"-S,"&$-&;1".4:0($+,()',)&$,(-$ 8*!$/00+;$A0"$-&;.)(.()$$ • $$!&;.)(.()$,44"0,1=&;$U$ O$V'++@1';/03$-&;.)($ O$6&3.@1';/03$-&;.)($ Dr. Le Dung Hanoi University of Science and Technology Full-custom design (1) • $$W,/&$25$),/&$-&;.)(.()$S./=$/=&$4=5;.1,+$+,50'/$0A$&,1=$ .( X ',+$/",(;.;/0"$,(-$/=&$.(/&"10((&1:0(;$2&/S&&($/=&3#$ Y,1=$/",(;.;/0"$,(-$&,1=$10((&1:0($.;$-&;.)(&-$.( X ',++5$,;$ ,$;&/$0A$"&1/,()+&;$ 9/25/13 4 Dr. Le Dung Hanoi University of Science and Technology Full-custom design (2) O$$R0/=$/=&$1."1'./$4&"A0"3,(1&$,(-$/=&$;.+.10($,"&,$1,($ 2&$04:3.Z&-$E';.()$Y8*!$/00+;J$ @$YH/"&3&+5$+,20"@.(/&(;.X&$/0$.34+&3&(/$ @$[.)=$10;/$0A$3,;L$;&/;$ @$7(1"&,;.()$3,('A,1/'".()$,(-$-&;.)($:3&$$ $$<.3&@/0@3,"L&/$1034&::0($ Dr. Le Dung Hanoi University of Science and Technology Semi-custom design • $6&3.@1';/03$-&X.1&$$ $O$=,;$4"&-&;.)(&-$4,"/;$$$ • $6&3.@1';/03$-&;.)($,44"0,1=&;$ $$6/,(-,"-$1&++$2,;&-$-&;.)($ $$W,/&$,"",5$2,;&-$-&;.)($ $$Q"0)",33,2+&$-&X.1&;$2,;&-$-&;.)($$$ 9/25/13 5 Dr. Le Dung Hanoi University of Science and Technology Standard cell based design (1) \ %.2","5$0A$;/,(-,"-$1&++;$ O$Y,1=$1&++$.;$,$),/&$$$ O$6,3&$=&.)=/D$X,".,2+&$S /=D$.(/&"+&,X&-$25$"0':()$1=,((&+;$ O$*++$.(4'/;$,/$/=&$/04D$,++$0'/4'/;$,/$/=&$20]03$ \ *$-&;.)(&"$;&+&1/;$1&++;$A"03$,$-&;.)($+.2,","5D$;4&1.A5.()$ S=&"&$/=&5$;=0'+-$2&$4+,1&-$0($/=&$78$,(-$/=&($ 1/,:()$=0S$/=&5$;=0'+-$2&$.(/&"10((&1/&-#$ \ V,;/&"$-&;.)($0A$30"&$1034+&H$2'.+ ()$2+01L;$ \ 6.+.10($A0'(-".&;$-&;.)($,(-$;&++$;'1=$04:3.Z&-$+.2",".&;$ A0"$/=&."$4"01&;;.()$/&1=(0+0)5$ Dr. Le Dung Hanoi University of Science and Technology Basic process standard cell based design !"#$%&'&()* +, %(* 9/25/13 6 Dr. Le Dung Hanoi University of Science and Technology [,"-S,"&$!&;1".4:0($%,()',)& Synthesis Translate HDL descriptions into logic gate networks in a particular library Dr. Le Dung Hanoi University of Science and Technology %0).1$65(/=&;.;$Q=,;&; • Logic optimization transforms current gate-level network into an equivalent gate-level network more suitable for technology mapping. • Technology mapping transforms the gate-level network into a netlist of gates (from library) which minimizes total cost. 9/25/13 7 %.2","5$0A$;/,(-,"-$1&++$$ /0123!23 * *4 ********5* 06074 * *8** ******59:** 06078 * *: ******59;* 0607: * *< ******494* 6=/45* **: ******59;* >2??@* *******>=@! ****72?6A ***@ABC=? ** ********** ******D6!!230 ** Dr. Le Dung Hanoi University of Science and Technology CMOS AND-OR-Invert Gate* 6%*"E,+-'"*&F*GH,%I,JI*#"''*H"#$%&'&()*+, %(*K5L$ Dr. Le Dung Hanoi University of Science and Technology 9/25/13 8 6%*"E,+-'"*&F*GH,%I,JI*#"''*H"#$%&'&()*+, %(*K4L$ @)%H$"G.G* Dr. Le Dung Hanoi University of Science and Technology Netlist of gates (from library) which minimizes total cost. D$,G"G*&F*G)%H$"G.G*K5M8L$ 59 /%I"-"%I"%H*HJ,%GF&J+,N&%G*K&-N+.O,N&%LU$ Dr. Le Dung Hanoi University of Science and Technology 9/25/13 9 D$,G"G*&F*G)%H$"G.G*K5M8L* Dr. Le Dung Hanoi University of Science and Technology 59 /%I"-"%I"%H*HJ,%GF&J+,N&%G*K&-N+.O,N&%LU$ D$,G"G*&F*G)%H$"G.G*K5M8L* Dr. Le Dung Hanoi University of Science and Technology 59 /%I"-"%I"%H*HJ,%GF&J+,N&%G*K&-N+.O,N&%LU$ 9/25/13 10 D$,G"G*&F*G)%H$"G.G*K5M8L* Dr. Le Dung Hanoi University of Science and Technology 59 /%I"-"%I"%H*HJ,%GF&J+,N&%G*K&-N+.O,N&%LU$ D$,G"G*&F*G)%H$"G.G*K5M8L* Dr. Le Dung Hanoi University of Science and Technology 59 /%I"-"%I"%H*HJ,%GF&J+,N&%G*K&-N+.O,N&%LU$ [...]... of Science and Technology Gate array based design + A gate array or uncommitted logic array (ULA) circuit is prefabricated with a number of unconnected logic gates (cells) + CMOS transistors with fixed length and width are placed at regular predefined positions and manufactured on a wafer, usually called a master slice ( sea of gates) + Creation of a circuit with a specified function is accomplished... function of the chip to be customized as desired reducing the designing time Cell I/O buffer reducing the mask costs Customized metal layer for + Disadvantages connecting gate - slow clock speed - wasted chip area Sea of gates Fixed transistor layer Dr Le Dung Hanoi University of Science and Technology 21 9/25/13 Gate array based design flow Design entry Technology mapping Simula:on Library... Hanoi University of Science and Technology Bidirec:onal Pins and Feedback line Dr Le Dung Hanoi University of Science and Technology 25 9/25/13 PLD Design Process Dr Le Dung Hanoi University of Science and Technology Combina:onal Circuit is implemented on SPLD Dr Le Dung Hanoi University of Science and Technology 26 9/25/13 PROM = Read-‐Only-‐Memory Dr Le Dung Hanoi University... Technology PAL Dr Le Dung Hanoi University of Science and Technology 28 9/25/13 Combina:onal Circuit is implemented PAL Dr Le Dung Hanoi University of Science and Technology FPLA Programmable AND array Dr Le Dung Programmable OR array Hanoi University of Science and Technology 29 9/25/13 Combina:onal Circuit is implemented on FPLA (1) Minimize each func:on separately 8 product... mapping Simula:on Library of cells Placement Rou:ng Timing simula:on Fabrica:on (metal 1 mask) Tes:ng Dr Le Dung Hanoi University of Science and Technology Programmable Device Based Design Based on programmable devices: The interconnection layers are personalized by electronic means for a specific application This work usually can be done by end-users F0 = A’B’+ AC’ F1 = B + AC’... Mul:ple-‐Output Op:miza:on 5 product terms F1 = abd + a’bd + ab’c’+ b’c F2 = a’bd + b’c + bc F3 = abd + ab’c’+ bc Hanoi University of Science and Technology Combina:onal Circuit is implemented on FPLA (2) F1 = abd + a’bd + ab’c’+ b’c F2 = a’bd + b’c + bc F3 = abd + ab’c’+ bc Dr Le Dung Hanoi University of Science and Technology 30 9/25/13