The complete verilog book

THE COMPLETE VERILOG BOOK THE COMPLETE VERILOG BOOK by Vivek Sagdeo Sun Micro Systems, Inc. KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW eBook ISBN: 0-306-47658-4 Print ISBN: 0-7923-8188-2 ©2002 Kluwer Academic Publishers New York, Boston, Dordrecht, London, Moscow Print ©1998 Kluwer Academic Publishers A ll rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America Visit Kluwer Online at: http://kluweronline.com and Kluwer's eBookstore at: http://ebooks.kluweronline.com D ordrecht CD-ROM available only in print edition. To My Parents, Sons-Parth and Nakul, Anjali, Friends LIST OF FIGURES 8 14 14 15 17 25 45 64 68 82 86 91 93 93 94 94 95 136 217 222 223 230 245 246 247 248 248 291 313 317 Figure 1-1. Figure 1-2. Figure 1-3. Figure 1-4. Figure 1-5. Figure 2-1. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 4-6. Figure 4-7. Figure 6-1. Figure 11-1. Figure 11-2. Figure 11-3. Figure 11-4. Figure 12-1. Figure 12-2. Figure 12-3. Figure 12-4. Figure 12-5. Figure 14-1. Figure 16-1. Figure 17-1. Block Diagram of a System with Processor, Main Memory, and Cache Bottom-up Methodology and Verilog Language Features Support Top-Down Methodology and Equivalent Verilog Language Features Support Typical Design Flow with Verilog Verilog Keywords Tables of Net Types and Resolution Functions Tables of Operators in Verilog Used for Evaluating Expressions Schematics for the Adder in Example 3-28 Top Level Block Diagram of r4200 UltraSPARC-IIi Block Diagram Schematics for Example 4-1 Network Data Structure for the andor Verilog Model in Example 4-1 Schedule of Events for a Verilog Model Algorithm for Verilog Model Execution Algorithm for Processing an Event Order of Events at a Time and Event Structure Diagrams Algorithm for Scheduling an Event Tables for Each Built-in Gate in Verilog State Diagram for Cache Controller with Write-Back Policy Block Diagram for the Cache Controller with Write-Back Policy Containing Dirty Bits State Transition Diagram for the Cache Controller with Write-Back Policy Block Diagram for a Cache System Typical Design Flow with Verilog Including Synthesis Logic Synthesis Components of Verilog Based Synthesis Components of Behavioral Synthesis with Verilog Traditional View (Class A or Mealy Machine) of a Sequential Design Modern View (Class A – Sagdeo Machine) of a Sequential Design Sharings Adders Amongst Different Operations in Example 14-1 C Interface Components for Verilog HDL Schematics for a Static RAM Cell with Bidirectionals and Strengths PREFACE The Verilog hardware description language (HDL) provides the ability to describe digital and analog systems. This ability spans the range from descriptions that express conceptual and architectural design to detailed descriptions of implementations in gates and transistors. Verilog was developed originally at Gateway Design Automation Corporation during the mid-eighties. Tools to verify designs expressed in Verilog were implemented at the same time and marketed. Now Verilog is an open standard of IEEE with the number 1364. Verilog HDL is now used universally for digital designs in ASIC, FPGA, microprocessor, DSP and many other kinds of design-centers and is supported by most of the EDA companies. The research and education that is conducted in many universities is also using Verilog. This book introduces the Verilog hardware description language and describes it in a comprehensive manner. Verilog HDL was originally developed and specified with the intent of use with a simulator. Semantics of the language had not been fully described until now. In this book, each feature of the language is described using semantic introduction, syntax and examples. Chapter 4 leads to the full semantics of the language by providing definitions of terms, and explaining data structures and algorithms. The book is written with the approach that Verilog is not only a simulation or synthesis language, or a formal method of describing design, but a complete language addressing all of these aspects. This book covers many aspects of Verilog HDL that are essential parts of any design process. It has the view of original development, and also encompasses changes and additions in subsequent revisions. The book starts with a tutorial introduction in chapter 1, then explains the data types of Verilog HDL in chapter 2. Today´s object-oriented world knows that the language-constructs and data-types are equally important parts of a programming language. Chapter 3 explains the three views of a design object: behavioral, RTL and structural. Each view is then described in detail, including the semantic introduction, example and syntax for each feature, in chapters 3, 5 and 6. Verilog takes the divide and conquer approach to the language design by separating various types of constructs using different syntax and semantics. The syntax and semantics include features to describe design using the three levels of abstractions, features for simulation control and debug, preprocessor features, timing descriptions, programming language interface and miscellaneous system tasks and functions. System tasks and functions that are useful for non-design descriptions, such as input-output, are described in chapters 8 and 10. The preprocessor enables one to define text substitutions and to include files, which are defined in chapter 9. The building of systems using all features is explained in chapter 11. Synthesis is an essential part of today´s design process, and Verilog HDL usage for synthesis requires special language understanding. The understanding needed is provided in chapters 11 to 13. Timing descriptions form a separate class of features in Verilog and are described in chapter 15. Chapter 17 describes how programming language interface (PLI) provides access to Verilog data structures and simulation information via common data definitions and routines. Standard Delay Format, which is discussed in chapter 18, extends capabilities of timing descriptions of specific blocks in Verilog, and is used in ASIC designs extensively. Chapter 19 enunciates the analog extensions to Verilog in the form of Verilog-A and Verilog-MS. Simulation speed is an important part of Verilog HDL usage, and a large part of the design cycle is spent in design verification and simulation. Some techniques to enhance this speed are discussed in chapter 20. The book keeps the reader abreast of current developments in the Verilog world, such as Verilog-A, cycle simulation, SDF, DCL and uses IEEE 1364 syntax. I hope that this book will be useful to all of those who are new to Verilog HDL, to those who want to learn additional facets, and to those who would like a reference book during the development of a hardware design or software tool with Verilog HDL. I wish for you to design and implement some interesting designs of ASICs, FPGAs, microprocessors, caches, memories, boards, systems and/or tools like simulators, synthesizers, timing analyzers, formal verifiers with Verilog HDL, and to have a lot of fun doing so. Vivek Sagdeo ACKNOWLEDGEMENTS A book of this size takes many different things to come together . I would like to acknowledge Carl Harris of Kluwer for encouragement and for facilitating the creation of manuscript. Jackie Denfeld handled the creation of final manuscript in a short time well. Tedd Corman provided the editorial review and my experience of working with him in the past on simulation and HDLs has been valuable. Satish Soman provided feedback from the design perspective. UC Berkeley extension provided the teaching environment for me that has added the academic dimension to this book. Dr Richard Tsina, Joan Siau and Roxanne Giovanetti from UCB deserve mention for their support. Students of the class “Digital Design of Verilog HDL” from UCB and PerformancAE kept the book-writing interesting and live. My coworkers from SUN microsystems have been very cooperative and accomodating and have really good insight into digital design and microprocessors. While working at Gateway Design where Verilog was designed and implemented, a terrific team was in place. Prabhu Goel, Barry Rosales, Manoj Gandhi, Phil Moorby, Ronna Alintuck and many from Marketing and Sales made this work on Verilog and well-rounded. Over the several years, experiences of working at Gateway(Cadence), Viewlogic, Silicon Graphics, Meta Software, Philips Semi and SUN Microsystems and IEEE 1364 have provided the background to cover many aspects of Verilog including language, digital and analog, system and microprocessors and have given a perspective that has made this work possible. I acknowledge all those whose names can’t be mentioned for lack of space but have been part of various projects with me. DISCLAIMER This DISK (CD ROM) is distributed by Kluwer Academic Publishers with *ABSOLUTELY NO SUPPORT* and *NO WARRANTY* from Kluwer Academic Publishers. Use or reproduction of the information provided on this DISK (CD ROM) for commercial gain is strictly prohibited. Explicit permission is given for the reproduction and use of this information in an instructional setting provided proper reference is given to the original source. Kluwer Academic Publishers shall not be liable for damage in connection with, or arising out of, the furnishing, performance or use of this DISK (CD ROM). TABLE OF CONTENTS 1. INTRODUCTION TO VERILOG HDL 1 1.1 1.2 1.3 1.4 1.5 1 1 2 2 2 7 8 Language Motivation 1.1.1 1.1.2 1.1.3 Language Design Verilog World Accessory Specifications Tutorial Via Examples 1.2.1 1.2.2 1.2.3 1.2.4 Counter Design Factorial Generator System Design with Processor, Memory, and Cache Cache System - Behavioral Model Overview of Verilog HDL 1.3.1 1.3.2 1.3.3 1.3.4 Correspondence To Digital Hardware Typical Design Flow with Verilog List of Keywords Comment Syntax Syntax Conventions Exercises 2. DATA TYPES IN VERILOG 2.1 2.2 2.3 Overview Value Systems Data Declarations 2.3.1 2.3.2 2.3.3 Introduction Examples Syntax 2.4 2.5 2.6 Reg Declaration 2.4.1 2.4.2 2.4.3 Introduction Examples Syntax Net Declaration 2.5.1 2.5.2 2.5.3 Introduction Syntax Examples Port Types 2.6.1 2.6.2 2.6.3 Introduction Examples Syntax 2.7 Aggregates – 1 and 2 Dimensional Arrays (Vectors and Memories) 2.7.1 2.7.2 2.7.3 Introduction Examples Syntax 10 13 13 15 17 17 18 19 21 21 21 22 22 23 23 23 23 24 24 24 24 28 29 29 29 30 30 31 31 31 32 1 [...]... hardware, the processor, the memory and the cache are modeled with their interfaces, in the three modules named Processor, Memory and Cache The module System instantiates all three blocks and connects the signals to the modules, thereby creating the network The data, address buses on the processor side are procData and procAddr and on the memory side are memData and memAddr The cache block connects the two... the output of the gate-level simulation (step 4) against the output of the original Verilog description simulation (step 3) to verify that the implementation is correct 5 The synthesis tools can be used at behavioral and at the RTL level The RTL level is synthesized using techniques that are commonly known as logic synthesis In this book, the major components of this flow will be discussed The various... of the design The gatelevel description has the same port and module definitions as the original highlevel Verilog description 1 The gate-level Verilog description from step 3 is now passed through the Verilog simulator You can use the original Verilog simulation drivers from steps 1 and 2 because module and port definitions are preserved through the translation and optimization processes Compare the. .. of the blocks in step 1 Thus, correctness of all signals at the (logic) synthesizable blocks are tested in this step 3 Synthesize the HDL description with the synthesizer In a typical Synthesizer like Synopsys, this step is divided into two parts—HDL Compilation and the Design Compilation Synthesizer performs architectural optimizations, then creates an internal representation of the design Use the. .. The description in Example 1-1 begins with the word “module” and ends with the word “endmodule” The interface to the module is described in the same line as module name “d_edge_ff_gates” The direction of each port in the interface list is described in the following lines beginning with the words like “inout” and “input” The “nand” statement has six instances of nand gates with names nl through n6 The. .. WIDTH Entry 18.8.9 The PERIOD Entry 18.8.10 The NOCHANGE Entry Timing Environment and Constraints 18.9.1 The PATHCONSTRAINT Entry 18.9.2 The PERIODCONSTRAINT Construct 18.9.3 The SUM Entry 18.9.4 The DIFF Constraint 18.9.5 The SKEWCONSTRAINT Entry Timing Environment – Information Entries 18.10.1 The ARRIVAL Construct 18.10.2 The DEPARTURE Construct 18.10.3 The SLACK Construct 18.10.4 The WAVEFORM Construct... then be varied if desired Notice that these are done outside the module and will be applicable throughout the file for all modules in it The module cache has a port-interface and certain reg and memory declarations are done in the beginning This is followed by initial block defining initialization or reset operation Then the always block as described in the previous paragraph is added to complete the. .. Entry 18.5.1 The CELLTYPE entry 18.5.2 The Cell Instance Entry Timing Specifications 18.6.1 Delay Type – Absolute 18.6.2 The INCREMENT keyword 18.6.3 The PATHPULSE Entry 18.6.4 The PATHPULSEPERCENT Entry Delay Definitions 18.7.1 The Delay Data 18.7.2 Delay Value 18.7.3 The IOPATH Entry 18.7.4 Conditionals 18.7.5 The RETAIN Entry 18.7.6 The PORT Entry 18.7.7 The INTERCONNECT Entry 18.7.8 The DEVICE Entry... 1-1 The flip-flop was built using predefined nand gate while the counter is built hierarchically using a module defined earlier Again, the definition of this block is enclosed between the keywords “module” and “endmodule” and the interface list is described at the top of the module The four flip-flops are instantiated using the name of the module “d_edge_ff_gates” followed by names (dffl-dff4) and the. .. 1 In Example 1-8, the factorial module generates the factorial of a number algorithmically This design module instantiated in a test module and the two modules communicate via the ports n and fact The module factorial contains an 'always' block that executes based on an event on n The ‘for’ loop computes the value of the factorial using the loop variable i and the limiting value n The test module contains . THE COMPLETE VERILOG BOOK THE COMPLETE VERILOG BOOK by Vivek Sagdeo Sun Micro Systems, Inc. KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW eBook ISBN: 0-306-47658-4 Print. Definitions 18.7.1 18.7.2 18.7.3 18.7.4 18.7.5 18.7.6 18.7.7 18.7.8 The Delay Data Delay Value The IOPATH Entry Conditionals The RETAIN Entry The PORT Entry The INTERCONNECT Entry The DEVICE Entry Timing Check Entries The SETUP Entry The HOLD Entry The SETUPHOLD. other kinds of design-centers and is supported by most of the EDA companies. The research and education that is conducted in many universities is also using Verilog. This book introduces the Verilog