Recognized as an American National Standard (ANSI) The Institute of Electrical and Electronics Engineers, Inc. 345 East 47th Street, New York, NY 10017-2394, USA Copyright © 1996 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published 1996. Printed in the United States of America ISBN 1-55937-727-5 No part of this publication may be reproduced in any form, in an electronic retrieval system or otherwise, without the prior written permission of the publisher. IEEE Std 1364-1995 IEEE Standard Hardware Description Language Based on the Verilog ¨ Hardware Description Language Sponsor Design Automation Standards Committee of the IEEE Computer Society Approved 12 December 1995 IEEE Standards Board Approved 1 August 1996 American National Standards Institute Abstract: The Verilog ¨ Hardware Description Language (HDL) is defined. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both ma- chine readable and human readable, it supports the development, verification, synthesis, and test- ing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the imple- mentors of tools supporting the language and advanced users of the language. Keywords: computer, computer languages, electronic systems, digital systems, hardware, hard- ware design, hardware description languages, HDL, programming language interface, PLI, Verilog HDL, Verilog PLI, Verilog ¨ IEEE Standards documents are developed within the Technical Committees of the IEEE Societies and the Standards Coordinating Committees of the IEEE Standards Board. Members of the com- mittees serve voluntarily and without compensation. They are not necessarily members of the Insti- tute. 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Permission to photocopy portions of any individual standard for educational class- room use can also be obtained through the Copyright Clearance Center. Note: Attention is called to the possibility that implementation of this standard may require use of subject matter covered by patent rights. By publication of this standard, no position is taken with respect to the existence or validity of any patent rights in connection therewith. The IEEE shall not be responsible for identifying all patents for which a license may be required by an IEEE standard or for conducting inquiries into the legal validity or scope of those patents that are brought to its attention. iii Introduction (This introduction is not a part of IEEE Std 1364-1995, IEEE Standard Hardware Description Language Based on the Verilog ¨ Hardware Description Language.) The Verilog ¨ Hardware Description Language (Verilog HDL) was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including veriÞcation simulation, timing analysis, test analysis, and synthesis. The Verilog HDL was designed by Phil Moorby during the winter of 1983Ð1984, and it was introduced into the EDA market in 1985 as the corner- stone of a veriÞcation simulator product. The Verilog HDL contains a rich set of built-in primitives, including logic gates, user-deÞnable primitives, switches, and wired logic. It also has device pin-to-pin delays and timing checks. The mixing of abstract lev- els is essentially provided by the semantics of two data types: nets and registers. Continuous assignments, in which expressions of both registers and nets can continuously drive values onto nets, provide the basic struc- tural construct. Procedural assignments, in which the results of calculations involving register and net values can be stored into registers, provide the basic behavioral construct. A design consists of a set of modules, each of which has an I/O interface and a description of its function, which can be structural, behavioral, or a mix. These modules are formed into a hierarchy and are interconnected with nets. The Verilog language is extensible via the Programming Language Interface (PLI). The PLI is a collection of routines that allows foreign functions to access information contained in a Verilog HDL description of the design and facilitates dynamic interaction with simulation. Applications of PLI include connecting to a Ver- ilog HDL simulator with other simulation and CAD systems, customized debugging tasks, delay calculators, and annotators. The language that inßuenced Verilog HDL the most was HILO-2, which was developed at Brunel University in England under a contract to produce a test generation system for the British Ministry of Defense. HILO-2 successfully combined the gate and register transfer levels of abstraction and supported veriÞcation simula- tion, timing analysis, fault simulation, and test generation. In 1990, Cadence Design Systems placed the Verilog HDL into the public domain and the independent Open Verilog International (OVI) was formed to manage and promote Verilog HDL. In 1992, the Board of Directors of OVI began an effort to establish Verilog HDL as an IEEE standard. With many designers all over the world designing electronic circuits with Verilog HDL, this idea was enthusiasti- cally received by the Verilog user community. When the Project Authorization Request (1364) was approved by the IEEE in 1993, a working group was formed and the Þrst meeting was held on October 14, 1993. Objective The starting point for the IEEE P1364 Working Group were the OVI LRM version 2.0 and OVI PLI versions 1.0 and 2.0. The standardization process started with the clear objective of making it easier for the user to understand and use Verilog. The IEEE P1364 standard had to be clear, unambiguous, implementable, and not overly constraining. Since Verilog HDL has been in use for some time, it was quite robust enough to be pre- sented to the user community without a great deal of enhancements. The working group, therefore, decided not to spend a lot of time extending the language, but, for the purpose of this standardization, to concentrate on clarifying the language. Since Verilog HDL has been in widespread use and a number of ASIC vendors have built extensive libraries in Verilog HDL, it was very important to maintain the integrity of these existing models. With this in mind, it iv was decided that the intent of the working group would be to maintain the integrity of the standard and every care would be taken not to invalidate existing models. The standardization process In order to clarify the language, many changes were proposed from a number of sources. The working group met 15 times over a period of 18 months and voted on nearly 400 motions. Four drafts of the document were generated and reviewed. It is a tribute to the hard work and dedication put forward by all the members of the working group that this standard was completed in the short span of 18 months. Many new sections were created, one of which is the section on scheduling semantics. A number of sections were merged to form new sections. The two annexes containing compiler directives and system tasks were moved into main text as two sections. Every effort has been made to clarify all ambiguities, add explana- tions, and delete references that were deemed unnecessary. Changes also included removing product speciÞc references and restrictions. The minimum product require- ments for implementing this standard were clariÞed. A number of examples, Þgures, and tables were retained in order to provide better context and explanation. The PLI Task Force provided a clear and accurate description of OVI PLI 1.0 implementations already in existence, and revisited the OVI PLI 2.0 speciÞcation to ensure its accuracy and completeness. The baseline for the access routines and the task/function routines was the OVI PLI 1.0 speciÞcation. As there are a large number of OVI PLI 1.0 routines in widespread use that were not included in the OVI PLI 1.0 document, it was decided to consider additions to this document from the pool of existing OVI PLI 1.0 implementations. The access routines and the task/function routines provide full backwards compatibility with Verilog HDL software tools and PLI applications. The baseline for the VPI routines was the existing OVI PLI 2.0 document. To this, the task force brought new experience from the implementations in progress, which helped prove the worthiness of the previously untested speciÞcation. Acknowledgments This standard is based on work originally developed by Cadence Design Systems, Inc. (in their Verilog LRM 1.6 and 2.0 and PLI documents) and Open Verilog International (in their Verilog LRM 2.0 and PLI 1.0 and 2.0). The IEEE is grateful to Cadence Design Systems and Open Verilog International for permission to use their materials as the basis for this standard. The IEEE Std 1364-1995 working group organization Many individuals from many different organizations participated directly or indirectly in the standardization process. The main body of the IEEE P1364 working group is located in the United States, with a subgroup in Japan. Over a period of 18 months many task forces were created, of which the PLI task force was prominent. The members of the IEEE P1364 working group had voting privileges, and all motions had to be approved by this group to be implemented. All task forces and subgroups focused on some speciÞc areas, and their recommendations were eventually voted on by the IEEE P1364 working group. v At the time this document was approved, the IEEE P1364 working group had the following membership: Maqsoodul (Maq) Mannan, Chair Yoshiharu Furui, Vice Chair (Japan) Alec G. Stanculescu, Vice Chair (USA) Lynn A. Horobin, Secretary Yatin Trivedi, Technical Editor Victor Berman John Mancini John Sanguinetti Leigh Brady Michael McNamara Joseph P. Skudlarek Clifford E. Cummings Elliot Mednick Stuart Sutherland Peter Eichenberger Phil Moorby John R. Williamson Andrew T. Lynch Gabe Moretti Alex N. ZamÞrescu The PLI task force consisted of the following members: Andrew T. Lynch, PLI Task Force Leader Stuart Sutherland, Technical Editor Charles A. Dawson Joel Paston Marco Zelado Rajeev Madhavan Sathyam K. Pattanam Guoqing Zhang David Roberts The IEEE P1364 Japan subgroup consisted of the following members: Yoshiharu Furui, Vice-Chair, IEEE-1364 Working Group Takaaki Akashi Junichi Murayama Toshiyuki Sakamoto Kasumi Hamaguchi Masaharu Nakamura Hitomi Sato Masato Ikeda Shouhei Oda Katsushida Seo Masaru Kakimoto Fujio Otsuka Mitsuhiro Yasuda Kazuya Morii Kazuhiro Yoshinaga The following persons were members of the balloting group: Guy Adam H. Gordon Adshead Unmesh Agarwala Anant Agrawal John Ainscough Takaaki Akashi Tom Albers Glen Anderson Lawrence F. Arnstein Michael Atkin Venkata Atluri Rick Bahr Jim Ball Jose Baradiaran Daniel S. Barclay David L. Barton Jean-Michel Berge Victor Berman J. Bhasker Ron Bianchini William D. Billowitch Ronald D. Blanton Miriam Blatt James Brandt Dennis B. Brophy Randal E. Bryant John A. Busco Ben Buzonas L. Richard Carley Thomas Chao Daniel Chapiro Clive R. Charlwood Chin-Fu Chen Mojy C. Chian Kai Moon Chow Michael D. Ciletti Joseph C. Circello Luc Claesen George M. Cleveland Edmond S. Cooley Tedd Corman David Crohn Clifford E. Cummings Godfrey Paul D'Souza Brian A. Dalio Carlos Dangelo Hal Daseking Timothy R. Davis Charles A. Dawson Willem De Lange Rajiv Deshmukh Caroline DeVore-Kenney Allen Dewey Bill Doss Douglas D. Dunlop Peter Eichenberger Hazem El Tahawy John A. Eldon Bassam N. Elkhoury Ted Elkind Brian Erickson Robert A. Flatt Bob Floyd Alain Blaise Fonkoua Douglas W. Forehand Paul Franzon Bill Fuchs vi Yoshiharu Furui Vassilios Gerousis Emil Girczyc Rita A. Glover Timothy G. Goldsbury Alan Goodrum Suresh Gopalakrishnan Harutaka Goto Kenji Goto Brian GrifÞn Steve Grout Kazuyuki Hagiwara Michael J. Haney James P. Hanna Anne C. Harris Akira Hasegawa Stuart Hecht Shankar Hemmady John Hillawi Chris N. Hinds Kazuyuki Hirakawa Fumiyasu Hirose Lynn A. Horobin Tamio Hoshino May Huang Sylvie Hurat Masaharu Imai Ann Irza Mitsuaki Ishikawa Yoshi Ishizaka David Jakopac Paul Jeffs Roger Jennings Eugene E. Jones Richard Jones Tetsuro Kage Masaru Kakimoto Osamu Karatsu Jake Karrfalt Kaoru Kawamura Masamichi Kawarabayashi Pratibha Kelapure Khozema Khambati Bruce Kim Choon B. Kim Tsutomu Kimoto Chris Kingsley Masayuki Koyama Tokinori Kozawa Sarangan K. Kumar Ramachandra P. Kunda Douglas Laird Jean Lebrun Bill Ledbetter Hung-Yi Lee Shawn Leonard Oz Levia George Lippincott Herbert Lopez-Aguado Jin-Qin Lu Andrew T. Lynch Viranjit S. Madan Rajeev Madhavan Naotaka Maeda Serge Maginot James Magro Wojciech P. Maly Maqsoodul Mannan Guillermo Maturana Michael McNamara Paul J. Menchini Jean Mermet Gerald T. Michael Glen S. Miranker Shankha Mitra Kristan Monsen John T. Montague Patrick Moore Gabe Moretti David S. Morris Chandra Moturu Wolfgang Mueller Shankar Ranjan Mukherjee Yoshiaki Nagashima David Nagle Hiroshi Nakamura Hiroshi Nakamura Seiji Nakamura Zainalabedin Navabi Sivaram K. Nayudu Robert N. Newshutz Jun Numata John W. OÕLeary Tetsuya Okabe Vincent Olive Yoichi Onishi Samir Palnitkar Mark Papamarcos David M. Parry Rajesh Patil Robert A. Pease Mitchell Perilstein Bruce Petrick John Petry Robert Piloty Juan Pineda Ron Poon Jan Pukite Selliah Rathnam David Rich John P. Ries Hemant G. Rotithor Jacques Rouillard Paul Rowbottom Jon Rubinstein Stefan Rusu Rob A. Rutenbar Karem A. Sakallah Toshiyuki Sakamoto John Sanguinetti Hitomi Sato Larry F. Saunders Quentin Schmierer Michael L. Seavey Alex Seibulescu Shailesh Shah Moe Shahdad Ravi Shankar Charles Shelor John P. Shen Hiroshi Shiraishi Toru Shonai Alexander A. Silbey Supreet Singh Joseph P. Skudlarek David M. Smith David R. Smith William Bong H. Soon Larry P. Soule John Spittal Chakra R. Srivatsa Joseph J. Stanco Alec G. Stanculescu Jay K. Strosnider Stuart Sutherland Kinya Tabuchi Atsushi Takahara Donald Thomas Partha Tirumalai Jose A. Torres Paul Traynar Richard Trihy Yatin Trivedi Shunjen Tsay Radha Vaidyanathan Arie van Rhijn Kerry Veenstra Venkat V. Venkataraman Sanjay Vishin Robert A. Walker Tsu-Hua Wang John J. Watters Ronald Waxman J. Richard Weger Paul Weil John R. Williamson John C. Willis Claudia H. Ye William R. Young Tetsuo Yutani Alex N. ZamÞrescu Guoqing Zhang vii When the IEEE Standards Board approved this standard on 12 December 1995, it had the following mem- bership: E. G. ÒAlÓ Kiener, Chair Donald C. Loughry, Vice Chair Andrew G. Salem, Secretary *Member Emeritus Also included are the following nonvoting IEEE Standards Board liaisons: Satish K. Aggarwal Steve Sharkey Robert E. Hebner Chester C. Taylor Mary Lynne Nielsen IEEE Standards Project Editor Verilog is a registered trademark of Cadence Design Systems, Inc. Gilles A. Baril Clyde R. Camp Joseph A. Cannatelli Stephen L. Diamond Harold E. Epstein Donald C. Fleckenstein Jay Forster* Donald N. Heirman Richard J. Holleman Jim Isaak Ben C. Johnson Sonny Kasturi Lorraine C. Kevra Ivor N. Knight Joseph L. KoepÞnger* D. N. ÒJimÓ Logothetis L. Bruce McClung Marco W. Migliaro Mary Lou Padgett John W. Pope Arthur K. Reilly Gary S. Robinson Ingo RŸsch Chee Kiow Tan Leonard L. Tripp Howard L. Wolfman viii Contents Section 1 Overview 1 Section 2 Lexical conventions 5 Section 3 Data types 13 Section 4 Expressions 27 Section 5 Scheduling semantics 45 Section 6 Assignments 50 Section 7 Gate and switch level modeling 55 Section 8 User-defined primitives (UDPs) 87 Section 8 Behavioral modeling 98 Section 10 Tasks and functions 125 Section 11 Disabling of named blocks and tasks 132 Section 12 Hierarchical structures 135 Section 13 Specify blocks 152 Section 14 System tasks and functions 172 Section 15 Value change dump (VCD) file 207 Section 16 Compiler directives 219 Section 17 PLI TF and ACC interface mechanism 228 Section 18 Using ACC routines 234 Section 19 ACC routine definitions 270 Section 20 Using TF routines 444 Section 21 TF routine definitions 449 Section 22 Using VPI routines 525 Section 23 VPI routine definitions 554 Annex A Formal syntax definition 594 Annex B List of keywords 604 ix Annex C The acc_user.h file 605 Annex D The veriuser.h file 615 Annex E The vpi_user.h file 622 Annex F System tasks and functions 635 Annex G Compiler directives 642 Annex H Bibliography 644 Section 1 1 IEEE Standard Hardware Description Language Based on the Verilog ¨ Hardware Description Language Section 1 Overview 1.1 Objectives of this standard The intent of this standard is to serve as a complete speciÞcation of the Verilog ¨ Hardware Description Language (HDL). This document contains Ñ The formal syntax and semantics of all Verilog HDL constructs Ñ Simulation system tasks and functions, such as text output display commands Ñ Compiler directives, such as text substitution macros and simulation time scaling Ñ The Programming Language Interface (PLI) binding mechanism Ñ The formal syntax and semantics of access routines, task/function routines, and Verilog procedural interface routines Ñ Informative usage examples Ñ Listings of header Þles for PLI 1.2 Conventions used in this standard This standard is organized into sections, each of which focuses on some speciÞc area of the language. There are sub- clauses within each section to discuss individual constructs and concepts. The discussion begins with an introduction and an optional rationale for the construct or the concept, followed by syntax and semantic descriptions, followed by some examples and notes. The verb ÒshallÓ is used through out this standard to indicate mandatory requirements, whereas the verb ÒcanÓ is used to indicate optional features. These verbs denote different meanings to different readers of this standard: [...]... to convey some semantic information For example, msb_constant_expression and lsb_constant_expression are equivalent to constant_expression The main text uses italicized font when a term is being deÞned, and constant-width font for examples, Þle names, and while referring to constants, especially 0, 1, x, and z values 2 Section 1 THE VERILOG HARDWARE DESCRIPTION LANGUAGE IEEE Std 1364-1995 1.4 Contents... bit-select, without any operator is considered an expression Wherever a value is needed in a Verilog HDL statement, an expression can be used Some statement constructs require an expression to be a constant expression The operands of a constant expression consist of constant numbers, parameter names, constant bit-selects of parameters, and constant part-selects of parameters only, but they can use any of... described in sections 17, 23, and 25 Additional $identiÞer system tasks and functions deÞned by software implementations Any valid identiÞer, including keywords already in use in contexts other than this construct, can be used as a system task or function name The system tasks and functions described in Section 14 are part of this standard Additional system tasks and functions with the $identiÞer construct... speciÞcation gives addresses to the individual bits in a multibit net or register The most signiÞcant bit speciÞed by the msb constant expression is the left-hand value in the range and the least signiÞcant bit speciÞed by the lsb constant expression is the right-hand value in the range Both msb constant expression and lsb constant expression shall be constant expressions The msb and lsb constant expressions... conversion shall take place when a real number is assigned to an integer The ties shall be rounded away from zero Implicit conversion shall take place when a net or register is assigned to a real Individual bits that are x or z in the net or the register shall be treated as zero upon conversion See Section 14 for a discussion of system tasks that perform explicit conversion 3.10 Parameters Verilog HDL. .. throughout this standard These examples are informativeÑthey are intended to illustrate the usage of Verilog HDL constructs and PLI functions in a simple context and do not deÞne the full syntax 1.7 Prerequisites Sections 17 through 23 and annexes C through E presuppose a working knowledge of the C programming language 4 Section 1 IEEE Std 1364-1995 Section 2 Lexical conventions This section describes... operands 2.5 Numbers Constant numbers can be speciÞed as integer constants or real constants Section 2 5 IEEE Std 1364-1995 IEEE STANDARD HARDWARE DESCRIPTION LANGUAGE BASED ON number ::= decimal_number | octal_number | binary_number | hex_number | real_number decimal_number ::= [ sign ] unsigned_number | [ size ] decimal _base unsigned_number binary_number ::= [ size ] binary _base binary_digit { _.. .IEEE Std 1364-1995 IEEE STANDARD HARDWARE DESCRIPTION LANGUAGE BASED ON a) To the developers of tools that process the Verilog HDL, the verb ÒshallÓ denotes a requirement that the standard imposes The resulting implementation is required to enforce the requirements and to issue an error if the requirement is not met by the input b) To the Verilog HDL model developer, the verb... including keywords already in use in contexts other than this construct, can be used as a compiler directive name The compiler directives described in Section 16 are part of this standard Additional compiler directives with the `identiÞer construct are not part of this standard Example: `define wordsize 8 12 Section 2 IEEE Std 1364-1995 Section 3 Data types The set of Verilog HDL data types is designed to... $system_function_identifier [ ( list_of_arguments ) ] ; list_of_arguments ::= argument { , [ argument ] } argument ::= expression Syntax 2-2ÑSyntax for system tasks and functions The $identiÞer system task or function can be deÞned in three places: Ñ A standard set of $identiÞer system tasks and functions, as deÞned in Section 14 Section 2 11 IEEE Std 1364-1995 Ñ Ñ Additional $identiÞer system tasks and functions . its attention. iii Introduction (This introduction is not a part of IEEE Std 1364-1995, IEEE Standard Hardware Description Language Based on the Verilog ¨ Hardware Description Language.) . Robinson Ingo RŸsch Chee Kiow Tan Leonard L. Tripp Howard L. Wolfman viii Contents Section 1 Overview 1 Section 2 Lexical conventions 5 Section 3 Data types 13 Section 4 Expressions 27 Section. IEEE Std 1364-1995 Section 2 5 Section 2 Lexical conventions This section describes the lexical tokens used in Verilog HDL source text and their conventions. 2.1 Lexical tokens Verilog