ASP v8 0 midrange family periphral

© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 1201ASP v8.0 January 2007 201ASP Mid-Range Family Peripheral Configuration and Assembly Programming © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 2201ASP Objectives z At the end of this class you will: – Understand the basic PICmicro peripherals and their associated registers – Have “HANDS ON” experience initializing Mid-Range peripherals – Be able to implement peripherals not covered here – Understand interrupts and polling – Write your own application code from “scratch” © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 3201ASP To get the most from this Class z Ideally you should be familiar with the following: – Assembler programming – Basic Mid-Range family Instruction set – Data and Program memory organization – MPLAB Integrated Development Environment – Microchip ICD2 debugger © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 4201ASP 201ASP Agenda z Brief review of Mid-Range Architecture, Instruction Set and Tools z Interrupts on the Mid-Range PICmicro – Interrupts Lab z Peripheral discussion: – Input/Output Ports – Timers z Timer0 z Timer1 – Timer1 Lab z Timer2 – Timer2 Lab © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 5201ASP 201ASP Agenda (cont.) z Capture / Compare / PWM Module (CCP) – PWM and Output Compare Labs z Analog Comparator z Analog to Digital Converters (ADC) – ADC Lab z Addressable Universal Asynchronous & Synchronous Receiver & Transmitter (AUSART) z I 2 C with the Master Synchronous Serial Port – I 2 C Based Temp Sensor Lab z Wrap-Up and additional questions © 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 6201ASP v8.0 January 2007 Mid-Range Family Basic Architecture and Development Tools © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 7201ASP Mid-Range PIC Block Diagram ADC TIMER0 MUX ALU AUSART MSSP PERIPHERALS WORKING REGISTER STATUS REGISTER Pages of Program Memory Banks of Data Memory INSTRUCTION REGISTER 8-bit value from instruction 14-bits PROGRAM COUNTER © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 8201ASP Program Memory z Maximum 8K words – (8K x 14 bits/word)/1 byte = 14Kbytes of memory z Reset Vector at 0000h – Program Counter (PC) will go to this address on reset z Interrupt Vector at 0004h – Program Counter (PC) will go to this address upon any Interrupt Reset Vector Interrupt Vector Page 0 Page 1 Page 2 Page 3 0000h 0004h 0005h 07FFh 0800h 0FFFh 1000h 17FFh 1800h 1FFFh © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 9201ASP Program Counter (PC) and Stack z 13-bit PC – PCLÆ ALU result (8-bits) or OPCODE(11-bits) – PCHÆ Paging bits z Updated from PCLATH z Specifies page in program memory z 8 Level Deep Stack – Stores the contents of the PC z PUSHES – CALL/Interrupt z POPS – RETURN, RETFIE,RETLW PCLATH PCH<12:8> PCL Stack Level 1 Stack Level 8 Program Memory PC<12:0> CALL, RETURN, RETFIE, RETLW © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 10201ASP Data Memory Map 128 Bytes Shared Shared Shared Shared Shared Shared Bank 0 Bank1 Bank2 Bank3 000h 01Fh 020h 07Fh 080h 09Fh 0A0h 0FFh 100h 110h 17Fh 180h 190h 1FFh 0EFh 16Fh 1EFh 10Fh 18Fh Special Function Registers Registers SFR SFR General Purpose Purpose Registers Registers General General Purpose Purpose Registers Registers Special Function Function Registers Registers General General Purpose Registers Registers General Purpose Purpose Registers Registers [...]... INTCON PIR1 PIR2 Bank0 © 200 7 Microchip Technology Incorporated All Rights Reserved 20 1ASP 06 h 07 h 08 h 09 h 0Ah 0Bh 0Ch 0Dh TRISB TRISC TRISD TRISE PCLATH INTCON PIE1 PIE2 86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh Bank1 Slide 11 Status Register IRP RP1 RP0 TO PD Contains: – – – Arithmetic status of the ALU The RESET status Bank select bits for data memory Z RP1 RP1 0 0 1 1 DC C RP0 RP0 0 1 0 1 BANK0 BANK1 BANK2 BANK3... regulator LEDs 16 x 2 LCD Module RS232 Connector Analog Pot 18, 28 and 40pin DIP sockets ICD Connecto r Piezo Buzzer Push button Switches I2C Based Temp Sensor © 200 7 Microchip Technology Incorporated All Rights Reserved 20 1ASP Slide 18 Interrupts © 200 6 Microchip Technology Incorporated All Rights Reserved 20 1ASP v8. 0 January 200 7 Slide 19 Polling and Interrupts Often we would like the processor to... Rights Reserved 20 1ASP RA = 0 RA = 0 Slide 21 Interrupts Reset code goto ;========================= int_vector code 00 4h Interrupt Service Routine (ISR) retfie ;return from ;interrupt ;========================= main_prog no interrupt 00 0h Start Main Main program program execution execution retfie instruction interrupt flag set Execute ISR at Execute ISR at address 00 4h address 00 4h code Start ;start... Start Program Counter Stack INTCON 1 0 0 0 CODE GIE ; initialize INTCON clrf INTCON 1 0 INTE 0 0 1 0 0 INTF Interrupt detected on “RB0/INT” Pin!! ;enable an external ;interrupt on the INT pin bsf INTCON,INTE ;enable global interrupts bsf INTCON,GIE ; sit here and loop forever goto $ © 200 7 Microchip Technology Incorporated All Rights Reserved 20 1ASP Slide 26 Peripheral Interrupts... Development Tools © 200 6 Microchip Technology Incorporated All Rights Reserved 20 1ASP v8. 0 January 200 7 Slide 14 MPLAB® IDE MPLAB® IDE (Integrated Development Environment) Integrates different Microchip and third party tools – – – – – Code Editor Cross Compilers Assemblers Simulators, In-Circuit Debuggers, Emulators Programmers © 200 7 Microchip Technology Incorporated All Rights Reserved 20 1ASP Slide 15 MPLAB®... an event occurs © 200 7 Microchip Technology Incorporated All Rights Reserved 20 1ASP Slide 20 Polling bsf PORTA,1 ;Set bit 1 of ;PORTA btfss INTCON,TMR0IF ;Check Timer0 ;interrupt flag ;in “INTCON” ;register and ;skip the next ;instruction if ;it is set goto $-1 ;Go to ;previous ;instruction bcf PORTA,1 RA = 1 RA = 1 NO TMR0IF = 1 TMR0IF = 1 ?? ?? YES ;Clear bit 0 of ;PORTA © 200 7 Microchip Technology... swapf temp_status,w movwf STATUS ;restore STATUS reg movf temp_w,w ;restore WREG retfie ;return from interrupt © 200 7 Microchip Technology Incorporated All Rights Reserved 20 1ASP Slide 34 Interrupt Hands on Lab © 200 6 Microchip Technology Incorporated All Rights Reserved 20 1ASP v8. 0 January 200 7 Slide 35 Interrupt The objective of this is to: – Learn how to set up and enable an interrupt on the Mid-Range... use any Peripheral Interrupts PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF Flag Bits Flags will set even if interrupts aren’t enabled! © 200 7 Microchip Technology Incorporated All Rights Reserved Description TMR0IF Timer0 Overflow Interrupt Flag INTF RB0/INT External Interrupt Flag RBIF PORTB Change Interrupt Flag 20 1ASP Slide 25 Enabling a Core Interrupt Int_vect CODE 00 4h ;clear external interrupt ;flag... goto $ © 200 7 Microchip Technology Incorporated All Rights Reserved Timer1 Overflow! 20 1ASP TMR1IF Slide 30 Interrupt Latency Interrupt Latency: – – Time from interrupt event to execution of instruction at address 00 04h Synchronous interrupts (typically internal) latency is 3 instruction cycles (Tcy) – Asynchronous interrupts (typically external) latency is 3 – 3.75 instruction cycles © 200 7 Microchip... locations © 200 7 Microchip Technology Incorporated All Rights Reserved 20 1ASP Slide 29 Int_vect CODE Enabling a Peripheral (Timer 1) Interrupt 00 4h banksel PIR1 bcf PIR1, TMR1IF retfie Main Start “goto $” address “goto $” address PIR1 PIR1,TMR1IF PIE1 PIE,TMR1IE bsf bsf Stack INTCON 0 1 1 CODE banksel bcf banksel bsf Program Counter INTCON,PEIE INTCON,GIE GIE PEIE PIE1 1 TMR1IE PIR1 1 0 . Vector at 00 04h – Program Counter (PC) will go to this address upon any Interrupt Reset Vector Interrupt Vector Page 0 Page 1 Page 2 Page 3 00 00h 00 04h 00 05h 07 FFh 08 00h 0FFFh 100 0h 17FFh 1 800 h 1FFFh ©. Bytes Shared Shared Shared Shared Shared Shared Bank 0 Bank1 Bank2 Bank3 00 0h 01 Fh 02 0h 07 Fh 08 0h 09 Fh 0A0h 0FFh 100 h 110h 17Fh 180h 190h 1FFh 0EFh 16Fh 1EFh 10Fh 18Fh Special Function Registers Registers SFR SFR General Purpose Purpose Registers Registers General General Purpose Purpose Registers Registers Special Function Function Registers Registers General General Purpose Registers Registers General Purpose Purpose Registers Registers ©. © 200 6 Microchip Technology Incorporated. All Rights Reserved. Slide 1 20 1ASP v8. 0 January 200 7 20 1ASP Mid-Range Family Peripheral Configuration and Assembly Programming © 200 7 Microchip