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201_ASP v8.0 potx

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© 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 1201ASP v8.0 January 2007 201ASP Mid-Range Family Peripheral Conguration and Assembly Programming © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 2201ASP Objectives  At the end of this class you will: – Understand the basic PICmicro peripherals and their associated registers – Have “HANDS ON” experience initializing Mid-Range peripherals – Be able to implement peripherals not covered here – Understand interrupts and polling – Write your own application code from “scratch” © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 3201ASP To get the most from this Class  Ideally you should be familiar with the following: – Assembler programming – Basic Mid-Range family Instruction set – Data and Program memory organization – MPLAB Integrated Development Environment – Microchip ICD2 debugger © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 4201ASP 201ASP Agenda  Brief review of Mid-Range Architecture, Instruction Set and Tools  Interrupts on the Mid-Range PICmicro – Interrupts Lab  Peripheral discussion: – Input/Output Ports – Timers  Timer0  Timer1 – Timer1 Lab  Timer2 – Timer2 Lab © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 5201ASP 201ASP Agenda (cont.)  Capture / Compare / PWM Module (CCP) – PWM and Output Compare Labs  Analog Comparator  Analog to Digital Converters (ADC) – ADC Lab  Addressable Universal Asynchronous & Synchronous Receiver & Transmitter (AUSART)  I 2 C with the Master Synchronous Serial Port – I 2 C Based Temp Sensor Lab  Wrap-Up and additional questions © 2006 Microchip Technology Incorporated. All Rights Reserved. Slide 6201ASP v8.0 January 2007 Mid-Range Family Basic Architecture and Development Tools © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 7201ASP Mid-Range PIC Block Diagram ADC TIMER0 MUX ALU AUSART MSSP PERIPHERALS WORKING REGISTER STATUS REGISTER Pages of Program Memory Banks of Data Memory INSTRUCTION REGISTER 8-bit value from instruction 14-bits PROGRAM COUNTER © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 8201ASP Program Memory  Maximum 8K words – (8K x 14 bits/word)/1 byte = 14Kbytes of memory  Reset Vector at 0000h – Program Counter (PC) will go to this address on reset  Interrupt Vector at 0004h – Program Counter (PC) will go to this address upon any Interrupt Reset Vector Interrupt Vector Page 0 Page 1 Page 2 Page 3 0000h 0004h 0005h 07FFh 0800h 0FFFh 1000h 17FFh 1800h 1FFFh © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 9201ASP Program Counter (PC) and Stack  13-bit PC – PCL ALU result (8-bits) or OPCODE(11-bits) – PCH Paging bits  Updated from PCLATH  Specifies page in program memory  8 Level Deep Stack – Stores the contents of the PC  PUSHES – CALL/Interrupt  POPS – RETURN, RETFIE,RETLW PCLATH PCH<12:8> PCL Stack Level 1 Stack Level 8 Program Memory PC<12:0> CALL, RETURN, RETFIE, RETLW © 2007 Microchip Technology Incorporated. All Rights Reserved. Slide 10201ASP Data Memory Map 128 Bytes Shared Shared Shared Shared Shared Shared Bank 0 Bank1 Bank2 Bank3 000h 01Fh 020h 07Fh 080h 09Fh 0A0h 0FFh 100h 110h 17Fh 180h 190h 1FFh 0EFh 16Fh 1EFh 10Fh 18Fh Special Function Registers Registers SFR SFR General Purpose Purpose Registers Registers General General Purpose Purpose Registers Registers Special Function Function Registers Registers General General Purpose Registers Registers General Purpose Purpose Registers Registers [...]... Return from Subroutine Go into standby mode Subtract W from literal k k Exclusive OR literal with W Slide 13 PICmicro Development Tools © 2006 Microchip Technology Incorporated All Rights Reserved 201ASP v8.0 January 2007 Slide 14 MPLAB® IDE   MPLAB® IDE (Integrated Development Environment) Integrates different Microchip and third party tools – – – – – Code Editor Cross Compilers Assemblers Simulators,... Buzzer Push button Switches I2C Based Temp Sensor © 2007 Microchip Technology Incorporated All Rights Reserved 201ASP Slide 18 Interrupts © 2006 Microchip Technology Incorporated All Rights Reserved 201ASP v8.0 January 2007 Slide 19 Polling and Interrupts  Often we would like the processor to perform a task if a specific event occurs  Two methods to check if this event has occurred: – Polling:  – Continuously... WREG retfie ;return from interrupt © 2007 Microchip Technology Incorporated All Rights Reserved 201ASP Slide 34 Interrupt Hands on Lab © 2006 Microchip Technology Incorporated All Rights Reserved 201ASP v8.0 January 2007 Slide 35 Interrupt  The objective of this is to: – Learn how to set up and enable an interrupt on the Mid-Range PIC – Become more familiar with the MPLAB IDE, the PICdem2 Plus and the . at 00 04h – Program Counter (PC) will go to this address upon any Interrupt Reset Vector Interrupt Vector Page 0 Page 1 Page 2 Page 3 00 00h 00 04h 00 05h 07 FFh 08 00h 0FFFh 100 0h 17FFh 1 800 h 1FFFh ©. Bytes Shared Shared Shared Shared Shared Shared Bank 0 Bank1 Bank2 Bank3 00 0h 01 Fh 02 0h 07 Fh 08 0h 09 Fh 0A0h 0FFh 100 h 110h 17Fh 180h 190h 1FFh 0EFh 16Fh 1EFh 10Fh 18Fh Special Function Registers Registers SFR SFR General Purpose Purpose Registers Registers General General Purpose Purpose Registers Registers Special Function Function Registers Registers General General Purpose Registers Registers General Purpose Purpose Registers Registers ©. Sensor © 200 6 Microchip Technology Incorporated. All Rights Reserved. Slide 19 20 1ASP v8. 0 January 200 7 Interrupts © 200 7 Microchip Technology Incorporated. All Rights Reserved. Slide 202 0 1ASP  Often

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Mục lục

    201ASP Mid-Range Family Peripheral Configuration and Assembly Programming

    To get the most from this Class

    Mid-Range Family Basic Architecture and Development Tools

    Mid-Range PIC Block Diagram

    Program Counter (PC) and Stack

    Special Function Registers (SFRs)

    ICD 2 (In Circuit Debugger)

    INTCON Register (Core Interrupts)

    Enabling a Core Interrupt

    PIE1 and PIR1 Registers*

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