Programing manual

Programing manual MELSEC A/Q series Programmable Logic Controllers Programming Manual Art No 87431 06 10 2004 Version D MITSUBISHI ELECTRIC MITSUBISHI ELECTRIC INDUSTRIAL AUTOMATION Programming Manual[.]

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MELSEC A/Q series

Programmable Logic ControllersProgramming Manual

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Programming Manual for the

MELSEC A and Q series and the MELSEC System QOrder-No.: 87431

RevisionChanges / Additions / Correktions

A 09/1998 pdp Programming manual for the MELSEC A and Q series based on Melsec Medoc plus

B 04/2001 pdp Ch 5.1.2: Changed bitmap (ladder diagram in GX IEC Developer) for the

ORP instruction

Changed bitmap for the LDP instructionCh 7.6.3: Note for the usage of the CALL instruction

Ch 7.14: Addition of the RSET_K_MD and RSET_K_P_MD instruction

Ch 7.11.13: Note for the usage of the ASC(P) instruction

Additional information for System Q CPUs (Q02, Q02H, Q06H,Q12H and Q25H).

C 08/2002 pdp-dk Additional information for Q00JCPU, Q00CPU and Q01CPU of the System Q.Q25H).

New instructions S.TO and FROM for use in a multi-CPU-System.

In chapter 9 now the representation format of the instruction in the GX IEC Developeris shown.

Additonal special relays and registers for System Q CPUs with function Version B orlater.

Separate tables for processing times for A series and Q series/System Q.Addition of an example in Ch 7.6.10, showing the program modification.Corrections:

Ch 6.5.1: Operating errors

Ch 6.7.3: Additional information for the COM instruction when used in amulti-CPU system

Ch 6.8.9: Time values for n1

Ch 7.1.1: Devices MELSEC Q

Ch 9.5.1: Processing times for the RBMOV and the BMOV instruction

D 09/2004 pdp-dk New chapter 10: Instructions for Q4ARCPU

New chapter 11: Dedicated instructions for intelligent function modulesCh 2.8: Summary of the instructions for Q4ARCPU

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About this Manual

The texts, illustrations, diagrams, and examples contained in this manual are intended exclusively as support material for the explanation, handling, programming, and operation of the programmable logic controllers of the

MELSEC A and Q series and the MELSEC System Q.

If you have any questions concerning the programming and operation of the equipment described in this manual, please contact your relevant sales office or

department (refer to back of cover).

Current information and answers to frequently asked questions are also available through the Internet (www.mitsubishi-automation.com)

MITSUBISHI ELECTRIC EUROPE B.V reserves the right for technicalchanges and changes to this manual at any time without prior notice.

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ContentsContents1Introduction1.1 Further manuals 1-11.2 CPU types 1-21.3 Software .1-21.4 Finding an instruction 1-31.5 PLC parameters 1-3

1.6 Comparison between GX IEC Developer and

GX Developer 1-4

2Instruction Tables

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Contents

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Contents

2.9 Instructions for special function modules 2-662.9.1 Instructions for serial communication modules 2-662.9.2 Instructions for PROFIBUS/DP interface modules 2-672.9.3 Instructions for ETHERNET interface modules 2-682.9.4 Instruction for MELSECNET/10 2-682.9.5 Instructions for CC-Link 2-69

3Configuration of Instructions

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Contents

3.9 Execution conditions of the instructions 3-343.9.1 Execution condition 3-343.9.2 EN input and ENO output 3-353.10 Number of program steps 3-373.10.1 For a System Q and QnA CPU 3-373.10.2 For an AnA, AnAS, and AnU CPU 3-38

4Layout and Structure of the Chapters

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Contents

6Application Instructions, Part 1

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Contents

6.4 Data transfer instructions 6-117

6.4.1 6-117

6.4.2 MOV, MOVP, DMOV, DMOVP .6-1186.4.3 EMOV, EMOVP 6-1216.4.4 $MOV, $MOVP 6-1246.4.5 CML, CMLP, DCML, DCMLP 6-1276.4.6 BMOV, BMOVP 6-1326.4.7 FMOV, FMOVP 6-1356.4.8 XCH, XCHP, DXCH, DXCHP 6-1386.4.9 BXCH, BXCHP 6-1416.4.10 SWAP, SWAPP 6-1446.5 Program Branch Instructions 6-1476.5.1 CJ, SCJ, JMP 6-1486.5.2 GOEND 6-1536.6 Program Execution Control Instructions .6-155

6.6.1 6-155

6.6.2 DI, EI, IMASK 6-1566.6.3 IRET 6-1636.7 Link Refresh Instructions 6-165

6.7.1 6-165

6.7.2 RFS, RFSP 6-1666.7.3 SEG 6-1686.7.4 COM 6-1726.7.5 EI, DI 6-1756.8 Other convenient Instructions 6-178

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Contents

7Application Instructions, Part 2

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Contents

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Contents

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Contents

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Contents

8Data Link Instructions

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Contents

9Instructions for System Q CPUs

9.1 Reading Module Information 9-29.1.1 UNIRD, UNIRDP 9-29.2 Debugging and failure diagnosis instructions 9-79.2.1 TRACE, TRACER 9-79.3 Writing to and reading from files 9-99.3.1 FWRITE 9-99.3.2 FREAD 9-209.4 Program instructions 9-339.4.1 PLOADP 9-339.4.2 PUNLOADP 9-369.4.3 PSWAPP 9-389.5 Data transfer insructions 9-419.5.1 RBMOV, RBMOVP 9-419.6 Instructions for use in a Multi-CPU System 9-469.6.1 S.TO, SP.TO 9-469.6.2 FROM, FROMP 9-49

10Instructions for Q4ARCPU

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Contents

11Instructions for Special Function Modules

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Contents

12Microcomputer Mode (AnN(S))

12.1 Storage capacities and memory areas 12-112.2 Applying user-created microcomputer programs 12-212.2.1 Memory map 12-312.2.2 Address configuration of the data storage area 12-312.2.3 Configuration of data memory area 12-4

13Error Codes

13.1 Table of error codes; Q00J, Q00 and Q01CPU 13-213.2 Table of Error Codes; QnA CPUs and System Q 13-1213.3 Table of error codes; A series (except AnA and AnAS) 13-3913.4 Table of error codes; AnA and AnAS CPUs 13-43

A Appendix A

A.1 Definition of the Processing Times A-1A.2 Processing times A-2A.2.1 Table of Processing Times (QnA series and System Q) A-3A.2.2 Processing times of the A series CPUs A-23A.3 Comparison of the CPUs A-32A.3.1 Available devices A-32A.3.2 I/O control modes A-34A.3.3 Data types A-34A.3.4 Timer-Vergleich A-35A.3.5 Comparision of counters A-38A.3.6 Comparison of display instructions A-39A.3.7 Q series and System Q instructions equivalent to A series

instructions A-40

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Contents

A.5 Table of Special Registers A-73A.5.1 Table of special registers (Q series and System Q) A-73A.5.2 Table of special registers (D) (A series only) A-110A.5.3 Table of link registers (A series only) A-120

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Introduction Further manuals

1Introduction

This manual describes the programming and processing of the sequence and applicationinstructions that are provided by the CPUs of the MELSEC A and Q series.

1.1Further manuals

QCPU/QnACPU Programming Manual (PID Instructions)- Description of the PID control instructions

QnPHCPU Programming Manual (Process Control Instructions)- Description of the PID control instructions

Programming Manual (AD57/58)

- Description of specific instructions for the special function modules AD57/58QCPU/QnACPU Programming Manual (SFC)

- Description of the instructions for sequential function chartsGX Developer Operation Manuals

- Fundamentals of programming in GX Developer

GX IEC DeveloperBeginner’s Manual

- Fundamentals of programming in GX IEC Developer

GX IEC DeveloperReference Manual

- Detailed description of programming in GX IEC Developer- Description of the IEC instructions (IEC standard library)

NOTE All manuals are listed in our current PLC price list.

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CPU types Introduction

1.2CPU types

The functions described in this manual can be transferred to all CPU types by the current ver-sions of the GX Developer and the GX IEC Developer provided that the according CPU sup-ports the instructions.

The different PLC types with their specific CPU are listed below in detail:

If, e.g in tables, A and Q is mentioned, all CPU types of the A series and the Q series/System Q are included Exceptions are marked separately.

1.3Software

All the described instructions, with few exceptions, can be applied with the available softwarepackages:

- GX Developer- GX IEC Developer

The program examples contained in this manual were created with the GX IEC Developer Therepresentation of the MELSEC Instruction List (IL) generally corresponds to that of the GXDeveloper.

All the instructions described in this manual are included within the standard library of the GXIEC Developer.

Corresponding to the selected CPU only those instructions are available within the GX IEC

PLC TypeCPU Type

A Series

AnA/AnU A2A, A2A-S1, A2U, A2U-S1,

A3A, A3U

AnAS/AnUS A2AS, A2AS-S1, A2AS-S30, A2AS-S60, A2US, A2US-S1

AnN A1, A2, A2C

A3M, A3N

AnS A1S, A1S-S1, A2S, A2S-S1

Q Series QnAQ2A/Q2AS, Q2A-S1/Q2AS-SQ3AQ4A, Q4ARSystem QQ(single processor types)Q00JQ (multi processor types)

Q00, Q01 (restricted use in a multi-CPU System) Q02, Q02H, Q06H, Q12H, Q12PH, Q25H, Q25PHPC-CPU-Module: PPC-CPU686(MS)-64

PPC-CPU686(MS)-128

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Introduction Finding an instruction

1.4Finding an instruction

Advanced

If you are already familiar with the programming of instructions for the MELSEC A and Q seriesas well as the System Q, look up the instruction chapters 5 through 9 The header line containsthe name of the instruction as it is applied within GX Developer and the MELSEC editor of theGX IEC Developer.

Beginners

If you are not really familiar with the handling of the instructions, proceed as follows:

● Read through chapter 3 regarding the differing representation of instructions within theMELSEC and the IEC editor.

● Read through chapter 4 regarding the consistent layout and structure of each descriptionof instruction.

● Use

- the tabular overview of instruction categories with brief descriptions in chapter 2- the index containing the entire instructions

NOTE All the instructions contained in this manual are also included within the online help of the GXIEC Developeras detailed as here.

1.5PLC parameters

Via parameters several functions, device ranges, etc are set up For the programming of thefunctions described in this manual, the parameter settings can remain preset or customised tothe user´s needs Refer to the according hardware manuals of the CPUs and programmingmanuals for detailed descriptions of the PLC parameter settings.

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Comparison between GX IEC Developer and GX Developer IntroductionExample: GX Developer, GX IEC Developer 6.0

1.6Comparison between GX IEC Developer and GX Developer

The most important features of the GX IEC Developer and the GX Developer are listed in thefollowing table:

GX IEC DeveloperGX Developer

Structured use Simple to use

Programming in comply with IEC 1131 —

Editiors: Instruction List, Ladder Diagram, Structured Text, SFC, FUB

Editiors: Instruction List, Ladder Diagram, SFC

Functions und Funktion Blocks Funktion Blocks (V 7.0 or later)

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Instruction Tables Subdivision of instructions

2Instruction Tables

2.1Subdivision of instructions

The instructions are subdivided into four major categories:● Sequence instructions

● Application instructions, Part 1● Application instructions, Part 2● Data link instructions

The categories of instructions are described more detailed in the following table:

Category of InstructionDescriptionReference

Sequence instructions

Input instructionOperation start,

series and parallel connection of contacts. Ch 5.1

Connection instructionSeries and parallel block connection,

storage and processing of operation results,inversion of operation results,

conversion of operation results into pulses,setting of edge relays.

Ch 5.2

Output instructionBit devices, counter and timer contacts,

output, setting, and resetting of annunciators,setting and resetting of devices,

leading edge and trailing edge output,bit device output inversion,

generating pulses.

Ch 5.3

Shift instructionShifting bit devices.Ch 5.4

Master control instruction

Setting and resetting single parts of a program.Ch 5.5

Termination instructionEnd of a part of program,

end of sequence and routine programs.

Ch 5.6

Miscellaneous instructions

Sequence program stop,no operation.Ch 5.7ApplicationinstructionsComparison operation instruction

Compares data to data (e.g =, >, ≥)Ch 6.1

Arithmetic operation instruction

Adds, subtracts, multiplies, divides, increments, and decrements BIN and BCD data, floating point data, and BIN block data, links character strings

Ch 6.2

Data conversion instruction

Converts data types, e.g.

BCD → BIN, BIN → BCD Ch 6.3

Data transfer instruction

Transmits designated dataCh 6.4

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Subdivision of instructions Instruction TablesApplicationinstructionsPart 2Logical operation instructions

Logical AND / OR, logical exclusive OR / exclusive NORCh 7.1

Rotation instructions16-bit and 32-bit data right / left rotationCh 7.2

Shift instructionsShift data by bit or wordCh 7.3

Bit processing instructions

Set, reset, and test bitsCh 7.4

Data processing instructions

Search, encode, and decode data at specified devices Disunite and unite data

Ch 7.5

Structured program instructions

Repeated operation, subroutine program calls, subroutine calls between program files, switching between main and subprogram parts, micro computer program calls, index qualification of entire ladders, store index qualification values in data tables

Ch 7.6

Data table operation instructions

Write to and read data from a data table, delete and insert data blocks in a data table

Ch 7.7

Buffer memory access instructions

Buffer memory access of special function modules or remote modules

Ch 7.8

Display instructionsOutput ASCII characters to the outputs of a module or to

an LED display

Ch 7.9

Debugging and failure diagnosis instructions

Failure checks, setting and resetting status latch, sampling trace, program trace

Ch 7.10

Character string processing instructions

Character string (ASCII code) processingCh 7.11

Special function instructions

Trigonometrical functions, square root and exponential calculation with BCD data and floating point data

Ch 7.12

Data control instructions

Upper and lower limit control and storage of checked data

Ch 7.13

File register switching instructions

Switching between file register blocks and filesCh 7.14

Clock instructionsWriting and reading clock dataCh 7.15

Peripheral device instructions

Message output and key input on peripheral unitsCh 7.16

Program instructionsSelect different program execution modesCh 7.17

Other instructionsReset watchdog timer (WDT), set and reset carry, pulse

generation, direct read from indirect access file registers, numerical key input from keyboard, batch save or recovery of index registers, write to EEPROM file registersCh 7.18Data link instructionsNetwork refresh instructions

Instructions for data refresh operations in network modules.

Ch 8.5

Dedicated data link instructions

Read and write data from and to object stations in object networks, Send data to network modules in object stations in object networks, Read data sent via SEND instruction, Data requests to different stations (write/read operations with clock data, RUN/STOP operations),Read and write data from and to special function modules in remote I/O stations.

Ch 8.6

A series compautible data link instructions

Read and write data from and to object stations in different networks, Read and write data from and to local stations (at master stations only), Read and write data

Ch 8.7

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Instruction Tables Subdivision of instructionsInstructions for a CPU of the System QReading module information

Reads module information from the designated head I/O number

Ch 9.1

Trace set/Trace resetStores trace data in the trace file in a memory cardCh 9.2

Writing to and reading from files

Writes data to the designated file.Reads data from the designated file

Ch 9.3

Programm instructionsLoad, unload, load + unload program from memory cardCh 9.4

Data transferHigh-speed block transfer of file registerCh 9.5

Data excange in a multi-CPU system

Writing to the CPU shared memory

Reading from the CPU shared memory of another CPU

Ch 9.6

Instructions for a Q4ARCPU

Mode settingsOperation mode setting for CPU start up and for

switching from the control system to the standby system

Ch 10.1

Data transferTransfer of data from the control system CPU to the

CPU of the standby system

Batch transfer of data to and from the buffer memory of special function modules

Ch 10.2

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Overview of instructions Instruction Tables

2.2Overview of instructions

2.2.1Description of the overview tables

The following sections 2.3 through 2.6 include an overview of all instructions described in thismanual.

In the following the layout of the overview table is described in detail:

(1) (2) (3) (4) (5) (6) (7) (8)

Explanation of the different columns:(1) Category of instruction

(2) Specification of instruction name ("command") for the programming

The instruction names are represented in MELSEC notation (refer to section 3.2 for expla-nation of the notation).

In general, 16-bit instructions are represented All 32-bit instructions are indicated by aleading "D".

Example:- 16-bit instruction: +- 32-bit instruction: D+

Pulse instructions, i.e instructions that are only executed at leading edge of a signal areindicated by an appended "P".

Example:- Execution when ON: +- Execution at leading edge: +P

CategoryInstructionVariablesMeaningExecution ConditionNumber of stepsReference

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Instruction Tables Overview of instructions

Instructions, processing character strings are indicated by a leading "$"

Example:- standard instructions: +

- character string instruction:+P(3) Specification of variables

Here, the variables to be used are specified The data source is represented by an "s", thedata destination is represented by a "d".

Example: s = if there is only one data sources1, s2 = if there are several data sourcess+0, s+1, (s1)+0, (s1)+1 = for 32-bit instructionse.g s1 = data register D0, (s1)+1 = data register D1s+0, s+1, s+2, s+3 = 4 successive devices, e.g for an array(4) Meaning and processing of the entire control instruction

(5) Indication of the execution condition according to the following table

(6+7) Indication of the number of program steps

Indicated is the number of steps that are required for the entire execution of the instruction.

SymbolExecution condition

no indication The instruction is executed continuously and independent from the prior execution

condition If the precondition is not set, the instruction is not executed.

The instruction is executed as long as the precondition is ON If the precondition is OFF, the instruction is not executed and no processing is conducted.

This instruction is a pulsed instruction It is only executed once and at leading edge of the input signal (e.g if the precondition alters from OFF to ON) Afterwards, the instruction will not be executed any longer even if the input signal is still ON.This instruction is a pulsed instruction as well It is only executed once and at trailing edge of the input signal (e.g if the precondition alters from OFF to ON) Afterwards, the instruction will not be executed any longer even if the input signal is still ON.

(d) + (s) → (d)Indicates16 bitsIndicates32 bits(d+1,d) + (s+1, s) → (d+1, d)16 bits16 bits

upper 16 bitslower 16 bits

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Sequence instructions Instruction Tables

2.3Sequence instructions

2.3.1Input instructions

CategoryInstructionVariablesMeaningExecution Condition

Number of stepsReference

QA

Inputinstruction

LDOperation start

(Load (normally open contact))

*

1 1 5.1.1

LDIOperation start

(Load (normally closed contact))

ANDSeries connection

(of NO contacts)

ANISeries connection

(of NC contacts)

ORParallel connection

(of NO contacts)

ORIParallel connection

(of NC contacts)

LDPPulse operation start

(leading edge)

*1

2

5.1.2

LDFPulse operation start

(trailing edge)

ANDPsPulse series

connection(leading edge)

ANDFsPulse series

connection (trailing edge)

ORPsPulse parallel

connection(leading edge)

ORFsPulse parallel

connection(trailing edge)

*: The number of program steps depends on the devices used.

• For the use of internal devices or file registers (R0 through R32767) : 1

• For the use of a direct access input (DX) : 2

• For the use of other devices : 3

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Instruction Tables Sequence instructions

2.3.2Connection instructions

CategoryInstruc-tionVariablesMeaningExecution ConditionNumber of stepsReference

QA

Connectioninstruction

ANB—Block series connection

(Ladder block series connection)

115.2.1

ORBBlock parallel connection

(Ladder block parallel connection)

MPS—Operation result

processing

(Store operation result (memory push))

115.2.2

MRDOperation result

processing

(Read operation result (memory read))

MPPOperation result

processing

(Read and clear operation result (memory pop))

INV—Operation result inversion

(Inversion instruction) 1 5.2.3

MEP—Operation result into

pulse conversion(Pulse generation at leading edge of operation result)

15.2.4

MEFOperation result into

pulse conversion(Pulse generation at trailing edge of operation result)

EGPdSetting of edge relays

(Setting an edge relay with leading edge of an operation result)

15.2.5

EGFSetting of edge relays

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Sequence instructions Instruction Tables

2.3.3Output instruction

2.3.4Shift instructions

QA

Outputinstruction

OUTdSetting instructions for

outputs

*1

*

1 5.3.1

SETdSetting of devices** *

1 5.3.5RSTdResetting devices**2 *1 5.3.6PLSd

Output at leading edge

2 *

3 5.3.8

PLFOutput at trailing edge

FFsInversion of bit output

device 2 5.3.9

DELTA

d

Generating pulses at direct access outputs

25.3.11

DELTAP

*: The number of program steps depends on the devices used.Refer to the reference chapter for the accurate number of steps.

**: This execution condition is only applied, if the annunciator (F) is used.

QA

Verschiebe-anweisungen

SFT

dShifting bit devices2 3* 5.4.1

SFTP

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Instruction Tables Sequence instructions

2.3.5Master control instructions

2.3.6Program termination instructions

2.3.7Miscellaneous instructions

QAMastercontrolinstructionMCn, dActivating indicated program parts 2 *3/5 5.5.1MCRnDeactivating indicated program parts 1

*: The according number of steps is 5 for all MC instructions and 3 for the MCR instruction.

Refer to chapter 3.9.2 "For an AnA, AnAS, and AnU CPU“ for the according number of steps.

QATermination instructionFEND—End of program branches15.6.1

ENDEnd of sequence

program 5.6.2

QA

Sonstige Anweisungen

STOP—Stop instruction

1

5.7.1

NOP—No operation

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Application instructions, Part 1 Instruction Tables

2.4Application instructions, Part 1

2.4.1Comparison operation instructions

QA

BIN 16-bit data comparison

LD=s1, s2Sets the output, if

s1 = s2

3 5/7* 6.1.1

AND=OR=

LD<>s1, s2Sets the output, if

s1 ≠ s2

3 5/7* 6.1.1

AND<>OR<>

LD>s1, s2Sets the output, if

s1 > s2

3 5/7* 6.1.1

AND>OR>

LD<=s1, s2Sets the output, if

s1 <= s2

3 5/7* 6.1.1

AND<=OR<=

LD<s1, s2Sets the output, if

s1 < s2

3 5/7* 6.1.1

AND<OR<

LD>=s1, s2Sets the output, if

s1 >= s2

3 5/7* 6.1.1

AND>=OR>=

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Instruction Tables Application instructions, Part 1

QA

BIN 32-bit data comparison

LDD=

s1, s2 Sets the output, if

s1 = s2*3**11 6.1.2ANDD=ORD=LDD<>

s1 ≠ s23***11 6.1.2ANDD<>ORD<>LDD>

s1, s2 Sets the output, ifs1 > s2 3* 11** 6.1.2

ANDD>ORD>LDD<=

s1 <= s2*3**11 6.1.2ANDD<=ORD<=LDD<

s1, s2 Sets the output, ifs1 < s2 3* 11** 6.1.2

ANDD<ORD<LDD>=

s1 >= s2*3**11 6.1.2ANDD>=ORD>=

*: The number of program steps depends on the devices used and the type of CPU.

• If a QnA CPU or a single processor CPU of the System Q is used: 3

• If a System Q multi processor CPU is used withinternal word devices (except for file register ZR): 5constants: 5

Bit Devices, whose device numbers are multiplies of 16,

whose digit designation is K8, and which use no index qualification: 5

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Application instructions, Part 1 Instruction Tables

QA

Floating point data comparison

LDE=

s1 = s2 3 6.1.3

ANDE=ORE=LDE<>

s1 ≠ s2 3 6.1.3

ANDE<>ORE<>LDE>

s1 > s2 3 6.1.3

ANDE>ORE>LDE<=

s1 <= s2 3 6.1.3

ANDE<=ORE<=LDE<

s1 < s2 3 6.1.3

ANDE<ORE<LDE>=

s1 >= s2 3 6.1.3

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