Synopsys MIPI VIP Next-Generation Discovery VIP for Faster SOC Verification May 2012 Yuanpeng Su © Synopsys 2012 Industry Driving Strong Demand for VIP Explosion in number of protocols • • Rapidly Increasing # of protocols on SoCs Highly optimized for end-user applications – – – • PCIe, USB 3.0, Ethernet 100G, SDIO, SATA6G MIPI Protocols (CSI, DSI, LLI, DigRF, UniPro ) New versions; new protocols VIP is a key part of the verification solution SDIO I2C PCI AMBA AHB UART USB2.0 AMBA APB MMC-SD 10x Protocols AMBA4 AXI HDMI USB OTG I2C SATA HDMI AMBA4 ACE MIPI DSI UART PCIe USB2.0 HDMI USB3.0 SDIO MMC-SD MIPI CSI SLIM Bus MIPI LLI GPIO MIPI HSI © Synopsys 2012 2001 2012 Increasing mobile display resolutions Challenges with Traditional VIP Current VIP technology running out of steam OVM VMM UVM OVM UVM Configuration & Test Development • Test Planning • Scenario Development SV Interface eRM SV Interface ‘e’ • Weeks before first test Debug • Days to find root cause, due to limited visibility • Current debug tools not protocol-aware C ‘e’ and C based VIP VMM OVM UVM SV Interface Vera Vera based VIP © Synopsys 2012 Performance Coverage Closure • Multiple wrappers create performance bottleneck • 2+ man-months to create coverage plan per title • Many VIPs = 3M+ lines of VIP code per SOC • 3+ man-months to implement coverage and scenarios Introducing Synopsys Discovery VIP © Synopsys 2012 Introducing Synopsys Discovery VIP VIPER Architecture • 100% SystemVerilog – – – • Direct methodology support – • No wrappers, No adapters What you get is what you know – © Synopsys 2012 Best performance Simulator portability Ease of integration Equal support for UVM, VMM, OVM Rapid Configuration and Planning 10x Faster Configuration All VIP options in one place Pull-downs show all Possible values 10X faster configuration Validity Check • Protocol Aware, Knowledge-based GUI Configuration • In-line protocol help Test plans eliminate weeks of coverage development • Auto-generated to match configuration Test Plans Sequence libraries save weeks of development time • Save weeks learning the protocol • Saves time developing tests Top-level Plans for all interfaces © Synopsys 2012 Synopsys Confidential Coverage bins Higher Performance with Native Simulation Faster Performance with SystemVerilog VIP Single kernel, No PLI solution VIP with PLI vs without PLI • Runs natively in all SystemVerilog simulator • Code size reduced by up to 20% by eliminating wrappers Up to 4X Faster Performance Synopsys (2-4X) Eliminates inefficiency of methodology mapping • Wrappers turn a single object into many call/tasks to map to underlying VIP Protocol-aware optimizations • Optimized VIP code • VCS Optimizations © Synopsys 2012 Several VIP configurations on Consumer SOC Protocol Aware Debug Environment Simulator Independent Protocol Analyzer Simplified viewing of protocol activity • Visually unravels complex protocol behavior • Quickly highlights bottlenecks or inactivity Immediate error identification • Spotlights errors on protocol-centric view • Provides on-demand detailed information Accelerated root-cause analysis • Highlights relationships across protocol hierarchy of transfers, packets, handshaking • Link to DVE and Verdi provides signal-level debug related to each transaction © Synopsys 2012 Synopsys Confidential Protocol Analyzer Link to Signal View Integrated with DVE and Verdi for signal-level debug Cross Highlighting • Autoload all protocol signals in waveform view • Highlight start and end of transactions with cursors • Synchronizes scrolling in time-domain © Synopsys 2012 Built-in Protocol Coverage Specification to plan to closure Protocol Specification • Protocol specification mapped to verification plan and functional coverage groups – – – • Built-in protocol cover points – – – • Protocol Verification Sub-Plan Hierarchical sub-plans Eases identification of low coverage protocol features Includes additional coverage based on Synopsys expertise in developing design IP Includes sequential cover-points from Synopsys experts Configuration aware User-extendable for custom applications Highlights coverage holes – Results back-annotated onto built-in verification plan Functional Coverage Group in VIP Back Annotated Coverage from Simulation © Synopsys 2012 10 Synopsys Verification IP Portfolio Synopsys VIP Portfolio AMBA (AXI, ACE) MIPI CSI AMBA (AXI, APB) MIPI DSI AMBA (AHB, APB) MIPI DigRF v4 USB 3.0 MIPI HSI USB (2.0, 1.1, OTG) PCI Express (Gen3/2/1) HDMI 1.4 NVM Express Ethernet 10G/40G/100G) PCI/PCI-X (2.0, 1.1) Interlaken SATA (1.5, 3.0 & 6Gbps) I2S SAS Serial I/O (RS232, GPIO) ATAPI OCP (2.2, 2.1, 2.0) I2C SDIO UART © Synopsys 2012 11 Mobile Applications CSI DSI Coming soon MIPI M-PHY, LLI, and more Synopsys VIP for Verification of ARM AMBA AXI and ACE protocols • Protocol Support – • Includes – – – – – – • 12 Configuration Tool Verification Plan Built-in Coverage Protocol Analyzer UVM, OVM, VMM and Verilog – © Synopsys 2012 Programmable number of Masters, Slaves, and Port Monitors Interconnect model System Monitor Sequencers Sequence Library System Configuration Object Features – – – – • AXI3, AXI4 and ACE protocols Runs natively for optimum performance Synopsys Discovery VIP for MIPI Next Generation VIPER Architecture • CSI-2 – – • DSI – – • Supports DSI spec 1.01.00 D-PHY spec 1.00.00 DigRFv4 – – • • • 2.0 spec 1.00 D-PHY spec 1.00.00 DigRFv4 spec 1.00 M-PHY spec 1.4 Support for UVM, VMM and Verilog Integrated with Discovery Protocol Analyzer Other MIPI protocols coming soon © Synopsys 2012 13 CSI-2 Discovery Verification IP Comprehensive CSI-2 Verification • • • • CSI-2 Transmitter and Receiver Built-in Protocol Checks Built in Verification Plan and Coverage Protocol Layer – – – – – – • Four virtual channels All types of packets (short and long) Interleaved and normal frames Operative/Inoperative line and frame number ECC generation, CRC generation and checking Error detection and recording Physical Layer – – – High Speed, Ultra Low Power, Escape Mode High Speed Synchonization One to four PHY data lanes © Synopsys 2012 14 CSI-2 Flow Serial Functional Coverage Phase Control Generator(s) VIP CSI-2 Protocol + Physical Serial CSI-2 Flow Parallel Functional Coverage Phase Control Generator(s) VIP CSI-2 Protocol PPI D-PHY Serial DSI Discovery Verification IP Comprehensive DSI Verification • • • • DSI Transmitter and Receiver Built-in Protocol Checks Built-in Verification Plan and Coverage Protocol Layer – – – – – – • Four virtual channels DCS command, Generic command and Video All packet structures 16BPP, 18BPP & 24 BPP RGB pixel formats ECC generation, CRC generation and checking Error detection and recording Physical Layer – – – One to four PHY data lanes High-speed, Low Power and Escape transmission modes Contention detection and recovery © Synopsys 2012 15 DSI Flow Serial Functional Coverage Phase Control Generator(s) VIP DSI Protocol + Physical Serial DSI Flow Parallel Functional Coverage Phase Control Generator(s) VIP DSI Protocol PPI D-PHY Serial DigRFv4 Verification IP Comprehensive DigRF Verification • • • Built-in Protocol Checks Built-in Verification Plan and Coverage Protocol Layer – – – – • Configurable high-speed, low-speed and standby modes (sleep, stall, hibernate) ICLC messages, nested frames, dummy frames, idle symbols, & marker symbols Link test modes CRC generation, Error detection and Re-transmission Physical Layer – – M-PHY serial and parallel RMMI interfaces Supports capability, status and configuration attributes © Synopsys 2012 16 DigRF Flow Serial Functional Coverage Phase Control Generator(s) VIP DigRF Protocol + Physical Serial DigRF Flow Parallel Functional Coverage Phase Control Generator(s) VIP DSI Protocol M-PHY RMM I Serial MIPI Debug: Protocol Analyzer Integrated Docs MIPI DSI Video MIPI DSI Command Transcript of messages, errors, warnings at time of transaction © Synopsys 2012 17 selected HS Long data lane States detailed packet info Discovery MIPI VIP Deliverables • Subenv including VIP – – – • • • • • Stimulus Generator Sequence Library HTML documentation Verification Plan QuickStart Examples – • Transmitter Receiver Monitors Including scoreboard Integration with Protocol Analyzer © Synopsys 2012 18 Discovery™ Verification IP • Next-generation architecture • 100% SystemVerilog • Native UVM, VMM, and OVM • Built-in Test Plans & Coverage • Up to 4x faster • Protocol-aware debug • Supports all major simulators VIPER Architecture © Synopsys 2012 19 Resources www.synopsys.com/vip More VIP © Synopsys 2012 20 Thank You © Synopsys 2012 21 ... title • Many VIPs = 3M+ lines of VIP code per SOC • 3+ man-months to implement coverage and scenarios Introducing Synopsys Discovery VIP © Synopsys 2012 Introducing Synopsys Discovery VIP VIPER Architecture... USB2.0 HDMI USB3.0 SDIO MMC-SD MIPI CSI SLIM Bus MIPI LLI GPIO MIPI HSI © Synopsys 2012 2001 2012 Increasing mobile display resolutions Challenges with Traditional VIP Current VIP technology running... in VIP Back Annotated Coverage from Simulation © Synopsys 2012 10 Synopsys Verification IP Portfolio Synopsys VIP Portfolio AMBA (AXI, ACE) MIPI CSI AMBA (AXI, APB) MIPI DSI AMBA (AHB, APB) MIPI