QFile Certificate Program on System Verilog and UVM

QUALIFICATION FILE: Certificate Program on System Verilog and UVM (Level 7) NSDA REFERENCE To be added by NSDA QUALIFICATION FILE – CONTACT DETAILS OF SUBMITTING BODY Name and address of submitting body: NATIONAL INSTITUTE OF ELECTRONICS AND INFORMATION TECHNOLOGY (NIELIT), NIT CAMPUS POST, CALICUT, KERALA PIN – 673601 Name and contact details of individual dealing with the submission Name: Sreejeesh SG Designation: Technical Officer Mobile: 9447769756 Email: sreejeesh@nielit.gov.in, sree@calicut.nielit.in List of documents submitted in support of the Qualifications File a) Annexure I- Course Curriculum b) Annexure II – Industry Validation (1) Section 3: Evidence of job market / Industry requirement (2) Occupational Map: Since the proposed jobrole has not been identified by SSC, the industry mapping will be as per progression pathways as indicated in the QF QUALIFICATION FILE: Certificate Program on System Verilog and UVM (Level 7) SUMMARY Qualification Title: Certificate Program on System Verilog and UVM Qualification Code NIELIT/ES/L7/022 Nature and purpose of This Qualification is aligned to Level the qualification: The purpose of this qualification is to train the students to be ready for ASIC Verification Engineer Body /bodies which will National Institute award the qualification: Technology Body which will accredit National providers to offer Technology Institute of Electronics and Information of Electronics and Information of Electronics and Information courses leading to the qualification: Body /bodies which will Be for National responsible Design Verification Engineer, System Level Verification Occupation(s) to which qualification gives access: Engineer, ASIC Verification Engineer, VLSI Verification Engineer, Design Verification Engineer and Functional Verification Application Engineer Licensing Requirements Proposed level of the qualification in the NSQF Anticipated Institute Technology assessment: the Examination Cell, volume N/A Level of training/learning required to complete the 320 Hours qualification B.E/B.Tech/B.Sc/MSc/Engineering Graduates/PG in Entry requirements/ Recommendations Electrical/Electronics/Electronics &Communication/ Bio-Medical Engineering/Medical Electronics/Electronics & Instrumentation/Computer Science and allied branches Prerequisites: Knowledge in Verilog HDL, C, C++, QUALIFICATION FILE: Certificate Program on System Verilog and UVM (Level 7) OOPS Concepts Professional: Progression from the Design/ASIC/VLSI Verification Engineer-> System Level Verification Engineer->Verification Manager Academic: M.Tech in VLSI/ Embedded System Design/ Qualification Electronics System Design  Integrated PhD involving application research Planned arrangements Presently only candidates who undergo training shall be for assessed RPL It will be incorporated once RPL strategy is finalized International Compatibility where Not Known Yet Known Date of Planned review of the Qualification After Every Years Formal Structure of the Qualification Mandator Title ofComponent and Identification Code y/ Optional Estimated Size (Learning Level hours) System Verilog and UVM M 200 Project M 120 Detailed Curriculum attached as - Annexure I SECTION -1 QUALIFICATION FILE: Certificate Program on System Verilog and UVM (Level 7) ASSESSMENT Name of Assessment body: Examination Cell, National Institute of Electronics and Information Technology 6-CGO Complex, Electronics Niketan Lodhi Road, New Delhi 110003 Name of body checking or verifying Assessments: Examination Cell, National Institute of Electronics and Information Technology 6-CGO Complex, Electronics Niketan Lodhi Road, New Delhi 110003 Name of Qualification Awarding body: National Institute of Electronics and Information Technology Will the assessment body be responsible for the RPL assessment? RPL Policy will be described as and when available Describe the overall assessment strategy and specific arrangements which have been put in place to ensure that assessment is always valid, consistent and fair and show that these are in line with the requirements of NSQF: This course would lay more emphasis on developing the practical skills of the student His overall knowledge shall be tested based on a comprehensive written assessment, his practical skills shall be equally measured with a detailed practical assessment The communication/technical skills of the student and his ability to express himself shall be tested in Viva Voce Assessment Each assessment shall define an OUTCOME and marked separately Student shall be required to pass in all OUTCOMEs individually and marks shall be allotted for each OUTCOME along with final aggregate marks in course Following assessment methodologies may be used: A Written Assessment B Practical Assessment C Viva Voce Assessment QUALIFICATION FILE: Certificate Program on System Verilog and UVM (Level 7) Supporting evidences for Assessment The assessment results are backed by following evidences The assessor collects a copy of the attendance for the training done under the scheme The attendance sheets are signed and stamped by the In charge / Head of the Training Centre The assessor verifies the authenticity of the candidate by checking the photo ID card issued by the institute as well as any one Photo ID card issued by the Central/Government The same is mentioned in the attendance sheet ASSESSMENT EVIDENCE Job Role: Design Verification Engineer, System Level Verification Engineer, ASIC Verification Engineer, VLSI Verification Engineer, Design Verification Engineer and Functional Verification Application Engineer Title of Unit/Component: Certificate Program on System Verilog and UVM Means of Assessment Outcomes to be Assessment Criteria for the assessed outcome System On Chip Develop SoC verification Total Written Practical Project Marks 100 50 50 (SoC) Verification environment based on using Object Object Oriented Oriented Programming Concepts Demonstrate the data flow and control flow in SoC Verification environment based on data structures, multithreading etc QUALIFICATION FILE: Certificate Program on System Verilog and UVM (Level 7) Methodology 150 Design Verification 50 100 Na based Verification Architecture for a specific of VLSI Circuits IP Use Universal Verification Methodology (UVM) Verification library for IP Verification Use of Synopsys/ CADENCE/Mentor Graphics Tools for UVM Libraries Grand Total 250 Pass/Fail Following Grading Scheme (on the basis of total marks) will be followed: Grade Marks Range (in %) S A >90% 80%-89% B 70%79% C D E Fail 60%-69% 50%-59% 40-49% System Level Verification Engineer->Verification