Name Thái Đình Chinh Class SE17C01 – CEA201 ID DE170147 5 4 Figure 5 6 indicates how to construct a module of chips that can store 1 MByte based on a group of four 256 Kbyte chips Let’s say this modul.
Name: Thái Đình Chinh Class: SE17C01 – CEA201 ID: DE170147 5.4 Figure 5.6 indicates how to construct a module of chips that can store MByte based on a group of four 256-Kbyte chips Let’s say this module of chips is packaged as a single 1-Mbyte chip, where the word size is byte Give a highlevel chip diagram of how to construct an 8-Mbyte computer memory using eight 1-Mbyte chips Be sure to show the address lines in your diagram and what the address lines are used for Answer: What we have: Number of bit address: 8MB = 23 * 220 B= 223 B => 23 bits address If the all the chips operate according to the topology of example 5.6 Each select chip will need 20 address bits (1MB = 220 B) Remaining bits: 23 – 20 = bít If we use construct an 8-MB computer memory using eight 1-MB chips We need high-order bits are needed to distinguish the above eight chips 5.6 The memory of a particular microcomputer is built from 64K * DRAMs According to the data sheet, the cell array of the DRAM is organized into 256 rows Each row must be refreshed at least once every ms Suppose we refresh the memory on a strictly periodic basis a What is the time period between successive refresh requests? b How long a refresh address counter we need? Answer: a According to the data sheet, each row must be refreshed at least once every ms There for 256 rows have to refresed one by one within ms The refresh period successive from row to row must be no greater than: 4/256 = 0.015625 ms = 15.625 μs b The cell array of the DRAM is organized into 256 rows We need bits to refresh address counter (256 = 28) 6.3 Consider a magnetic disk drive with surfaces, 512 tracks per surface, and 64 sectors per track Sector size is kB The average seek time is ms, the track-totrack access time is 1.5 ms, and the drive rotates at 3600 rpm Successive tracks in a cylinder can be read without head movement a What is the disk capacity? b What is the average access time? Assume this file is stored in successive sectors and tracks of successive cylinders, starting at sector 0, track 0, of cylinder i c Estimate the time required to transfer a 5-MB file d What is the burst transfer rate? Answer: a Disk capacity = Number of surfaces * Number of tracks per surface * Number of sectors per track * Sector size => Disk capacity = * 512 * 64 * 1kB = 23+9+6+10 B = 228 B = 256 MB b Rotational latency has the definition: Describes the time required to position a specific sector under the read–write head Average latency is typically given as the time it takes the drive to perform half a rotation of the platter, and is directly dependent on its RPM rating Rotation time = 60 / the drive rotates ( time to make a rotation ) => Rotational latency = rotation time / = ≈ 8.33 ms The seek time = 8ms * Average access time = seek time + rotational latency ≈16.33 ms c The cylinder capacity: * 64 * KB = 219 B = 512 KB = 0.5 MB ( Because each cylinder includes: tracks * 64 sectors per track * 1KB per sector) The number of cylinder is: 5MB / 0.5 MB = 10 cylinders The disk will need the seek time of ms to find cylinder i, 8.3 ms on average to find sector 0, and × ( 60 / 3600*100 ) = 133.3 ms to read all tracks on one cylinder The track-to-track access time is 1.5 ms => Access Time = + × (8.3 + 133.3 + 1.5) + (8.3 + 133.3) = 1437.5 ms (After the last cylinder, we don’t have the track-to-track access time) d External transfer rate is commonly called burst data transfer rate or interface transfer rate It refers to the speed of outputting data from the hard disk cache Basically it is number of bytes that get transferred per unit of time Burst rate = RPM/60 * sectors per track * bytes per sector = 3600/60 * 64 *1KB = 3932160 B/ s = 3.75 MB / s 6.4 Consider a single-platter disk with the following parameters: rotation speed: 7200 rpm; number of tracks on one side of platter: 30,000; number of sectors per track: 600; seek time: one ms for every hundred tracks traversed Let the disk receive a request to access a random sector on a random track and assume the disk head starts at track a What is the average seek time? b What is the average rotational latency? c What is the transfer time for a sector? d What is the total average time to satisfy a request? Answer: a In a case that we assumed the head starts at track 0, then the calculations are simplified If the request track is track 0, then the seek time is If the requested track is track 29,999, then the seek time is the time to traverse 29,999 tracks For a random request, on average the number of tracks traversed is 29,999/2 = 14999.5 tracks Seek time: one ms for every hundred tracks traversed: => Average seek time = 14999.5 * / 100 = 149.995 ms b Rotation speed: 7200 rpm => One revolution need : 60s / 7200 ≈ 0.00833 s = 8.33 ms => Rotational latency = 8.33 / ≈ 4.167 ms c With 600 sectors per track and the time for one complete revolution of 8.333 ms The transfer time for one sector = the time for one complete revolution / sectors per track = 8.333 ms/ 600 = 0.01389 ms d We have the total average time to satisfy a request = sum of average seek time(a) + rotational latency(b) + transfer time for a sector(c) = 149.995 + 4.167 + 0.01388 = 154.17588 ms 7.14 Examination of the timing diagram of the 8237A indicates that once a block transfer begins, it takes three bus clock cycles per DMA cycle During the DMA cycle, the 8237A transfers one byte of information between memory and I/O device a Suppose we clock the 8237A at a rate of MHz How long does it take to transfer one byte? b What would be the maximum attainable data transfer rate? c Assume that the memory is not fast enough and we have to insert two wait states per DMA cycle What will be the actual data transfer rate? Answer: a Bus cycle = / f = / ( * 106 ) = 0.2 μs It takes three bus clock cycles per DMA cycle which mean to transfer one byte, it takes bus clock cycles Time to transfer one byte = * Bus cycle = 0.6 μs b Data Rate: Data Rate is defined as the amount of data transmitted during a specified time period over a network In this case: Data rate = 1B / Time to transfer one B = / (0.6 * 10-6 ) = 1.67 MB/s c If we have to insert two wait states per DMA cycle We need more * 0.2 μs to wait for each one byte Time to transfer one byte = 0.6 μs + * 0.2 μs = μs In this case: Data rate = 1B / Time to transfer one B = / (1 * 10-6 ) = MB/s 7.18 A computer consists of a processor and an I/O device D connected to main memory M via a shared bus with a data bus width of one word The processor can execute a maximum of 106 instructions per second An average instruction requires five machine cycles, three of which use the memory bus A memory read or write operation uses one machine cycle Suppose that the processor is continuously executing “background” programs that require 95% of its instruction execution rate but not any I/O instructions Assume that one processor cycle equals one bus cycle Now suppose the I/O device is to be used to transfer very large blocks of data between M and D a If programmed I/O is used and each one-word I/O transfer requires the processor to execute two instructions, estimate the maximum I/O data-transfer rate, in words per second, possible through D b Estimate the same rate if DMA is used Answer: a If the processor is continuously executing “background” programs that require 95% of its instruction execution rate but not any I/O instructions The processtor only give 5% for I/O The maximum I/O instruction execution rate is: 106 * 5% / 100% = 50000 instruc/s Each one-word I/O transfer requires the processor to execute two instructions which mean the maximum I/O data-transfer rate in words per second = The maximum I/O instruction execution rate / = 25000 instruc/s b An average instruction requires five machine cycles, three of which use the memory bus And the processor is using 95% for another task, so at that time DMA don’t able to use memory bus Therefore, for 95% of the time, DMA can only use the remaining two cycles The remaining 5% of the time, the CPU isn't using the memory bus, therefore all of the DMA cycles are its own The number of machine cycles available for DMA control = 106 * (5% * + 95% * 2) = 2.15 * 106 instructions /s ... per surface * Number of sectors per track * Sector size => Disk capacity = * 5 12 * 64 * 1kB = 23 +9+6+10 B = 22 8 B = 25 6 MB b Rotational latency has the definition: Describes the time required to... cell array of the DRAM is organized into 25 6 rows We need bits to refresh address counter (25 6 = 28 ) 6.3 Consider a magnetic disk drive with surfaces, 5 12 tracks per surface, and 64 sectors per... once every ms There for 25 6 rows have to refresed one by one within ms The refresh period successive from row to row must be no greater than: 4 /25 6 = 0.015 625 ms = 15. 625 μs b The cell array of