Metal Oxide Resistive Switching Memory

Metal Oxide Resistive Switching Memory Shimeng Yu, Byoungil Lee, H.-S Philip Wong Center for Integrated Systems and Department of Electrical Engineering, Stanford University 13.1 Introduction Information storage device is a key component of nanoelectronic systems Conventional memories such as SRAM, DRAM, and FLASH are facing formidable device scaling challenges Emerging memory device concepts have been actively pursued both in industry and academia in hopes of finding solutions for future information storage needs [1-2] The ideal characteristics for a memory device include fast programming speed (~ns), long retention time (>10 years), low power consumption, good reliability, high integrated density, and continued scalability Several candidates have been proposed to achieve the above goals, such as magnetoresistive random access memory (MRAM) [3], ferroelectric random access memory (FeRAM) [4] In recent years, memory devices based on the electrically switchable resistance phenomenon have been extensively studied The basic principle of this kind of memory is to use a high resistance state (HRS) or low resistance state (LRS) to store the information data “0” or “1”, and the transition between the two states can be triggered by electrical inputs Roughly speaking, resistive switching memories can be classified into three groups [5]: (i) phase-change memory (PCM) based on chalcogenides [6-9], which relies on the temperature induced change between the crystalline phase (corresponding to LRS) and the amorphous phase (corresponding to HRS) (ii) programmable-metallization-cell (PMC) memory based on solid electrolytes or polymers [10-13], which relies on the formation (corresponding to LRS) or the rupture (corresponding to HRS) of a metallic conducting bridge between two electrodes, and (iii) resistance random access memory (RRAM) based on metal oxides Among these resistive switching memories, metal oxide memory is promising for practical applications due to its compatibility with silicon CMOS fabrication technology Here, we review the research progress of metal oxide memory including the physical mechanism of switching, state of the art device performances, as well as device cell structure for integration into a memory array The negative differential resistances phenomenon in oxides was firstly reported in the 1960s [14-15], then it was reviewed by G Dearnaley et al [16] in 1970 Recent work on the resistive switching metal oxide memory can be traced back to the discovery of hysteresis I-V characteristics in perovskite oxides [17-19] such as Pr0.7Ca0.3MnO3, SrTiO3, SrZrO3, etc in the late 1990s and the early 2000s Since 2004, the research activities have focused on binary metal oxides [20-26] such as NiO, TiO 2, ZrO2, ZnO, Cu2O, Al2O3, HfO2, etc because of the simplicity of the material and good compatibility with silicon CMOS fabrication process Recently, the performance of perovskite oxide memories and related physical mechanism of resistive switching were reviewed by R Waser et al [27-28] and A Sawa [29] Therefore, here we focus this review on binary metal oxide memory 13.1.1 Device Operation It is necessary to first introduce some basic concepts and terminologies about metal oxide memory The typical metal oxide memory cell is a simple metal-insulator-metal (MIM) structure, as shown in Fig (a) The switching event from high resistance state (HRS) to low resistance state (LRS) is referred to as the “set” process Conversely, the switching event from LRS to HRS is referred to as the “reset” process In some cases, for the fresh samples in its initial resistance state (IRS), a larger voltage is needed to trigger on the resistive switching behaviors for the subsequent cycles This is called the “electroforming” or “forming” process The switching modes of metal oxide memory can be broadly classified into two switching modes: unipolar and bipolar Unipolar switching means the switching direction depends on the amplitude of the applied voltage but not on the polarity, thus set/reset can occur at the same polarity, and usually it can symmetrically occur at both forward and reversed voltages, as illustrated in Fig 1(b) Bipolar switching means the switching direction depends on the polarity of the applied voltage, thus set can only occur at one polarity and reset can only occur at the reverse polarity, as illustrated in Fig (c) To avoid a hard dielectric breakdown in the set process, it is recommended to enforce a set compliance current, which is usually provided by the semiconductor parameter analyzer, or more practically, by a memory cell selection (or access) transistor/diode or a series resistor To read the data from the cell, a small voltage is applied that does not affect the state of the memory cell For nonvolatile application, the cell should retain its state at standby mode and free from disturb from reading/writing of neighboring cells Fig (a) Schematic of metal-insulator-metal (MIM) structure for metal oxide memory cell, and schematic of metal oxide memory’s I-V curves, showing two modes of operation: (b) unipolar and (c) bipolar 13.1.2 Device Characteristics To further understand how the metal oxide memory works, the device characteristics of HfO2 based memory cell [30-31] from Industrial Technology Research Institute (ITRI) are presented as an example Fig (a) shows the transmission electron microscopy (TEM) image of the concave structure device of TiN/Ti/HfOx/TiN stack with 30 nm cell size; here nm HfO x layer is used for the main switching layer, TiN is used for the electrode material, and a thin Ti buffer layer is used for improving the switching stability Fig (b) shows the typical I-V curve of such memory cell A 200 µA set compliance current is enforced, and the device exhibits bipolar switching Fig (c) shows the switching endurance testing result The set/reset programming condition is +1.5 V/-1.4 V pulse with 500 µs width, and it is seen that after 10 switching cycles, the HRS/LRS resistance ratio is still larger than 100, although there is some degradation Fig (d) shows the data retention testing result, the measurement is performed at 150 °C, and it is seen that 10 years lifetime is expected using a simple linear extrapolation Besides, fast switching speed (~5 ns), and multi-bit storage potential is also demonstrated in the HfO2 memory Besides HfO2, other binary metal oxides such as NiO, TiO 2, ZrO2, ZnO, Cu2O, Al2O3 have been extensively explored Up to now, dozens of binary metal oxides have been found to exhibits electricfield-induced bistable resistance switching behavior Most of the metals are transition metals, and some are lanthanide series metals The materials for switching layer and electrode layer are summarized in Table 13.1 Note that some nitrides, e.g TiN are also used for the electrode layer Fig (a) Transmission electron microscopy (TEM) image of the concave structure device of TiN/Ti/HfOx/TiN stack; (b) Typical I-V curve of the device with the cell size of 30 nm; (c) Endurance testing by 500 µs pulse: successive 10 switching cycles is achieved; (d) Retention testing at 150 °C: 10 years lifetime is expected Reprinted from Ref [30-31] Table 13.1 Summary of the materials that has been used for binary metal oxide memory Yellow metals corresponding binary oxides are used for switching layer; blue metals are used for electrode layer 13.2 Possible Physical Mechanism for Resistive Switching in Metal Oxides The physical mechanism for resistive switching in metal oxide memory is still under a heated debate According to ITRS 2007 [32], resistive switching mechanism can be roughly classified into three groups: thermal effect, electronic effect, or ionic effect Thermal effect refers to the thermal dissolution of conductive filaments triggered by local Joule-heating and works like a traditional household fuse albeit at the nanoscale [33-34] It is also referred to as fuse/anti-fuse switching type The electronic effect mechanism conjectures that injected charges are trapped by interface defects These trapped charges modify the Schottky barrier height between electrodes and oxides and thereby changing the conductance through the MIM structure [35-36] Another case of electronic effect is Mott metal-insulator-transition due to the strong electron-electron correlation in some transition metal oxides [37-38] Ionic effect refers to the migration of ions with related electrochemical reactions to form a conducting bridge between electrodes [39-40] It is also referred to as reduction/oxidation type Actually, this ionic effect is just the operating principle of programmable-metallization-cell memory in solid electrolytes or polymers as mentioned before Metal oxides can also serve as fast ions conductors for some particular metal ions like Ag+ and Cu2+ [41-42] Here we plan to focus on the intrinsic properties of metal oxides, thus we would not include those metal oxides memory with Ag or Cu electrodes in the following discussions So far, no single model mentioned above can explain all the experimental results obtained in various materials It seems that the thermal dissolution model can address parts of the unipolar switching characteristics, while the ionic migration model can explain most of the bipolar switching characteristics However, the distinction between the two switching behaviors is ambiguous Here we discuss several key issues such as the conducting mechanism, the nature of electroforming/set/reset process, the effect of electrode materials on switching modes, with the aim of seeking a rational mechanism for both unipolar and bipolar switching characteristics 13.2.1 Conduction Mechanism A lot of conductive atomic force microscopy (C-AFM) measurements [43-47] have been reported in the literature, revealing that conductive filaments (CFs) with nanoscale diameters are formed in the oxide layer during the set process, and large conducting current passes through these filaments in LRS Fig shows one of these C-AFM measurements results [45] Typically, CFs are sparsely and non-homogeneously distributed under the electrodes This means that the conducting area in LRS is an extremely small portion of the entire electrode area, which is typically quite large in most experiments Therefore, the conductance in LRS would not decrease as much as the conductance in HRS does when the electrode area is decreased, resulting a larger HRS/LRS resistance ratio, which is a benefit of scaling down memory cell size It has been experimentally demonstrated that these CFs can be formed by C-AFM tip individually [48], but in most cases multiple CFs exist in the oxide layer, which is believed to be responsible for the multi-level switching behaviors exhibited in some metal oxide memory devices [49-50] Although the filamentary conduction mechanism is widely recognized, some researchers argued that a bulk conduction mechanism dominates the LRS resistance in their TiO devices [51] They proposed that charged dopants (mainly oxygen vacancies) migrate under a voltage bias to the TiO2/electrode interface The interfacial changes modify the Schottky barrier height at the interface and lead to the resistive switching in their devices In essence, such arguments not contradict with the filamentary conduction mechanism, provided that the so-called bulk conduction is regarded as many parallel CFs It should be noted that if CFs are dense enough in ultra-scaled devices, the bulk conduction behavior may arise A usual experiment that aims at distinguishing filamentary or bulk conduction is to measure the trend of the HRS/LRS resistance ratio versus the cell area If the ratio goes up when the cell area is scaled down, filamentary conduction prevails If the ratio remains almost constant when the cell is scaled down, bulk conduction prevails However, so far, these experiments have not been performed for devices with truly nanometer scale size (< 100 nm) memory cells and therefore the results are not yet conclusive Fig Conductive atomic force microscopy (C-AFM) of LRS (a) and HRS (b) conductance in Al2O3 memory, showing filamentary conduction dominates in LRS (scanned area: àmì2 àm; maximum y scale: (a) 105 nA, (b) nA) Reprinted from [45] The CFs are conjectured to be made up of oxygen vacancies (Vo) in most metal oxide memory devices, and this assumption was confirmed by micro X-ray fluorescence (XRF) and X-ray absorption near-edge spectroscopy (XANES) [52] It is well known that Vo can act as an effective donor in n-type metal oxides Ab-initio calculation of the rutile TiO2 electronic structure [53] reveals that Vo can produce a defect state within the band gap This state is occupied by two electrons that are localized on Ti 3d orbital of the nearest Ti atoms to Vo If a chain of such Vo forms, it is expected that electrons delocalization occurs and the hopping probability can increase remarkably along these CFs and ultimately lead to the LRS Although Vo plays an important role in the switching behaviors of most metal oxide memory devices, the composition of CFs is not limited to Vo There are quite a few reports that the CFs in NiO memory are composed of excess metallic Ni in NiO This suggestion is confirmed by measurement of the dependence of the LRS resistance on temperature [54] and XPS composition analysis [55] It was further verified by electron energy loss spectroscopy (EELS) that there exists a Ni-rich phase at the grain boundaries, which implies that the CFs of Ni are formed as precipitates at the grain boundaries [56] A simple way to distinguish whether the CFs are metallic or semiconducting is to measure the LRS resistance temperature dependency If the LRS resistance goes up with the 10 increase of temperature, the CFs are metallic and may consist of metal precipitates On the contrary, if the LRS resistance drops with the increase of temperature, CFs are semiconducting and may consist of Vo There are many efforts to fit the I-V characteristics of HRS and LRS to current conduction models in the literature Most of the reports show an Ohmic relationship in the LRS And in the semiconducting CFs, Mott variable hopping conduction [57] is proposed to dominate in LRS, and this assumption was supported by some temperature varying measurements [58-59] and AC conductance measurement [60] But, the conduction fitting results in HRS are quite diverse, Poole-Frenkel emission (I~V*exp(V 1/2)) [6162], Schottky emission (I~exp(V1/2)) [63-64], the space charge limited current (SCLC) characteristic (the Ohmic region I~V, followed by the child’s square law region I~V2) [65-66], were observed in various metal oxide memories The diverse I-V characteristics in HRS involving different leakage mechanism may be associated with the different dielectric properties or different fabrication processes conditions, e.g annealing temperature, annealing ambient, and the properties of the interface between the oxides and the electrodes Nevertheless, the key issue of metal oxides memory modeling is not the leakage current mechanism in HRS, but to investigate the mechanism that triggers the resistive switching So in the next section, we will discuss the forming/set and reset process, respectively 32 forming CFs The key idea of these techniques is to induce the formation and rupture of CFs in specific locations during the switching instead of allowing them to occur randomly Besides materials solutions mentioned above, novel programming methods are also helpful in reducing parameter fluctuations Using multiple pulses rather than a single pulse [128] or using a ramped series of pulses [129] can remarkably improve the cycle to cycle uniformity To summarize, the scalability of metal oxide memory devices is the most competitive characteristics compared with other emerging memories It is foreseeable to achieve sufficient noise margin (>10X), low energy consumption (