Danh sách DATA SHEET các IC 74HC151, 74LS1389, 74LS192_2, 74LS193, 74LS194, 7400, 7408, 7476, 7492, 7493, 74138, 74139, 74151, 74164, 74247, cd4511b, dm74ls32, 7404, sn54ls04sp, sn54ls93, sn74ls247, sn5476.
Revised February 1999 MM74HC151 8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology Along with the high noise immunity and low power dissipation of standard CMOS integrated circuits, it possesses the ability to drive 10 LS-TTL loads The MM74HC151 selects one of the data sources, depending on the address presented on the A, B, and C inputs It features both true (Y) and complement (W) outputs The STROBE input must be at a low logic level to enable this multiplexer A high logic level at the STROBE forces the W output HIGH and the Y output LOW The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground Features ■ Typical propagation delay data select to output Y: 26 ns ■ Wide operating supply voltage range: 2–6V ■ Low input current: µA maximum ■ Low quiescent supply current: 80 µA maximum (74HC) ■ High output drive current: mA minimum Ordering Code: Order Number MM74HC151M MM74HC151SJ MM74HC151MTC MM74HC151N Package Number Package Description M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC16 N16E 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Devices also available in Tape and Reel Specify by appending the suffix letter “X” to the ordering code Connection Diagram Truth Table Pin Assignments for DIP, SOIC, SOP and TSSOP Inputs Select Top View Outputs Strobe C B A S X X X H L H L L L L D0 D0 L L H L D1 D1 L H L L D2 D2 L H H L D3 D3 H L L L D4 D4 H L H L D5 D5 H H L L D6 D6 H H H L D7 D7 H = HIGH Level, L = LOW Level, X = Don't Care D0, D1 D7 = the level of the respective D input Y W MM74HC151 8-Channel Digital Multiplexer September 1983 MM74HC151 Logic Diagram Recommended Operating Conditions −0.5 to +7.0V Supply Voltage (VCC) DC Input Voltage (VIN) −1.5 to VCC +1.5V DC Output Voltage (VOUT) −0.5 to VCC +0.5V Clamp Diode Current (IIK, IOK) ±20 mA DC Output Current, per pin (IOUT) ±25 mA DC VCC or GND Current, per pin (ICC) ±50 mA Storage Temperature Range (TSTG) −65°C to +150°C Min Max Supply Voltage (VCC) V DC Input or Output Voltage VCC V −40 +85 °C (tr, tf) VCC = 2.0V 1000 ns VCC = 4.5V 500 ns VCC = 6.0V 400 ns (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times Power Dissipation (PD) (Note 3) 600 mW S.O Package only 500 mW Lead Temperature (TL) 260°C Note 3: Power Dissipation temperature derating — plastic “N” package: − 12 mW/°C from 65°C to 85°C DC Electrical Characteristics VIH VIL Parameter Conditions (Note 4) VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Minimum HIGH Level 2.0V 1.5 1.5 1.5 V Input Voltage 4.5V 3.15 3.15 3.15 V 6.0V 4.2 4.2 4.2 V Maximum LOW Level 2.0V 0.5 0.5 0.5 V 4.5V 1.35 1.35 1.35 V 6.0V 1.8 1.8 1.8 V Input Voltage VOH Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur Note 2: Unless otherwise specified all voltages are referenced to ground (Soldering 10 seconds) Symbol Units Minimum HIGH Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V 4.5V 4.5 4.4 4.4 4.4 V 6.0V 6.0 5.9 5.9 5.9 V |IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V |IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V VIN = VIH or VIL VOL Maximum LOW Level VIN = VIH or VIL Output Voltage |IOUT| ≤ 20 µA 2.0V 0.1 0.1 0.1 V 4.5V 0.1 0.1 0.1 V 6.0V 0.1 0.1 0.1 V V VIN = VIH or VIL IIN |IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 |IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V VIN = VCC or GND 6.0V ±0.1 ±1.0 ±1.0 µA Maximum Quiescent VIN = VCC or GND 6.0V 8.0 80 160 µA Supply Current IOUT = µA Maximum Input Current ICC Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V Thus the 4.5V values should be used when designing with this supply Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used MM74HC151 Absolute Maximum Ratings(Note 1) (Note 2) MM74HC151 AC Electrical Characteristics VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = ns Symbol tPHL, tPLH Parameter Conditions Guaranteed Typ Maximum Propagation Delay Units Limit 26 35 ns 27 35 ns 22 29 ns 24 32 ns 17 23 ns 16 21 ns A, B or C to Y tPHL, tPLH Maximum Propagation Delay A, B or C to W tPHL, tPLH Maximum Propagation Delay Any D to Y tPHL, tPLH Maximum Propagation Delay any D to W tPHL, tPLH Maximum Propagation Delay Strobe to Y tPHL, tPLH Maximum Propagation Delay Strobe to W AC Electrical Characteristics CL = 50 pF, tr = tf = ns (unless otherwise specified) Symbol tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tPHL, tPLH tTLH, tTHL CPD Parameter Conditions VCC TA = 25°C Typ TA = −40 to 85°C TA = −55 to 125°C Guaranteed Limits Units Maximum Propagation Delay 2.0V 90 205 256 300 ns A, B or C to Y 4.5V 31 41 51 60 ns ns 6.0V 26 35 44 51 Maximum Propagation Delay 2.0V 95 205 256 300 ns A, B or C to W 4.5V 32 41 51 60 ns ns 6.0V 27 35 44 51 Maximum Propagation Delay 2.0V 70 195 244 283 ns any D to Y 4.5V 27 39 49 57 ns ns 6.0V 23 33 41 48 Maximum Propagation Delay 2.0V 75 185 231 268 ns any D to W 4.5V 29 37 46 54 ns ns 6.0V 25 32 40 46 Maximum Propagation Delay 2.0V 50 140 175 203 ns Strobe to Y 4.5V 21 28 35 41 ns ns 6.0V 18 24 30 35 Maximum Propagation Delay 2.0V 45 127 159 185 ns Strobe to W 4.5V 20 25 32 37 ns 6.0V 17 22 28 32 ns Maximum Output Rise 2.0V 30 75 95 110 ns and Fall Time 4.5V 15 19 22 ns 6.0V 13 16 19 Power Dissipation (per package) 110 ns pF Capacitance (Note 5) CIN Maximum Input 10 10 10 Capacitance Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD V CC f + ICC pF 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D MM74HC151 Physical Dimensions inches (millimeters) unless otherwise noted MM74HC151 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E MM74HC151 8-Channel Digital Multiplexer Physical Dimensions inches (millimeters) unless otherwise noted (Continued) General Description Features These Schottky-clamped circuits are designed to be used in high-performance memory-decoding or data-routing applications, requiring very short propagation delay times In high-performance memory systems these decoders can be used to minimize the effects of system decoding When used with high-speed memories, the delay times of these decoders are usually less than the typical access time of the memory This means that the effective system delay introduced by the decoder is negligible ■ Designed specifically for high speed: The DM74LS138 decodes one-of-eight lines, based upon the conditions at the three binary select inputs and the three enable inputs Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding A 24-line decoder can be implemented with no external inverters, and a 32-line decoder requires only one inverter An enable input can be used as a data input for demultiplexing applications ■ Typical propagation delay (3 levels of logic) Memory decoders Data transmission systems ■ DM74LS138 3-to-8-line decoders incorporates enable inputs to simplify cascading and/or data reception ■ DM74LS139 contains two fully independent 2-to-4-line decoders/demultiplexers ■ Schottky clamped for high performance DM74LS138 21 ns DM74LS139 21 ns ■ Typical power dissipation DM74LS138 32 mW DM74LS139 34 mW The DM74LS139 comprises two separate two-line-to-fourline decoders in a single package The active-low enable input can be used as a data line in demultiplexing applications All of these decoders/demultiplexers feature fully buffered inputs, presenting only one normalized load to its driving circuit All inputs are clamped with high-performance Schottky diodes to suppress line-ringing and simplify system design Ordering Code: Order Number Package Number Package Description DM74LS138M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS138SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS138N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide DM74LS139M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS139SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide DM74LS139N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Devices also available in Tape and Reel Specify by appending the suffix letter “X” to the ordering code www.sycelectronica.com.ar DM74LS138 • DM74LS139 Decoder/Demultiplexer 74LS138 / 74LS138-SMD / 74LS139 Decoder/Demultiplexer DM74LS138 • DM74LS139 Connection Diagrams DM74LS138 DM74LS139 Function Tables DM74LS138 DM74LS139 Inputs Enable Inputs Outputs Select Enable G1 G2 (Note 1) C B A YO Y1 Y2 Y3 Y4 Y5 Y6 Y7 Outputs Select G B A Y0 Y1 Y2 Y3 X H X X X H H H H H H H H H X X H H H H L X X X X H H H H H H H H L L L L H H H H L L L L L H H H H H H H L L H H L H H H L L L H H L H H H H H H L H L H H L H H L L H L H H L H H H H H L H H H H H L H L L H H H H H L H H H H H L H L L H H H H L H H H H L H L H H H H H H L H H H L H H L H H H H H H L H H L H H H H H H H H H H L H = HIGH Level L = LOW Level X = Don’t Care Note 1: G2 = G2A + G2B Logic Diagrams DM74LS138 DM74LS139 www.sycelectronica.com.ar Supply Voltage Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed The device should not be operated at these limits The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings The “Recommended Operating Conditions” table will define the conditions for actual device operation 7V Input Voltage 7V 0°C to +70°C Operating Free Air Temperature Range −65°C to +150°C Storage Temperature Range DM74LS138 Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current mA TA Free Air Operating Temperature 70 °C V DM74LS138 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions Min VI Input Clamp Voltage VCC = Min, II = −18 mA VOH HIGH Level Output Voltage VCC = Min, IOH = Max, VIL = Max, VIH = Min Typ (Note 3) Max −1.5 2.7 3.4 Units V V LOW Level VCC = Min, IOL = Max, VIL = Max, VIH = Min 0.35 0.5 Output Voltage IOL = mA, VCC = Min 0.25 0.4 II Input Current @ Max Input Voltage VCC = Max, VI = 7V 0.1 IIH HIGH Level Input Current VCC = Max, VI = 2.7V 20 µA IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.36 mA IOS Short Circuit Output Current VCC = Max (Note 4) ICC Supply Current VCC = Max (Note 5) VOL −20 V mA −100 mA 10 mA 6.3 Note 3: All typicals are at VCC = 5V, TA = 25°C Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second Note 5: ICC is measured with all outputs enabled and OPEN DM74LS138 Switching Characteristics at VCC = 5V and TA = 25°C Symbol Parameter From (Input) Levels To (Output) of Delay RL = kΩ CL = 15 pF Min tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output tPLH Propagation Delay Time LOW-to-HIGH Level Output tPHL Propagation Delay Time HIGH-to-LOW Level Output Max CL = 50 pF Min Units Max Select to Output 18 27 ns Select to Output 27 40 ns Select to Output 18 27 ns Select to Output 27 40 ns Enable to Output 18 27 ns Enable to Output 24 40 ns Enable to Output 18 27 ns Enable to Output 28 40 ns www.sycelectronica.com.ar DM74LS138 • DM74LS139 Absolute Maximum Ratings(Note 2) PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device SN74LS247DR Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) SN74LS247DR SOIC D 16 2500 333.2 345.9 28.6 Pack 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DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated SN5476, SN54LS76A SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR SDLS121 – DECEMBER 1983 – REVISED MARCH 1988 Copyright 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date Products conform to specifications per the terms of Texas Instruments standard warranty Production processing does not necessarily include testing of all parameters POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN5476, SN54LS76A SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR SDLS121 – DECEMBER 1983 – REVISED MARCH 1988 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN5476, SN54LS76A SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR SDLS121 – DECEMBER 1983 – REVISED MARCH 1988 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN5476, SN54LS76A SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR SDLS121 – DECEMBER 1983 – REVISED MARCH 1988 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN5476, SN54LS76A SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR SDLS121 – DECEMBER 1983 – REVISED MARCH 1988 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN5476, SN54LS76A SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR SDLS121 – DECEMBER 1983 – REVISED MARCH 1988 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 5962-9557501QEA ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 5962-9557501QE A SNJ5476J 5962-9557501QFA ACTIVE CFP W 16 TBD A42 N / A for Pkg Type -55 to 125 5962-9557501QF A SNJ5476W 5962-9557501QFA ACTIVE CFP W 16 TBD A42 N / A for Pkg Type -55 to 125 5962-9557501QF A SNJ5476W 7601301EA ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 7601301EA SNJ54LS76AJ 7601301EA ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 7601301EA SNJ54LS76AJ JM38510/00204BEA ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00204BEA JM38510/00204BEA ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00204BEA M38510/00204BEA ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00204BEA M38510/00204BEA ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 JM38510/ 00204BEA SN5476J ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 SN5476J SN5476J ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 SN5476J SN54LS76AJ ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 SN54LS76AJ SN54LS76AJ ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 SN54LS76AJ SNJ5476J ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 5962-9557501QE A SNJ5476J SNJ5476J ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 5962-9557501QE A SNJ5476J SNJ5476W ACTIVE CFP W 16 TBD A42 N / A for Pkg Type -55 to 125 5962-9557501QF Addendum-Page Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) A SNJ5476W SNJ5476W ACTIVE CFP W 16 TBD A42 N / A for Pkg Type -55 to 125 5962-9557501QF A SNJ5476W SNJ54LS76AJ ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 7601301EA SNJ54LS76AJ SNJ54LS76AJ ACTIVE CDIP J 16 TBD A42 N / A for Pkg Type -55 to 125 7601301EA SNJ54LS76AJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect NRND: Not recommended for new designs Device is in production to support existing customers, but TI does not recommend using this part in a new design PREVIEW: Device has been announced but is not in production Samples may or may not be available OBSOLETE: TI has discontinued the production of the device (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details TBD: The Pb-Free/Green conversion plan has not been defined Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe The component is otherwise considered Pb-Free (RoHS compatible) as defined above Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device (5) Multiple Device Markings will be inside parentheses Only one Device Marking contained in parentheses and separated by a "~" will appear on a device If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options Finish options are separated by a vertical ruled line Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width Addendum-Page Samples PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2017 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information Efforts are underway to better integrate information from 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conducted any testing other than that specifically described in the published documentation for a particular TI Resource Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements Using products in an application does not by itself establish any safety features in the application Designers must ensure compliance with safety-related requirements and standards applicable to their applications Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables) Such equipment includes, without limitation, all medical devices identified by the U.S Food and Drug Administration as Class III devices and equivalent classifications outside the U.S TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product) Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated ... the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption, IS = CPD V CC f + ICC pF 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012 ,... www.sycelectronica.com.ar DM74LS193 Synchronous 4-Bit Binary Counter with Dual Clock 74LS193 Synchronous 4-Bit Binary Counter with Dual Clock DM74LS193 Logic Diagram www.sycelectronica.com.ar Note... www.sycelectronica.com.ar CL = 50 pF Min Units Max 20 MHz 26 30 ns 24 36 ns 24 29 ns 24 32 ns 38 45 ns 47 54 ns 40 41 ns 40 47 ns 35 44 ns DM74LS193 AC Electrical Characteristics DM74LS193 Physical Dimensions