Advanced Computer Architecture - Lecture 13: Instruction level parallelism. This lecture will cover the following: out-of-order execution; problems of out-of-order execution; dynamic scheduling; scoreboard technique; simple pipelined datapath facilitates; MIPS 5-stage pipeline;...
CS 704 Advanced Computer Architecture Lecture 13 Instruction Level Parallelism (Dynamic Scheduling - Scoreboard Approach) Prof Dr M Ashraf Chughtai Today's Topics Recap - Lecture 11-12 Out-of-Order Execution Dynamic Scheduling Scoreboard Technique Summary MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) Recap: Lecture 12 - FP and Integer Multiplier - FP and Integer Divider Here, we observed that : - Only one instruction is issued on every clock cycle - the integer ADD instructions go through the FP pipeline as they go through in standard pipeline – as the integer ALU operations have ZERO latency - the FP add and FP/integer multiply and divide instructions enter into loop when they reach EX-stage due to longer latencies of these operations – thus increases the number of stalls before the instruction is issued to EX stage MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) Recap: Lecture 12 RAW and WAR hazards may occur because the instruction are of varying length and may reach WB out-of-order There are different ways to RAW hazard: MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) Recap: Lecture 12 WAW hazard (The jth instruction writes prior to the ith instruction; the ith instruction overwrites the result of jth instruction) MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) Recap: Lecture 12 Two ways to resolve WAW hazard - Delay the issue of jth instruction until the ith instruction enters the MEM stage - Stamp out the ith instruction by detecting the hazard and changing the control (WB) so that the ith instruction does not write Hence, the jth instruction can be issued right-away MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) Today's Topics Out-of-Order Execution Problems of Out-of-order execution Dynamic Scheduling Scoreboard Technique Summary MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) In-Order Execution Simple Pipelined datapath facilitates only the In-order instruction execution, i.e., Instructions are fetched, decoded and issued in the sequence of the program and no later instruction can proceed if an instruction is stalled due to hazard – structural or data dependence MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) In-order Execution … Cont’d For example: in the code DIV.D F0, F2, F4 ADD.D F10, F0, F8 SUB.D F12, F8, F14 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) In-order Execution … Cont’d Conclusion MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 10 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 48 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 49 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 50 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 51 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 52 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 53 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 54 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 55 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 56 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 57 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 58 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 59 MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 60 Summary Problems of Out-of-order execution Dynamic Scheduling Scoreboard Technique Summary MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 61 Aslam-u-Alacun And Allah Hafiz MAC/VU-Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 62 ... Divide Lecture 13 – Instruction Level Parallelism -Dynamic (2) 32 MAC/VU -Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 33 MAC/VU -Advanced Computer Architecture. .. Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 34 MAC/VU -Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 35 MAC/VU -Advanced Computer Architecture. .. Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 36 MAC/VU -Advanced Computer Architecture Lecture 13 – Instruction Level Parallelism -Dynamic (2) 37 MAC/VU -Advanced Computer Architecture