Advanced Computer Architecture - Lecture 5: Instruction set principles (Cont''d). This lecture will cover the following: encoding instructions and MIPS Instruction format; instruction set encoding; MIPS instruction set; instruction word types; hybrid length taxonomy;...
CS 704 Advanced Computer Architecture Lecture Instruction Set Principles (Encoding instructions and MIPS Instruction format) Prof Dr M Ashraf Chughtai MAC/VU-Advanced Computer ArchitectureLecture - Instruction Set Principles Cont'd Today’s Topics Recap Lecture Instruction Set Encoding MIPS Instruction Set Summary MAC/VU-Advanced Computer Architecture Cont'd Lecture - Instruction Set Principles Recap: Lecture Three pillars of Computer Architecture Hardware, Software and Instruction Set Instruction Set Interface between hardware and software Taxonomy of Instruction Set: Stack, Accumulator and General Purpose Register Types and Size of Operands: Types: Integer, FP and Character Size: Half word, word, double word Classification of operations Arithmetic, data transfer, control and support MAC/VU-Advanced Computer Architecture Cont'd Lecture - Instruction Set Principles Recap … Cont’d Operand Addressing Modes Immediate, register, direct (absolute) and Indirect Classification of Indirect Addressing Register, indexed, relative (i.e with displacement) and memory Special Addressing Modes Auto-increment, auto-decrement and scaled Control Instruction Addressing modes Branch, jump and procedure call/return MAC/VU-Advanced Computer Architecture Cont'd Lecture - Instruction Set Principles Instruction set Encoding Essential elements of computer instructions Type of the operation to be performed – This information is encoded in the “operation code”, or the op-code, field of the machine language instruction – Examples: add, mov etc Place to find the source operand (s) Possible locations are: CPU registers, memory cells, I/O locations, part of the instruction itself MAC/VU-Advanced Computer Architecture Cont'd Lecture - Instruction Set Principles Computer Instructions Encoding Place to store the results Possible locations are: CPU registers, memory cells and I/O locations Place to find the next instruction from – Address of the next instruction in sequence (this is the default case) – Address of the instruction at the branch target location MAC/VU-Advanced Computer Architecture Cont'd Lecture - Instruction Set Principles Instruction Word Types Variable Length - Operation is specified in one field, Op-code Can support any number of operands Each address specifier determines the addressing mode and length of the specifier for the operand Generally, it generates the smallest code representation as unused fields need not be included Typical Examples: VAX, Intel 80x86 Operation and Address number of Specifier # operands Address field # Address Specifier #n MAC/VU-Advanced Computer Architecture Cont'd Lecture - Instruction Set Principles Address Field # n Variable length Encoding Cont’d Operation and Address number of Specifier # operands Address field # Address Specifier #n Address Field # n - The decision regarding the length depends upon the range of addressing modes and degree of independence between op-code and mode - For example: immediate addressing requires one or two address field whereas indexed addressing requires or fields The length of Intel 80x86 varies between byte and 17 byte and is generally smaller than RICS architecture which uses fixed length format MAC/VU-Advanced Computer Architecture Cont'd Lecture - Instruction Set Principles Fixed Length Format - Always has same number of operands Addressing modes (if option exist) is specified in Op-code It generally generates the largest code size Fields may be used for different purposes, if necessary Typical Examples: Alpha, MIPS, PowerPC, SPARC Operation code Address field # Address field # Address field # MAC/VU-Advanced Computer Architecture Cont'd Lecture - Instruction Set Principles Third Alternative: Hybrid Length Multiple formats are specified by the op-code One or two fields are added to specify addressing mode Similarly, one or two fields specify operand address It generally generates the optimum code size Typical Examples: IBM 360/370, MIPS16, TI-TMS320c54x Operation code Address specifier Address field Operation code Address Specifier # Address Specifier # Address field Operation code Address specifier Address field # Address field # MAC/VU-Advanced Computer Architecture 10 Cont'd Lecture - Instruction Set Principles Result Summary A single byte is used for the op code, 16 MB memory address space, single addressable memory unit: byte, 24 bits operands is 24 bits and 8-bit data bus Instruction Format Code size Number of memory bytes 4address instruction 13 22 3address instruction 10 19 2address instruction 7 16 1address instruction 4 7 0address instruction 1 10 MAC/VU-Advanced Computer Architecture 22 Cont'd Lecture - Instruction Set Principles RISC and MIPS ISA RISC and MIPS is a fixed length, 64-bit LOAD/STORE Architecture Contains 32 GPR each of 32-bit Supports: - 3-address, reg-reg arithmetic instruction - displacement instructions with address offset 12-16 bits - immediate data 8-bit and 16-bit and - register indirect - data size 8-, 16-, 32- and 64-bit integer - 64-bit IEEE 754 floating point MAC/VU-Advanced Computer Architecture 23 Cont'd Lecture - Instruction Set Principles RISC and MIPS ISA …Cont’d Supports … cont’d Instructions: - Data Transfer: load, store, register-register move - Simple Arithmetic: add, subtract, and shift - Compare: equal, not-equal, less - Branch: PC-relative, jump and call/return Designed for pipelining efficiency MAC/VU-Advanced Computer Architecture 24 Cont'd Lecture - Instruction Set Principles MIPS Instruction Word format Recap: MIPS types and size of operands Types of an Operand - Integer - Single-precision floating point - Character Size of Operand - Character - Half word - Single precision FP or Word - Double precision FP or double word 8-bit 16-bit 32-bit 64-bit MAC/VU-Advanced Computer Architecture 25 Cont'd Lecture - Instruction Set Principles MIPS Instruction Word Format Register-Register (R-Type) 31 26 25 Op 21 20 Rs 16 15 Rt Rd 11 10 Sht Func Op-code = 000000 Rs and Rt : source operand registers Rd : Result carrying register Sht: Number of bit-shift –(left/right) Func: ALU function to encode the data path operation Execution: Rd