Tài liệu PCI EXPRESS SYSTEM ARCHITECTURE pdf

[...]... 577 PCI Express Power Management vs ACPI 577 PCI Express Bus Driver Accesses PCI Express Configuration and PM Registers 577 ACPI Driver Controls Non-Standard Embedded Devices 577 Some Example Scenarios 579 Scenario—OS Wishes To Power Down PCI Express Devices 580 Scenario—Restore All Functions To Powered Up State 582 Scenario—Setup a Function-Specific System WakeUp... Completion 766 An Issue For PCI Express- to -PCI or -PCI- X Bridges 767 PCI Special Cycle Transactions 767 xxxi Contents Chapter 22: PCI Compatible Configuration Registers Header Type 0 770 General 770 Header Type 0 Registers Compatible With PCI 772 Header Type 0 Registers Incompatible With PCI 772 Registers Used to Identify... RCRB 957 The RCRB Missing Link 958 Appendices Appendix A: Test, Debug and Verification of PCI Express Designs 961 Appendix B: Markets & Applications for the PCI Express Architecture 989 Appendix C: Implementing Intelligent Adapters and Multi-Host Systems With PCI Express Technology 999 Appendix D: Class Codes 1019 Appendix E: Locked Transactions... Calls Init Code In Each 891 Chapter 24: Express- Specific Configuration Registers Introduction 894 PCI Express Capability Register Set 896 Introduction 896 Required Registers 897 General 897 PCI Express Capability ID Register 898 Next Capability Pointer Register 898 PCI Express Capabilities Register 898... Register 790 Master Latency Timer Register 790 Interrupt Line Register 791 Usage In a PCI Function 791 Usage In a PCI Express Function 791 Interrupt Pin Register 792 Usage In a PCI Function 792 Usage In a PCI Express Function 792 Base Address Registers 792 Introduction 793 IO Space Usage ... Initialization Period In PCI 738 Definition of Initialization Period In PCI- X 739 PCI Express and Initialization Time 739 Initial Configuration Access Failure Timeout 739 Delay Prior To Initial Configuration Access to Device 739 A Device With a Lengthy Self-Initialization Period 740 RC Response To CRS Receipt During Run-Time 740 Chapter 21: PCI Express Enumeration... 351 Devices May Support Both MSI and Legacy Interrupts 352 Special Consideration for Base System Peripherals 353 Example System 353 Chapter 10: Error Detection and Handling Background 356 Introduction to PCI Express Error Management 356 PCI Express Error Checking Mechanisms 356 Transaction Layer Errors 358 Data Link Layer... Target Bus ≤ Subordinate Bus Number 727 Single Host /PCI Bridge 727 Multiple Host /PCI Bridges 729 PCI Express Enhanced Configuration Mechanism 731 Description 731 Some Rules 731 Type 0 Configuration Request 732 Type 1 Configuration Request 733 xxx Contents Example PCI- Compatible Configuration Access 735 Example... 643 Auxiliary Power 645 Part Five: Optional Topics Chapter 17: Hot Plug Background 650 Hot Plug in the PCI Express Environment 651 Surprise Removal Notification 652 Differences between PCI and PCI Express Hot Plug 652 Elements Required to Support Hot Plug 655 Software Elements 655 Hardware Elements ... 702 Form Factors Under Development 703 General 703 Server IO Module (SIOM) 703 Riser Card 704 Mini PCI Express Card 704 NEWCARD form factor 707 xxix Contents Part Six: PCI Express Configuration Chapter 19: Configuration Overview Definition of Device and Function 712 Definition of Primary and Secondary Bus . Topology 48 Enumerating the System 50 PCI Express System Block Diagram 51 Low Cost PCI Express Chipset 51 High-End Server System 53 PCI Express Specifications. MHz PCI Bus Based System 33 Limitations of 66 MHz PCI bus 34 Limitations of PCI Architecture 34 66 MHz and 133 MHz PCI- X 1.0 Bus Based Platforms 35 PCI- X