11002 GS2 Getting Started with PIC® MCU Mid-Range Architecture, Instruction Set and Assembly Language Programming © 2005 Microchip Technology Incorporated All Rights Reserved © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide Class Objective When you finish this class you will: − Understand the basics of the inner workings of a PIC16 − Understand most instructions − Understand memory organization − Understand how to write simple programs © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide Agenda Architecture Basics Instruction Set Overview Memory Organization and Addressing Modes Special Features Hands-on Exercises © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide Architecture The high performance of the PIC® microcontroller can be attributed to the following architectural features: − Harvard Architecture − Instruction Pipelining − Large Register File − Single Cycle Instructions − Single Word Instructions − Long Word Instructions − Reduced Instruction Set − Orthogonal Instruction Set © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide Harvard Architecture Von Neumann Architecture: − − Fetches instructions and data from a single memory space Limits operating bandwidth Harvard Architecture: − − − © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Uses two separate memory spaces for program instructions and data Improved operating bandwidth Allows for different bus widths Slide Instruction Pipelining Instruction fetch is overlapped with execution of previously fetched instruction Instruction Cycles Example Program MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2 T0 T1 T2 Fetch Execute T4 T5 T6 T7 Time to execute normal instruction Fetch Execute Time to execute call instruction includes pipeline flush Fetch Execute Fetch Flush Fetch Fetch Execute 51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return © 2007 Microchip Technology Incorporated All Rights Reserved T3 Fetch Execute Fetch 11002 GS2 Flush Slide Instruction Pipelining Pre-Fetched Instruction Executing Instruction movlw 0x05 Instruction Cycles Example Program MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2 T0 Fetch 51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide Instruction Pipelining Pre-Fetched Instruction Executing Instruction movwf REG1 movlw 0x05 Instruction Cycles Example Program MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2 T0 T1 Fetch Execute Fetch 51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide Instruction Pipelining Pre-Fetched Instruction Executing Instruction call SUB1 movwf REG1 Instruction Cycles Example Program MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2 T0 T1 T2 Fetch Execute Time to execute normal instruction Fetch Execute Fetch 51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide Instruction Pipelining Pre-Fetched Instruction Executing Instruction addwf REG2 call SUB1 Instruction Cycles Example Program MAIN movlw movwf call addwf 0x05 REG1 SUB1 REG2 T0 T1 T2 T3 Fetch Execute Fetch Execute Fetch Execute Fetch 51 SUB1 movf PORTB,w 52 return 53 SUB2 movf PORTC,w 54 return © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 10 Lab 4: Results You have learned: − How to make decisions in software and take different courses of action © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 83 Lab 5: The Task Use a lookup table to obtain the bit pattern to be displayed on PORTB © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 84 Lab 5: Program Structure Instruction Lab Setup Code Instruction Subroutine Call Instruction Instruction Instructions Instructions Instruction Instruction © 2007 Microchip Technology Incorporated All Rights Reserved Instruction 11002 GS2 Slide 85 Lab 5: Template – Part Lab 5: Lookup Table Lab 5: Lookup Table 1 2 3 4 5 6 7 8 9 10 10 11 RESET_V 11 RESET_V 12 12 13 START 13 START 14 14 15 15 16 16 17 17 18 18 19 19 20 20 LIST p=16f877a LIST p=16f877a #include #include cblock 0x020 cblock 0x020 COUNTERL COUNTERL COUNTERH COUNTERH endc endc org org goto goto 0x0000 0x0000 START START clrf PORTB clrf PORTB bsf STATUS,RP0 bsf STATUS,RP0 movlw b’11110000' movlw b’11110000' movwf TRISB movwf TRISB bcf STATUS,RP0 bcf STATUS,RP0 st st Instruction} {1 Instruction} {1 {2nd Instruction} {2nd Instruction} {3rd Instruction} {3rd Instruction} ;Reset Vector ;Reset Vector ;Clear PORTB output latches ;Clear PORTB output latches ;Switch to bank ;Switch to bank ;Load value to make lower bits outputs ;Load value to make lower bits outputs ;Move value to TRISB ;Move value to TRISB ;Switch to bank ;Switch to bank ;Clear index into table ;Clear index into table ;Load W with high byte of TABLE address ;Load W with high byte of TABLE address ;Move W to PCLATH ;Move W to PCLATH ;CONTINUED ON NEXT SLIDE ;CONTINUED ON NEXT SLIDE © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 86 Lab 5: Template – Part © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 87 Lab 5: Template – Part © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 88 Lab 5: Solution – Part Lab 5: Lookup Table Lab 5: Lookup Table 1 2 3 4 5 6 7 8 9 10 10 11 RESET_V 11 RESET_V 12 12 13 START 13 START 14 14 15 15 16 16 17 17 18 18 19 19 20 20 LIST p=16f877a LIST p=16f877a #include #include cblock 0x020 cblock 0x020 COUNTERL COUNTERL COUNTERH COUNTERH endc endc org org goto goto 0x0000 0x0000 START START ;Reset Vector ;Reset Vector clrf clrf bsf bsf movlw movlw movwf movwf bcf bcf clrf clrf movlw movlw movwf movwf PORTB PORTB STATUS,RP0 STATUS,RP0 b’11110000' b’11110000' TRISB TRISB STATUS,RP0 STATUS,RP0 INDEX INDEX HIGH TABLE HIGH TABLE PCLATH PCLATH ;Clear PORTB output latches ;Clear PORTB output latches ;Switch to bank ;Switch to bank ;Load value to make lower bits outputs ;Load value to make lower bits outputs ;Move value to TRISB ;Move value to TRISB ;Switch to bank ;Switch to bank ;Clear index into table ;Clear index into table ;Load W with high byte of TABLE address ;Load W with high byte of TABLE address ;Move W to PCLATH ;Move W to PCLATH ;CONTINUED ON NEXT SLIDE ;CONTINUED ON NEXT SLIDE © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 89 Lab 5: Solution – Part © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 90 Lab 5: Solution – Part © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 91 Lab 5: Results You have learned: − How to implement a lookup table − How to retrieve data from a lookup table − How to call a subroutine on another page − How to perform a computed goto © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 92 Summary PIC16 Architecture PIC16 Instruction Set PIC16 Memory Organization Simple Programming Techniques © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 93 References PIC® MCU Mid-Range Family Reference Manual (DS33023A) Microchip Technology Programming and Customizing PICmicro Microcontrollers by Myke Predko Design with PIC® Microcontrollers by John B Peatman © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 94 References 123 PIC® Microcontroller Experiments for the Evil Genius by Myke Predko © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 95 Thank You © 2005 Microchip Technology Incorporated All Rights Reserved © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 96 Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KeeLoq, KeeLoq logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A and other countries AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A and other countries SQTP is a service mark of Microchip Technology Incorporated in the U.S.A All other trademarks mentioned herein are property of their respective companies © 2007 Microchip Technology Incorporated All Rights Reserved 11002 GS2 Slide 97 ... f,d f,d Inclusive OR W with ff Inclusive OR W with Move ff Move goto goto iorlw iorlw k k k k Go to address Go to address Inclusive OR literal with W Inclusive OR literal with W ff Move W to... literal Subtract W from literal f,d f,d Exclusive OR W with ff Exclusive OR W with xorlw xorlw k k Exclusive OR literal with W Exclusive OR literal with W © 2007 Microchip Technology Incorporated All... PCL Slide 36 PC Relative Addressing: Lookup Table PIC® MCU ORG 0x0020 ;Page movlw HIGH SevenSegDecode Example: Use a lookup movwf PCLATH table with relative movlw addressing to retrieve the call