VFP Programmer’s Model ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. C2-19 2.6 System registers A VFP implementation contains three or more special-purpose system registers: •The Floating-point System ID register (FPSID) is a read-only register whose value indicates which VFP implementation is being used. See FPSID on page C2-20 for details. •The Floating-point Status and Control register (FPSCR) is a read/write register which provides all user-level status and control of the floating-point system. See FPSCR on page C2-21 for details of the FPSCR. •The Floating-point Exception register (FPEXC) is a read/write register, two bits of which provide system-level status and control. The remaining bits of this register can be used to communicate exception information between the hardware and software components of the implementation, in an IMPLEMENTATION DEFINED manner. See FPEXC on page C2-24 for details of the FPEXC. • Individual VFP implementations can define and use further system registers for the purpose of communicating between the hardware and software components of the implementation. All such registers are IMPLEMENTATION DEFINED. They may not be used outside the implementation itself, except as described in implementation-specific documentation. Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. VFP Programmer’s Model C2-20 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E 2.6.1 FPSID The FPSID has the following format: Bits[31:24] Contain an implementor code. The following code is defined: 0x41 = A (ARM Ltd) All other values of the implementor code are reserved by ARM Ltd. Bit[23] Contains 0 if the implementation contains a hardware coprocessor, or 1 if it is a pure software implementation. Bits[22:21] Indicate which FSTMX/FLDMX format is used (see Storing and reloading values of unknown precision on page C2-15): 0b00 Indicates standard format 1. 0b01 Indicates standard format 2. 0b10 Is reserved. 0b11 Indicates a non-standard format. Bit[20] Contains 0 if the implementation supports both single precision and double precision (a D variant of the architecture), or 1 if it only supports single precision (a non-D variant). Bits[19:16] Contain the architecture version number, encoded as follows: 0b0000 indicates VFPv1. All other values of this architecture version code are reserved by ARM Ltd. Bits[15:8] Contain an IMPLEMENTATION DEFINED representation of the primary part number of the VFP implementation. Bits[7:4] Contain an IMPLEMENTATION DEFINED variant number. This is typically used to distinguish variants of the same primary part. For example, two variants of the same VFP implementation might have hardware coprocessor interfaces designed to work with different ARM processors. Bits[3:0] Contain the IMPLEMENTATION DEFINED revision number of the part. The FPSID register is read-only, and can be accessed in both privileged and unprivileged modes. Attempts to write the FPSID register are ignored. 31 24 23 22 21 20 19 16 15 8 7 4 3 0 implementor SW format SNG architecture part number variant revision Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. VFP Programmer’s Model ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. C2-21 2.6.2 FPSCR The FPSCR has the following format: All of these bits can be read and written, and can be accessed in both privileged and unprivileged modes. Note All bits described as DNM (Do Not Modify) in the diagram are reserved for future expansion. They are initialized to zeros. Non-initialization code must use read/modify/write techniques when handling the FPSCR, in order to ensure that these bits are not modified. Failure to observe this rule can result in code which has unexpected side effects on future systems. The FPSCR bits are described in the following subsections. Condition flags Bits[31:28] of the FPSCR contain the results of the most recent floating-point comparison: N Is 1 if the comparison produced a less than result Z Is 1 if the comparison produced an equal result C Is 1 if the comparison produced an equal, greater than or unordered result V Is 1 if the comparison produced an unordered result. These condition flags do not directly affect conditional execution, either of ARM instructions or of VFP instructions. A comparison instruction is normally followed by an FMSTAT instruction. This transfers the FPSCR condition flags to the ARM CPSR flags, after which they can affect conditional execution. For more details of how comparisons are performed, see Comparison instructions on page C3-6. Flush-to-zero mode control Bit[24] of the FPSCR is the FZ bit and controls flush-to-zero mode. See Flush-to-zero mode on page C2-13 for details of this processing mode. FZ == 0 Flush-to-zero mode is disabled and the behavior of the floating-point system is fully compliant with the IEEE 754 standard. FZ == 1 Flush-to-zero mode is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N Z C V DNM FZRMODESTRIDE D N M LEN DNM I X E U F E O F E D Z E I O E DNM I X C U F C O F C D Z C I O C Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. VFP Programmer’s Model C2-22 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E Rounding mode control Bits[23:22] of the FPSCR select the current rounding mode. This rounding mode is used for almost all floating-point instructions. The only floating-point instructions which do not use it are FTOSIZD, FTOSIZS, FTOUIZD and FTOUIZS, which always use RZ mode. The rounding modes are encoded as follows: 0b00 Indicates Round to Nearest (RN) mode 0b01 Indicates Round towards Plus Infinity (RP) mode 0b10 Indicates Round towards Minus Infinity (RM) mode 0b11 Indicates Round towards Zero (RZ) mode. See Rounding on page C2-9 for details of the rounding modes. Vector length/stride control The LEN field (bits[18:16]) of the FPSCR controls the vector length for VFP instructions that operate on short vectors, that is, how many registers are in a vector operand. Similarly, the STRIDE field (bits[21:20]) controls the vector stride, that is, how far apart the registers in a vector lie in the register bank. The allowed combinations of LEN and STRIDE are shown in Table 2-2 on page C2-23. All other combinations of LEN and STRIDE produce UNPREDICTABLE results. The combination LEN == 0b000, STRIDE == 0b00 is sometimes called scalar mode. When it is in effect, all arithmetic instructions specify simple scalar operations. Otherwise, most arithmetic instructions specify a scalar operation if their destination lies in the range S0-S7 (for single precision) or D0-D3 (for double precision). The full rules used to determine which operands are vectors and full details of how vector operands are specified can be found in Chapter C5 VFP Addressing Modes and in the individual instruction descriptions. The rules for vector operands do not allow the same register to appear twice or more in a vector. The allowed LEN/STRIDE combinations listed in Table 2-2 never cause this to happen for single-precision instructions, so single-precision scalar and vector instructions can be used with all of these LEN/STRIDE combinations. For double-precision vector instructions, some of the allowed LEN/STRIDE combinations would cause the same register to appear twice in a vector. If a double-precision vector instruction is executed with such a LEN/STRIDE combination in effect, the instruction is UNPREDICTABLE. The last column of Table 2-2 indicates which LEN/STRIDE combinations this applies to. Double-precision scalar instructions work normally with all of the allowed LEN/STRIDE combinations. Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. VFP Programmer’s Model ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. C2-23 Exception status and control Bits[12:8] and bits[4:0] of the FPSCR are the trap enable bits and cumulative exception bits respectively for the five types of exception. For details of what these do, see Floating-point exceptions on page C2-10. Table 2-3 shows which bits are associated with each exception. Table 2-2 Vector length/stride combinations LEN STRIDE Vector length Vector stride Double-precision vector instructions 0b000 0b00 1 - All instructions are scalar 0b001 0b00 2 1 Work normally 0b001 0b11 2 2 Work normally 0b010 0b00 3 1 Work normally 0b010 0b11 3 2 UNPREDICTABLE 0b011 0b00 4 1 Work normally 0b011 0b11 4 2 UNPREDICTABLE 0b100 0b00 5 1 UNPREDICTABLE 0b101 0b00 6 1 UNPREDICTABLE 0b110 0b00 7 1 UNPREDICTABLE 0b111 0b00 8 1 UNPREDICTABLE Table 2-3 Exception status and control bits Exception type Trap enable bit Cumulative exception bit Invalid Operation IOE (bit[8]) IOC (bit[0]) Division by Zero DZE (bit[9]) DZC (bit[1]) Overflow OFE (bit[10]) OFC (bit[2]) Underflow UFE (bit[11]) UFC (bit[3]) Inexact IXE (bit[12]) IXC (bit[4]) Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. VFP Programmer’s Model C2-24 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E 2.6.3 FPEXC The FPEXC register has the following format: This register can only be accessed in privileged modes. The EX bit The EX bit (bit[31]) is a status bit which specifies how much information needs to be saved to record the state of the floating-point system. It can be read on all VFP implementations, and is mainly of interest to process swap code. EX == 0 In this case, the only significant state in the floating-point system is the contents of the architecturally defined writable registers, that is, of the general-purpose registers, FPSCR and FPEXC. If EX == 0 when a process is swapped out, only these registers need to be saved, or reloaded when the process is swapped back in. Also, no unexpected ARM exceptions (such as an undefined instruction exception to process a pending exception in the hardware) must occur during the saving and reloading of the registers. EX == 1 Here, there is additional IMPLEMENTATION DEFINED significant state in the floating-point system which process swap code needs to handle. This typically occurs when VFP hardware requires support code assistance to handle a potential exception, and one or more of the additional hardware system registers contains details of the potential exception. (Some implementations describe this by saying that the hardware is in an exceptional state.) The actions required to swap a process out when EX == 1 and to swap such a process back in are IMPLEMENTATION DEFINED. The behavior of the EX bit when FPEXC is written is IMPLEMENTATION DEFINED, subject to the constraint that writing a 0 to the EX bit must be a legitimate action. Otherwise, the process swap technique described above for the case EX == 0 cannot work. The EN bit The EN bit (bit[30]) is a global enable bit, and can be both read and written. EN == 1 In this case, the floating-point system is enabled and operates normally. EN == 0 Here, the floating-point system is disabled. In this state, all VFP instructions are treated as undefined instructions when executed in an unprivileged ARM processor mode, and all except the following are treated as undefined instructions when executed in a privileged ARM processor mode: •an FMXR to the FPEXC or FPSID register •an FMRX from the FPEXC or FPSID register. 31 30 29 0 EXEN IMPLEMENTATION DEFINED Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. VFP Programmer’s Model ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. C2-25 Note An FMXR to the FPSCR or an FMRX from the FPSCR is treated as an undefined instruction when EN == 0. If a VFP implementation contains additional system registers besides FPSID, FPSCR, and FPEXC, the behavior of FMXR instructions to them and FMRX instructions from them is IMPLEMENTATION DEFINED. Other bits All bits of the FPSCR other than the EX and EN bits are IMPLEMENTATION DEFINED, including whether they are readable, writable or both. They are typically used in hardware implementations for communicating exception information between the VFP hardware and its support code. A constraint on how these bits are defined is that when the EX bit is 0, it must be possible to save and reload all significant state in the floating-point system by saving and reloading only the VFP general-purpose registers, FPSCR and FPEXC. Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. VFP Programmer’s Model C2-26 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E 2.7 Reset behavior and initialization When a hardware VFP implementation is reset, the FPEXC EN bit is reset to 0. The behavior of all other VFP registers and of the remaining bits of FPEXC on hardware reset is IMPLEMENTATION DEFINED. When the software component of a VFP implementation has finished initializing, the following are true: • The FPEXC EN bit is set to 1 • The FPEXC EX bit is set to 0 • All bits of the FPSCR are set to 0, with the possible exception of the condition code flags in some cases. This selects the following settings: — normal IEEE 754 mode, not flush-to-zero mode —the Round to Nearest rounding mode — scalar mode (vector length 1) — all exceptions are untrapped, and their cumulative status bits indicate that no exceptions of that type have been detected yet. It is IMPLEMENTATION DEFINED whether the VFP general-purpose registers and the FPSCR condition flags are initialized, and if so, what values they are initialized to. Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. C3-1 Chapter C3 VFP Instruction Set Overview This chapter gives an overview of the VFP instruction set. It contains the following sections: • Data-processing instructions on page C3-2 • Load and Store instructions on page C3-13 • Register transfer instructions on page C3-17. Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. VFP Instruction Set Overview C3-2 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E 3.1 Data-processing instructions All VFP data-processing instructions are CDP instructions for coprocessors 10 or 11, with the following format: p, q, r, s These bits collectively form the instruction’s primary opcode. See Table 3-1 for the assignment of these opcodes. When all of p, q, r and s are 1, the instruction is a two-operand extension instruction, with an extension opcode specified by the Fn and N bits. Fd and D These bits normally specify the destination register of the instruction: • For a single-precision instruction, Fd holds the top 4 bits of the register number and D holds the bottom bit. • For a double-precision instruction, Fd holds the register number and D must be 0. If D is 1 in a double-precision instruction, the instruction is UNDEFINED. For multiply-accumulate instructions, this register is also the accumulate operand register. For comparison instructions, it is the first operand register rather than a destination register. Fn and N These bits normally specify the first operand register of the instruction. • For a single-precision instruction, Fn holds the top 4 bits of the register number and N holds the bottom bit. • For a double-precision instruction, Fn holds the register number and N must be 0. However, if p, q, r and s are all 1, the instruction is an extension instruction, and the Fn and N fields form an extension opcode instead of specifying a register. See Table 3-2 for the assignment of these extension opcodes. If N is 1 in a double-precision non-extension instruction, the instruction is UNDEFINED. Fm and M These bits specify the second operand register of the instruction, or the only operand register for some extension instructions. • For a single-precision instruction, Fm holds the top 4 bits of the register number and M holds the bottom bit. • For a double-precision instruction, Fm holds the register number and M must be 0. If M is 1 in a double-precision instruction, the instruction is UNDEFINED. cp_num If cp_num is 0b1010 (coprocessor number 10), the instruction is a single-precision instruction. If cp_num is 0b1011 (coprocessor number 11), the instruction is a double-precision instruction. For the instructions that convert between single-precision and double-precision (FCVTDS and FCVTSD), cp_num matches the source precision. 3130292827 242322212019 1615 1211 876543 0 cond 1110pDqr Fn Fd cp_num NsM0 Fm Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark. [...]... flush-to-zero mode changes) Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E Chapter C4 VFP Instructions This chapter describes the syntax and usage of each VFP instruction, in the section: • ARM DDI 0100E Alphabetical list of VFP instructions on page C4-2 Copyright © 1996-2000 ARM Limited All rights reserved Please... language condition Instruction type ARM condition == = FCMP EQ != ? FCMP NE > > FCMPE GT >= >= FCMPE GE < < FCMPE MI or CC = FCMP PL or CS ?< C3-8 IEEE predicate FCMP LT Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instruction... behavior with regard to Invalid Operation exceptions • Which ARM condition is to be used This is not always obvious For example, a standard < comparison on floating-point numbers must use the ARM MI or LO/CC condition, not LT, despite the fact that floating-point comparisons are always signed If this column contains two conditions, no single ARM condition can be used to test the predicate Each of these... used to test the predicate Each of these predicates can be tested using a suitable combination of two ARM conditions, in several different ways For example, the predicate can be tested by checking that NE and VC are both true, or that either of GT and MI is true ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark... particular, the VFP architecture requires: • • C3-14 a load or store of a signaling NaN not to raise an Invalid Operation exception, nor to change the signaling NaN into a quiet NaN a load or store of a denormalized number in flush-to-zero mode not to change it into +0 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E... register, the instruction is UNDEFINED Rd This specifies the ARM register involved in the transfer If Rd is R15, the behavior is as specified for the generic ARM instruction: • • cp_num For an MCR instruction (L == 0), the instruction is UNPREDICTABLE For an MRC instruction (L == 1), the top 4 bits of the value transferred are placed in the ARM condition code flags, and the remaining 28 bits are discarded... FMSTAT instruction uses this behavior to transfer comparison results to the ARM If cp_num is 0b1010 (coprocessor number 10), the instruction is a single-precision or system register transfer If cp_num is 0b1011 (coprocessor number 11), the instruction is a double-precision register transfer ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com... IMPLEMENTATION DEFINED Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instruction Set Overview 3.3.1 General-purpose register transfer instructions The FMRS instruction allows a single-precision value or a 32-bit integer in a single-precision register to be transferred to an ARM register, and the FMSR instruction... of NaN handling and flush-to-zero mode In particular, the VFP architecture requires: • a load or store of a signaling NaN not to raise an Invalid Operation exception, nor to change the signaling NaN into a quiet NaN • a load or store of a denormalized number in flush-to-zero mode not to change it into +0 ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge... unordered if either or both of them are NaNs Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instruction Set Overview Note If both values are the same NaN, the comparison result is unordered, not equal If an exact bit-by-bit comparison is wanted, the ARM comparison instructions must be used rather than VFP comparison . VFP Programmer’s Model ARM DDI 0100E Copyright © 1996-2000 ARM Limited. All rights reserved. C2-19 2.6 System registers A. watermark. VFP Programmer’s Model C2-20 Copyright © 1996-2000 ARM Limited. All rights reserved. ARM DDI 0100E 2.6.1 FPSID The FPSID has the following format: Bits[31:24]