Dynamic reconfigurable architectures and transparent optimization techniques

... Dynamic Reconfigurable Architectures and Transparent Optimization Techniques Antonio Carlos Schneider Beck Fl Luigi Carro Dynamic Reconfigurable Architectures and Transparent Optimization Techniques ... two techniques related to dynamic optimization are presented in details: dynamic reuse and binary translation In Chap 5, studies that already use both re...

Ngày tải lên: 08/03/2016, 11:22

... Dynamic and Adaptive Techniques in SRAM Design 249 John J Wuu 11 .1 Introduction 249 11 .2 Read and Write Margins 250 11 .2 .1 Voltage Optimization Techniques 2 51 11. 2 .1. 1 Column ... 252 11 .2 .1. 2 Row Voltage Optimization 255 11 .2.2 Timing Control 257 11 .3 Array Power Reduction 259 11 .3 .1 Sleep Types 259 11 .3 .1. 1 Active Sleep .260 11 .3 .1. 2 ... 267 1...

Ngày tải lên: 06/08/2014, 01:21

... factor for adaptive scaling to lower supply voltage 1. 5 1. 0 Very convenient for a nominal supply voltage of 1. 1V! Temperature = 12 5C 0.5 Temperature = -40C 0.0 0.4 0.5 0.6 0.7 0.8 0.9 1. 1 1. 2 1. 3 1. 4 ... 20 07 [7] H Su, F Liu, A Devgan, E Acar, S Nassif, “Full Chip Leakage Estimation Considering Power Supply and Temperature Variations,” International 22 [8] [9] [10...

Ngày tải lên: 06/08/2014, 01:21

... operating condition 1E-9 Leakage current in [A/μ m] Leakage current in [A/μ m] 10 0E -12 10 E -12 1E -12 10 0E -15 10 0E -12 10 E -12 1E -12 10 0E -15 10 E -15 10 E -15 0.4 0.5 0.6 0.7 0.8 0.9 1. 1 1. 2 1. 3 1. 4 -50 -25 ... 35 0E+6 1. 1 1. 4 1. 5 1. 6 1. 7 1. 8 1. 9 30 0E+6 Frequency [Hz] 1. 3 N-well bias voltage [V] 1. 2 250E+6 200E+6 15 0E+6 10 0E+6 Nominal VDD...

Ngày tải lên: 06/08/2014, 01:21

... 3.0 1. 5 2.0 2.5 3.0 1. 01 1.02 1. 03 1. 05 1. 06 1. 12 1. 03 1. 04 1. 07 1. 13 1. 15 1. 33 1. 05 1. 08 1. 13 1. 24 1. 27 1. 69 1. 08 1. 13 1. 20 1. 41 1 .40 2.26 1. 5 2.0 2.5 3.0 1. 03 1. 06 1. 05 1. 10 1. 09 1. 17 1. 06 1. 12 ... 1. 12 1. 11 1.22 1. 18 1. 38 1. 09 1. 19 1. 17 1. 36 1. 28 1. 63 1. 13 1. 26 1. 24 1. 52 1. 39 1. 94 (b) fm =...

Ngày tải lên: 06/08/2014, 01:21

... Normalized leakage Die count 10 0% 80% 60% 40 % 20% 0% Accepted dies: NBB 81 110 C 1. 1V ABB ABB σ/μ=0.69% 0.925 NBB σ/μ =4 .1% 1. 075 1. 15 Normalized frequency 1. 225 Figure 4. 6 Measurement results: comparison ... lower V CC for same frequency 1. 28V 2.5 Tota power (mW) Frequency (GHz) 4. 05GHz 5% frequency increase 1. 1 1. 2 1. 3 Vcc (V) 1. 5 LBG Switching 1. 35V 1. 4...

Ngày tải lên: 06/08/2014, 01:21

... (mV) Fmax (MHz) 17 00 Compensated Fmax 16 50 16 00 Aged Fmax (0.9V) 15 50 15 00 12 0 10 0 0.9V 80 60 1. 2V 40 20 0 50 10 0 15 0 200 Aging Time (Hours) Figure 4 .18 Aging compensation using dynamic body bias ... off for a large decrease in the other Chapter Adaptive Supply Voltage Delivery for U-DVS Systems 10 1 18 14 12 0 .1 10 0.2 0.2 Number of Stages (N) 16 0 .15 0...

Ngày tải lên: 06/08/2014, 01:21

... A Wang, S Naffziger (eds.), Adaptive Techniques for Dynamic Processor Optimization, DOI: 10 .10 07/ 978 -0-3 87- 76 472 -6_6, © Springer Science+Business Media, LLC 2008 12 4 Lawrence T Clark, Franco ... vibrations as a power source for wireless sensor nodes,” Computer Communications, vol 26, no 11 , pp 11 31 11 44, July 2003 [6] A Wang and A Chandrakasan, “A 18 0-mV Sub-th...

Ngày tải lên: 06/08/2014, 01:21

... Vol 36, No 11 , pp 4 98 506, November 20 01 [2] Montonarro, J, et al., “A 16 0 MHz, 32b 0.5W CMOS RISC microprocessor,” IEEE Journal of Solid-state Circuits, vol 31, pp 17 03 17 14, November 19 96 [3] ... DLL and PLL based on selfbiased techniques, ” IEEE Journal of Solid-State Circuits, Vol 31, No 11 , pp 17 23 17 32, November 19 96 Chapter Sensors for Critical Path Monitoring...

Ngày tải lên: 06/08/2014, 01:21

... F 1. 5 1. 3 1 .2 1. 1 0.9 0.8 Nand Wire PG Nor Add 1. 4 Normalized Period Normalized Period 1. 4 Low Frequency, F/3 1. 5 Nand Wire PG Nor Add 16 1 1. 3 1 .2 1. 1 0.9 0.8 0.9 1. 0 VDD 1. 1 1 .2 0.8 0.8 0.9 1. 0 ... path, for this analysis, it is simpler and sufficient to analyze the path as a simple buffered delay line Vi Vo w1(b1 +1) Vi Rd/w1 w1(b1 +1) Cd L1 w2(b2 +1)...

Ngày tải lên: 06/08/2014, 01:21

... Acar, and S Nassif, “Full Chip LeakageEstimation Considering Power Supply and Temperature Variations,” ISLPED, 25 27 Aug 20 03, pp 78–83 Chapter Architectural Techniques for Adaptive Computing 1 ,2 ... Performance,” DAC, 5–9 June 20 00, pp 1 72 175 [22 ] S Naffziger, B Stackhouse, T Grutkowski, D Josephson, J Desai, and M Horowitz, “The Implementation of a 2- Core, Multi-Thr...

Ngày tải lên: 06/08/2014, 01:21

... achieved 2. 0 16 12 1.68 10 1.66 1.64 1. 62 1.60 1.58 25 .2 25 .3 25 .4 Time (s) 25 .5 Low to High Error-rate phase transition 1.70 1.5 1.68 1.66 1.0 1.64 1. 62 0.5 1.60 1.58 0.0 29 .4 29 .5 29 .6 Time (s) 29 .7 ... incubation, drift and threshold in single-damascene copper interconnects,” IEEE 20 02 International Interconnect Technology Conference, 20 02, pp 127 – 129 , 3...

Ngày tải lên: 06/08/2014, 01:21

... B 5 12 B 1 0 24 B 20 48 B Wordlines 32 64 128 25 6 Bitlines 64 64 64 64 Effective critical paths 105 195 41 5 730 Chapter Variability-Aware Frequency Scaling in Multi-Clock Processors 21 5 Figure 9.3 ... Multi-Clock Processors 22 7 Architectural Support for Programming Languages and Operating Systems, 20 04, pp 24 8 25 9 [17] W Zhao and Y Cao, “New Generation of Predictiv...

Ngày tải lên: 06/08/2014, 01:21