Estimation of cosmic ray induced background and a fpga based data compression algorithm for deeme experiment

Estimation of Cosmic Ray Induced Background and a FPGA-Based Data Compression Algorithm for DeeMe Experiment Nguyen Minh Truong Department of Physics Osaka University This dissertation is submitted for the degree of Doctor of Science Graduate School of Science May 2017 I would like to dedicate this thesis to my loving parents Without their love, support and putting me through the best education possible, I wouldn’t have been able to get to this stage To my wife, for her unending support and love, I wouldn’t have gotten through this doctorate if it wasn’t for her Declaration I hereby declare that the contents of this thesis are original except where specific reference is made to the work of others, and they have not been submitted in whole or in part for any other degree or any other university This thesis is my own work and contains nothing which is the outcome of work done in collaboration with others, except as specified in the text and Acknowledgements Nguyen Minh Truong May 2017 Acknowledgements First of all, I would like to thank my advisors Prof Masaharu Aoki and Prof Yoshitaka Kuno for the continuous support of my doctoral study and related research Without Prof Kuno’s help, I can not study in Osaka University Studying in Kuno-lab years, from master course until now, I really thank his favors I also learn a lot from him By giving clear answers for my questions, he helps me open my mind in the best ways Prof Aoki is my main supervisor in doctoral course, I learn from him a lot of knowledge, from the basic knowledge in physics, computer and electronics areas I realy admire him for his patience I can not imagine how much time he spend to teach me many things, from basic one to the depth knowledge Besides my advisors, I would like to thank the rest of my thesis committee: Prof Masaharu Nomachi, Prof Tadafumi Kishimoto, and Prof Takashi Nakano By giving the insightful comments and encouragement, and also the hard questions, they help me widen my research from various perspectives So, I can complete my thesis in the best ways My sincere thanks also goes to Prof Youichi Igarashi, Prof Yoshihiro Seiya, Dr Hiroaki Natori, Dr Yohei Nakatsugawa and DeeMe collaborator, who provided me an opportunity to join DeeMe group Without their precious support, I can not finish my research I thank my fellow labmates, for friendship and for all the fun we have had in the last five years I realy thank my friends in Kuno-lab, with their help in Japanese whenever I have problem with Japanese communication I also thank my friends from Osaka City Univeristy, for their helps in DeeMe beam time, for their comments in meeting and for all thing we have in DeeMe group I am also thankfull to Kuno-lab secretaries, Ms Miki, Ms Komai, and Ms Imoto They help me a lot during I study in Osaka Univeristy I would like to thank the Matsuda Yosahichi Memorial scholarship, for their financial support for my study time in Japan Last but not the least, I would like to thank my family: my parents and my brother for supporting me spiritually throughout writing this thesis and my life And huge thanks, love to my wife, a sky of my life Abstract DeeMe experiment which is an experiment searching for muon to electron conversion (µ-e conversion) will be conducted at J-PARC Materials and Life Science Experimental Facility (MLF) The µ-e conversion in the nuclear field, µ − +N→ e− + N, is one of chargedLepton Flavor Violation (cLFV) processes This process is forbidden in the Standard Model (SM) of particle physics However in the prediction of numerous theoretical models beyond the SM, this process will happen at a level of few orders of magnitude below upper limits given by previous experiments The current upper limits of the branching ratio on the µ-e conversion process are BR(µ − +Au→ e− +Au) < × 10−13 given by SINDRUM II experiment; BR(à +Ti e +Ti) < 4.3 ì 10−12 and 4.6 × 10−12 given by SINDRUM II and the experiment at TRIUMF, respectively DeeMe experiment will use the pulsed proton beam from Rapid Cycling Synchrotron at J-PARC Electrons from µ-e conversion may be produced inside a production target and they will be transported to a spectrometer by a secondary beamline The momenta of electrons will be measured by the spectrometer DeeMe experiment has a potential to reach a single event sensitivity (SES) at a level of 10−15 The physics run will start to take data in around 2016−2017 when the construction of beamline at MLF has completed In order to achieve the SES written above, it is very important to understand and control potential backgrounds Cosmic ray induced background is one of potentially backgrounds in DeeMe experiment A Monte-Carlo study has performed to estimate its rate Based on this result, a data acquisition (DAQ) system has been developed so that it is not only used to collect the detector signals from the spectromenter but also used to monitor the cosmic ray induced background In this thesis, the Monte-Carlo study to estimate the cosmic ray induced background and the DAQ system that can collect the detecotor signals and monitor the backgrounds are reported Table of contents List of figures xv List of tables xix Introduction 1.1 Overview 1.2 Muon and Lepton Numbers 1.3 µ-e Conversion Process 1.4 How to Search for µ-e Conversion 1.5 µ-e Conversion Experiment DeeMe experiment at J-PARC 2.1 Pulsed Proton Beam 2.2 Muon Production Target 2.3 H-line at MLF 2.4 Multi-Wire Proportional Chamber 2.5 Single Event Sensitivity Background Estimation by Monte-Carlo Calculation 3.1 Overview 3.2 Cosmic Ray Induced Background 3.2.1 Cosmic Ray Source 3.2.2 Cosmic Ray Induced Background in DeeMe Experiment 3.3 Monte Carlo Estimation 3.3.1 Coordinates Definition 3.3.2 Major Background Source Positions along H-line 3.3.3 Muon Interaction and Electron Production Mechanism 3.3.4 Electron Production Models 3.3.5 Electrons Induced at Horizontal Direction 1 11 12 12 15 18 20 23 23 26 26 27 28 29 30 37 40 42 xii Table of contents 3.4 3.3.6 Event Generation 3.3.7 Analysis and Event Cut 3.3.8 Cosmic Ray Induced Background 3.3.9 Systematic Errors Monitoring the Backgrounds 3.4.1 Concept 3.4.2 Significance with Likelihood method FPGA-Based Data Compressor 4.1 Overview 4.2 FADC board 4.2.1 Hardware of the FADC Board 4.2.2 Issue of the FADC Board 4.3 Data Compression 4.3.1 Lossy Data Compression 4.3.2 Lossless Data Compression 4.4 Optimum Compression Method for DeeMe Experiment 4.5 Adaptive Delta Compression 4.5.1 Adaptive Delta Compression Algorithm 4.5.2 Data Format for Adaptive Delta Compression in FADC Board 4.5.3 Design of the Delta Compressor Module 4.5.4 Advantage of Delta Compressor Module 4.6 Implementation to the FADC Board 4.6.1 Design of the Firmware 4.6.2 Data Format 4.6.3 Handshake Protocol between Modules 4.6.4 Advantage of the New Firmware 4.7 Self Trigger 4.8 Single FADC Board Performance Test 4.8.1 Test the Compressor in FPGA 4.8.2 Test Handshake Protocol 4.8.3 Test the Connection Between FADC Chip and FPGA Chip 4.8.4 Test Performance of New Firmware and Compressor 4.9 Multiple-Board Performance Test 4.9.1 Network Congestion 4.9.2 Head-of-Line Blocking Problem 4.9.3 High Performance Network Switch 46 47 51 52 53 53 54 57 57 58 58 59 61 61 62 68 70 70 74 76 80 81 81 84 87 88 89 91 91 93 94 96 97 97 98 99 Table of contents xiii 103 Summary and Discussion References 105 List of figures 1.1 1.2 1.3 1.4 1.5 µ-e conversion with photonic mechanism and non-photonics mechanism µ ± → e± γ and µ ± → e± e+ e− process with photonic mechanism The historical search of cLFV [18] Setup of SINDRUM II experiment [20] SINDRUM II experiment result [20] 8 2.1 2.2 2.3 The concept of DeeMe experiment Time structure of pulsed proton beam from RCS The ratio between the µ-e conversion branching ratio and the µ-e conversion braching ratio on Al target is plotted as a function of atomic number Z [24] Lifetime of negative muon in material is plotted as a function of atomic number Z [16] The H-line and spectrometer in DeeMe experiment The H-line beam envelope The acceptance of H-line [29] The concept of the MWPC Signal of MWPC in beam test at MLF November 2015 11 12 2.4 2.5 2.6 2.7 2.8 2.9 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 Momentum distribution of electrons produced by 3-GeV protons hitting a Graphite target Time structure of charged particles at J-PARC MLF Cosmic ray flux from various experiments [36] Cosmic ray induced background in DeeMe experiment Coordinate definition for cosmic ray induced background study Angles definition for cosmic ray induced background study The concept of major background source position study Number of positron hitting virtual detector as a function of x position along the beam line 13 13 16 17 17 19 20 24 24 26 28 29 30 31 31 xvi List of figures 3.9 3.28 3.29 3.30 3.31 Phase space of electron and positron beam at target, a−b: phase space of electron beam emitted from target, c−d: phase space of positron beam emitted from MWPC4 Phase space of electron and positron beam at HQ beam duct, a−b: phase space of electron beam emitted from target, c−d: phase space of positron beam emitted from MWPC4 Positron distribution in HQ beam duct virtual detector Positron distribution in production target Electron stopping power in iron [39] Geometrical configuration of the G4beamline calculation to study the number of electrons induced by muons in material Number of electrons induced versus the iron thickness The θe− distribution of electron with momentum from 80 MeV/c to 120 MeV/c in different muon energies The electron production models Concept to study models with cosmic rays muon Cosmic muon source in G4beamline The θµ distribution of cosmic ray muon and muon GeV The θe− distribution of electron induced from different muon theta hitting the beam duct model The θe− distribution of electron induced from different muon theta hitting the target model PDF of beam duct PDF of target Example putting electron in H-line at HQ Concept of background rejection by track fitting Phase-space y’ versus y of electrons induced background from the HQ beam duct (blue color) and electrons µ-e signal from the target (red color) at plan X0 Momentum distribution of the electron background induced at HQ beam duct Momentum distribution of the electron background induced at the target Muon lifetime and background level Concept to monitor cosmic ray induced background 4.1 4.2 4.3 A FADC board is used for recording signal waveforms from MWPC FADC board diagram Zero-suppression example 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 3.20 3.21 3.22 3.23 3.24 3.25 3.26 3.27 33 34 35 36 38 38 39 39 41 42 43 43 44 44 46 47 47 49 50 51 51 52 54 58 59 62 94 FPGA-Based Data Compressor Table 4.13 Network speed versus global busy signal Bandwidth (kbps) 1,000 10,000 20,000 30,000 40,000 50,000 100,000 4.8.3 Busy signal (ms) 5,000 4,000 3,000 ∼3,000 1,000 ∼ 2,000 18 18 Test the Connection Between FADC Chip and FPGA Chip 800 700 500 800 700 600 400 ADC channel ADC channel 600 300 500 400 300 200 50000 52000 54000 56000 58000 60000 time (ns) 200 10000 20000 30000 40000 50000 time (ns) 60000 70000 80000 90000 70000 80000 90000 (a) Pulsed signal test 1000 1000 800 600 ADC channel ADC channel 800 600 400 400 200 200 0 51000 10000 51500 52000 time (ns) 20000 52500 30000 53000 40000 50000 time (ns) 60000 (b) Square signal test Fig 4.18 Test fit input signal with the FADC board In this test, the input signal, pulse signal or square signal, is fed to any channel of FADC board Figure 4.18 shows the examples of input signal when signal is in the middle of waveform length This test is needed to test that the FADC chip and the FPGA chip have either the good clock phase assignment or not If they have not good clock phase assignment, 95 4.8 Single FADC Board Performance Test the data readout has strange shape Moreover, this test is needed to confirm that the Delta Compressor Module can work with any different delta-data mode Spike Problem of FADC Board During tests of FADC board, the problem of FADC board is detected When inserting the pulse waveform to FADC board as Figure 4.19a, the data readout has an error as Figure 4.19b The signal is sometime different with the normal signal, this problem is called spike problem of FADC board After checking all most situation, it is assumed that the spike problem comes from the output propagation delay of ADC chip According to ADC chip manual [63], there is an output propagation delay of ADC chip and it is ns Therefore, when the FADC board writes data to the memory with 100 MHz frequency, it can take the mix of data between the current and previous data Because of this mix, the data wrote to memory may have error in some bits In order to solve this spike problem, the write clock of data to FIFO is with an amount of delay in the clock of ADC chip In the firmware, the clock, which is used to write data to FIFO, is designed to shift some phases Because the maximum output propagation delay of ADC chip is ns, the maximum clock phase needed to shift is 10 × 360 = 270° To confirm the estimation is correct, the test with clock phase shifting is done and the result is shown in table 4.14 From this test, the spike problem is removed when the phase of clock is shifted from 280° to 340° (a) Pulsed signal test (b) Spike issue Fig 4.19 Spike problem of FADC board After selection the clock phase assignment between FADC chip and FPGA, the FADC board is tested by changing the timing of trigger By changing the timing of trigger, the input signal can move to the end or the begin of waveform length readout The input signal is put 96 FPGA-Based Data Compressor Table 4.14 Clock phase and spike problem Clock phase (degree) 10 45 90 180 270 280 300 320 340 350 360 Spike spike No spike spike spike spike spike No spike No spike No spike No spike spike spike to any channel of FADC board and the data readout shows the exactly waveform of input signal From this test, it is confirm that the spike problem is removed 4.8.4 Test Performance of New Firmware and Compressor This test is needed to confirm how much data is compressed and whether it is satisfied for DeeMe experiment The first test in this performance test is with the input signal which is the estimation signal of DeeMe experiment The estimation signal is produced from function generator as shown in the left hand size of Figure 4.20 and insert to any channel of FADC board This signal has the High Voltage switching region, some signals before the extraction region and some signals after the extraction region The readout waveform length of FADC board should show exactly input waveform By comparing the Figure4.20a and Figure 4.20b, the readout signal is confirmed correct Moreover, by adding the estimation signals to all channels of FADC board, the data size of estimation signal is calculated From this test, the data size for each event with 32 input signals for 32 channels is calculated as 1.44 Mbits/event By comparing the data size before and after applying the compression algorithm, the compression ratio is calculated as 2.9 This compression ratio is almost close to maximum compression ratio 3.5 as calculated in Section 4.4 The data size is reduced, thus the global busy signal of FADC board in this test is reduced to ∼18 ms This dead time is small enough for DeeMe experiment 97 4.9 Multiple-Board Performance Test (a) DeeMe estimation signal 800 600 1000 400 200 ADC value ADC value 1000 800 600 400 200 50000 0 10000 55000 20000 60000 65000 time (ns) 30000 70000 75000 40000 50000 time (ns) 60000 70000 80000 90000 (b) Signal from FADC board after compressing Fig 4.20 Test FADC board with DeeMe signal 4.9 4.9.1 Multiple-Board Performance Test Network Congestion After tested FADC board with some edge conditions and confirmed FADC board working well with new firmware and Delta Compressor module, it is needed to test the readout system with multiple FADC boards In DeeMe experiment, there are MWPCs and each MWPC has 96 channels, so that 12 FADC boards are used to read out waveform from all channels of MWPCs The data of each FADC board is up to 1.44 Mbits/events even though Delta Compressor module is used, thus the test of data transferred with multiple FADC boards is needed 98 FPGA-Based Data Compressor The first test is to review the data transmission of two FADC boards Figure 4.21 shows the setup of this test, two FADC boards and PC are connected to network switch Gigabit Switch (Lan-GSW 16P/HGW) is used in this test This network switch supports for the connection method 1000BASE-T / 100BASE-TX / 10BASE-T, thus it can transfer data up to Gbps When the DAQ system readouts data from only FADC board, the data transfers well with 100 Mbps, acceptance trigger is 25 Hz and global busy signal is 18 ms However, when the DAQ system starts to record the data from two FADC boards, the data transfer rate drops to ∼3 Mbps and the acceptance trigger drops to ∼2 events/s FADC board FADC board PC Gigabit Switch (LAN-GSW 16P/HGW) Category cable Fig 4.21 Test data transfer with two FADC boards 4.9.2 Head-of-Line Blocking Problem After checking data size of FADC board and network switch buffer size, it is assumed that the source of the data transfer rate dropping comes from Head-of-line (HoL) blocking problem Figure 4.22 is an example of HoL blocking HoL blocking is an issue in computer network, it occurs when there is a line of packets blocking by the first packet Usually, the network switch has the buffer memory for blocking data and only the first received packed is prepared to transfer forward All of packed data received afterwards can not be transferred if the first package is not transferred This issue happens when the destination output is busy The output port has contention when two or more input ports compete the data transferred As an example in Figure 4.22, the data from input competes with data of input 2, thus the output port has contention and data transferred rate drops On the other hand, the data transferred from input port to output port does not have HoL blocking problem because there is only one data transferred from input port to output port Moreover, the HoL blocking issue 4.9 Multiple-Board Performance Test 99 Fig 4.22 Head of Line Blocking problem also happens when the output buffer is full When the input data rate is larger than the output data rate, it leads to the output buffer size of network switch full and stop data transferred When two FADC boards connect to the network switch and the DAQ system readout data from these FADC boards, the data from these FADC boards competes to transfer data together Therefore, the output port to DAQ system is occupied and it is contention This leads to the HoL blocking problem of network system 4.9.3 High Performance Network Switch The network switch has HoL blocking only when it has input buffer; therefore, if the network switch has non blocking and the internal bandwidth sufficient for data transferred, the HoL blocking does not happen This architecture is known as virtual output queues (VOQ) In basic explanation, the VOQ technical prepares the separate queue for each output port, data transferred does not need to compete together to be forwarded In order to solve the problem of HoL blocking in DeeMe experiment, the network switch should be changed to another one which has supported for VOQ There are many network switches satisfying these conditions After checking performance of network switch, the Cisco Catalyts 3850 24T (WS-C3850-24T) is selected This network switch has 24 ports, each port has supported for 10/100/1000, buffer size is 6MByte/24 port and this network switch also prepares VOQ to prevent HoL blocking If 12 FADC boards are used, data transferred rate is 180 × 12 = 2.16 MBytes/event, it is still smaller than buffer size memory of WS-C3850-24T network switch which is 6MByte Therefore, the HoL blocking problem is removed by using this network switch 100 FPGA-Based Data Compressor Fig 4.23 Two VLAN set up for 12 FADC boards Moreover, it is noteworthy that FADC board has 100 Mbps TCP/IP network interface, thus 12 FADC boards transfer data with data rate up to 1.2 Gbps In order to prevent the network problem, 12 FADC boards are divided to two groups and VLAN technology is used to transfer data as Figure 4.23 By using this technique, data transferred rate of each VLAN is 0.6 Gbps, it helps transfer data smoothly After setting up VLAN for network switch, 12 FADC boards are tested with DAQ system The result of this test is shown in Figure 4.24 According to this result, maximum acceptance trigger rate for DAQ system is 50 events/s Figure 4.25 shows the screen of DAQ with 12 FADC boards In this figure, the data transferred rate is up to 50 events/s and data size of each FADC board is ∼5.2 MBytes/s 101 4.9 Multiple-Board Performance Test Acceptan trigger rate (events/s) 50 40 30 20 10 0 20 40 60 80 100 Trigger rate (Hz) Fig 4.24 Data transfer rate of 12 FADC boards Fig 4.25 DAQ screen with of 12 FADC boards Chapter Summary and Discussion Cosmic ray induced background is estimated for DeeMe experiment Cosmic ray muons can pass through the celling of MLF and hit the production target, beam ducts or magnet yokes and induce electron in horizontal axis These scattering electrons can have momentum from 80 MeV/c to 120 MeV/c in horizontal direction and they can be transferred to the spectrometer by magnetic field and induced background for DeeMe experiment As calculation in Chapter 3, the cosmic ray induced background contributes 0.025±0.015 background/year In order to achieve the 3σ significance in case of one event observed in the signal region, the monitor time window should be recoded larger than 170 µs To collect data from spectrometer, the readout boards for MWPCs are built up These readout boards will not only collect electrons signals from MWPCs to search for µ-e conversion signal, but also monitor the background for DeeMe experiment There are two ways to monitor the cosmic rays induced background for DeeMe experiment The first method is recording the long waveform of MWPC with accelerator trigger signal from MLF When receiving accelerator trigger signal, the readout board will collect data with waveform length ∼ 80 µs In this waveform length, 10 µs after extraction timing is used to search for µ-e conversion signal and 70 µs before extraction timing is used to monitor the cosmic rays induced background Because of long waveform is recorded during taking data from accelerator trigger signal, huge data is transferred from the readout board So, the dead time of readout system is increased In order to transferring huge data from FADC board but its dead time is small enough for DeeMe experiment, the readout board firmware is rewritten In the new firmware, the delta compression algorithm is applied to compress data in FPGA, the firmware is also divided to many modules for easy debugging and modifying By using compressor technology, the data is compressed with compression ratio 2.9, this helps reduce the dead time of readout board to 18 ms Therefore, FADC board can record up to 160 µs by recording two time maximum waveform length for each time 104 Summary and Discussion Moreover, to monitor the cosmic ray induced background more longer time window, the self trigger is implemented in FADC board This self trigger can automatic monitor the cosmic rays induced background when it detect any signal over the setting threshold The DAQ system is built up to take data from 12 readout boards After checking data transferred rate and data size of DAQ system, the high performance network switch is used to make private network for DeeMe experiment This network switch supports for VOQ and it has huge memory buffer size, this will help cancel HoL blocking problem of network system Moreover, VLAN technology is also applied to help transfer data smoothly The maximum readout rate of DAQ system is 50 Hz with 12 readout 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