Моноблок MSI AE2400 MS AE111 rev 3 2 схема

5 MS-AE111 Ver : 3.2 Intel (R) LGA775 E5400 Processor (65W) D C B A Intel (R) ( GMCH G41) + ICH7 Chipset 01 : BLOCK DIAGRAM 02 : PLATFORM 03 : Intel LGA775 - Signals 04 : Intel LGA775 - Power 05 : Intel LGA775 - GND 06 : Eaglelake - FSB , PCIE 07 : Eaglelake - Memory DDR2 08 : Eaglelake - VGA , MSIC 09 : Eaglelake - Power 10 : Eaglelake - GND 11 : DDR2 SODIMM 12 : DDR2 SODIMM 13 : DDR2 TREMINATION 14 : ICH7 - PCI / DMI / CPU / LAN 15 : ICH7 - LPC / ATA / USB 16 : ICH7 - Power 17 : D-SUB 18 : ENE3926D 19 : USB CONN FOR REART & IR 20 : USB CONN FOR FRONT & BT 21 : SATA CONN & ESATA CONN 22 : PCIE LAN (RTL8111DL) 23 : Mini_PCIE & Front Panel 24 : AUDIO(ALC888) 25 : TI TAS5706 AMPLIFIER 26 : WEBCAM & Touch & Fan Control 27 : SYSTEM POWER 3/5V 28 : DC_IN POWER & +12V 29 : SYSTEM POWER 3/5V 30 : GPU POWER 31 : NB_CORE , VDDR POWER 32 : VRM11- INTERSIL 6333 3PHASE 33 : PCI to USB& PCIRST 34 : SCALER(HDMI0-IN) 35 : SCALER(HDMI1-IN) 36 : SCALER(MAIN) 37 : SCALER(LVDS & INV) 38 : SCALER(POWER) 39 : ClK Generator - ICS9LPRS113A 40 : Madison-M2_Host-lvds 41 : Madison-M2_IO 42 : Madison-M2_Power 43 : Madison-M2_Power straps 44 : Madison-M2_MEM Interface 45 : Madison-M2_DDR3_B0 46 : Madison-M2_DDR3_B1 47 : Madison-M2_DDR3_A0 48 : Madison-M2_DDR3_A1 49 : EMI 50 : POWER MAP 51 : Non_Footprint for BOM 52 : GPIO & Jumper Setting 53 : Power on Sequency 54 : History D CPU: Intel Core Duo/Extreme/Quad & Pentium D Processor System Chipset: Intel G41 (North Bridge) Rev : A3 Intel ICH7 (South Bridge) Rev : A1 On Board Chipset: CLOCK : ICS9LPRS113A PCIE LAN RTL8111DL EC : ENE3926D PCI to USB : VT6212LG-1.01-RH Scalar : RTD2482D E-SATA : JMICRON JMB 362 Audio Codec : ALC888 7.1 Channel Ver : A1 BIOS : SPI- 8M C B Main Memory: DDR III * (Max 4GB) GPU: Madison & Park (M2) A MICRO-STAR INT'L CO.,LTD Title COVER Size Document Number Custom Date: Rev 31 MS-AE111 Sheet Tuesday, March 09, 2010 1 of 54 Block Diagram D D VRD 11 Intel LGA775 Processor(65W) 3-Phase PWM FSB 800/1066/1333 FSB VGA VGA Channel1 GPU DDRIII RGB Intel GMA 4XXX HDMI DDR3 1066/1333 Eaglelake G41 Channel2 PCIE x16 DDR III SODIMM Modules DDRIII Madison or Park C C DMI Scaler SATA-HDD LVDS SATA-ODD HD Audio Codec SATA2 HD Audio Link Gb RTL8111DL LAN USB 2.0 ICH7 B VT6212LG TI TAS5706 SATA2 PCIE LAN USB Port 0~7 AMP + subwoofer ALC888VC2 PCIE E-SATA JMB362 PCIE Mini PCIE1 PCIE Mini PCIE2 SATA2 ESATA PCI B USB Port 8~11 SPI LPC Bus Keyboard EC Mouse KB3926D Serial Port A A SPI ROM MICRO-STAR INT'L CO.,LTD Title BLOCK DIAGRAM Size Document Number Custom Date: Rev 31 MS-AE111 Sheet Tuesday, March 09, 2010 of 54 CPU SIGNAL BLOCK VCC_VRM_SENSE VCC_VRM_SENSE 31 VSS_VRM_SENSE VSS_VRM_SENSE 31 14,22 FP_RST# VID[0 7] H_A#[3 35] R67 13 13 CPU_GTLREF2 H_IERR# H_FERR# H_STPCLK# H_FERR# H_STPCLK# 13,17 H_INIT# H_INIT# 6 H_DBSY# H_DRDY# H_TRDY# 6 6 6 H_ADS# H_LOCK# H_BNR# H_HIT# H_HITM# H_BPRI# H_DEFER# 13 H_A20M# 13 PM_SLP_N VTT_OUT_RIGHT R17 CPU_GTLREF3 B VTT_OUT_RIGHT 38 CPU_BSEL0 38 CPU_BSEL1 38 CPU_BSEL2 4,13 H_PWRGD 4,6 H_D#[0 63] H_D#[0 63] ADS# LOCK# BNR# HIT# HITM# BPRI# DEFER# X_0R0402 AD1 AF1 AC1 AG1 AE1 AL1 AK1 M2 AE8 AL2 N2 P2 K3 L2 AH2 N5 AE6 C9 G10 D16 A20 51R0402 Y1 V2 X_62R0402 AA2 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 H_PWRGD G29 H30 G30 N1 U3 U2 F3 T2 J2 R1 G2 T1 A13 DP3# DP2# DP1# DP0# J17 H16 H15 J16 ADSTB1# ADSTB0# DSTBP3# DSTBP2# DSTBP1# DSTBP0# DSTBN3# DSTBN2# DSTBN1# DSTBN0# LINT1/NMI LINT0/INTR AD5 R6 C17 G19 E12 B9 A16 G20 G12 C8 L1 K1 H_D#63 H_D#62 H_D#61 H_D#60 H_D#59 H_D#58 H_D#57 H_D#56 H_D#55 H_D#54 B22 A22 A19 B19 B21 C21 B18 A17 B16 C18 D63# D62# D61# D60# D59# D58# D57# D56# D55# D54# R11 H_REQ#[0 4] TP1 LL_ID[1:0] = 00 GTLREF_SEL = H_BPM#0 H_REQ#[0 4] R10 51R0402 0R0402 R6 R7 R8 R9 DPSLP# H_TESTHI12 TP2 TP3 H_BR#0 R19 R20 R22 R23 R25 R26 14 BSEL VTT_OUT_RIGHT 4,5,31 38 38 H_RS#[0 2] 0R0402 X_0R0402 X_0R0402 H_BR#0 H_COMP5_R TABLE FSB FREQUENCY 0 266 MHZ (1066) 200 MHZ (800) 0 133 MHZ (533) C3 X_C0.1u16Y0402 RN3 8P4R-51R0402 H_BPM#3 H_BPM#5 H_BPM#1 H_BPM#0 RN4 8P4R-51R0402 H_TMS H_TDI H_BPM#2 H_BPM#4 4,6 8,14 VTT_OUT_LEFT 4,5 TP8 TP14 TP15 TP16 H_BPM#2 H_BPM#3 C V_FSB_VTT CK_H_CPU# CK_H_CPU R18 X_49.9R1%0402 X_49.9R1%0402 49.9R1%0402 49.9R1%0402 49.9R1%0402 49.9R1%0402 H_ADSTB#1 H_ADSTB#0 H_DSTBP#3 H_DSTBP#2 H_DSTBP#1 H_DSTBP#0 H_DSTBN#3 H_DSTBN#2 H_DSTBN#1 H_DSTBN#0 H_NMI H_INTR R4 R5 51R0402 51R0402 Change 0B 0101 51R0402 51R0402 VTT_OUT_LEFT 51R0402 51R0402 51R0402 X_62R0402 X_62R0402 H_RS#[0 2] For Kentsfield CPU support H_TESTHI9 H_TESTHI8 H_TESTHI12 H_RS#2 H_RS#1 H_RS#0 H_ADSTB#1 H_ADSTB#0 H_DSTBP#3 H_DSTBP#2 H_DSTBP#1 H_DSTBP#0 H_DSTBN#3 H_DSTBN#2 H_DSTBN#1 H_DSTBN#0 H_NMI H_INTR C2 C0.1u16Y0402 VTT_SEL = H_TESTHI2_7 R12 H_TESTHI1 R13 H_TESTHI0 R14 R15 RSVD_G6 R16 H_COMP5 H_COMP4 H_COMP3 H_COMP2 H_COMP1 H_COMP0 C1 C0.1u16Y0402 VTT_OUT_RIGHT 4,5,31 8P4R-680R0603 CPU_MCH_GTLREF H_REQ#4 H_REQ#3 H_REQ#2 H_REQ#1 H_REQ#0 H_TESTHI12 H_TESTHI11 H_TESTHI10 H_TESTHI9 H_TESTHI8 D VTT_OUT_RIGHT Prescott / Cedar Mill CPU_GTLREF0 CPU_GTLREF1 H_BPM#5 H_BPM#4 H_BPM#3 H_BPM#2 H_BPM#1 H_BPM#0 A3 F5 B3 AP1# AP0# BR0# COMP5 COMP4 COMP3 COMP2 COMP1 COMP0 PWRGOOD CPU_GTLREF0 CPU_GTLREF1 GTLREF_SEL G5 J6 K6 M6 J5 K4 G28 F28 BSEL0 BSEL1 BSEL2 RESET# AN7 H1 H2 H29 E24 AG3 AF2 AG2 AD2 AJ1 AJ2 BCLK1# BCLK0# BOOTSELECT LL_ID0 LL_ID1 RN2 R1 680R0402-RH W2 P1 H5 G4 G3 F24 G24 G26 G27 G25 F25 W3 F26 AK6 G6 RSVD RESERVED0 RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 G23 VID5 VID2 VID0 VID4 VID7 VID3 VID6 VID1 VTT_OUT_RIGHT TESTHI12 TESTHI11 TESTHI10 TESTHI9 TESTHI8 TESTHI7 TESTHI6 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1 TESTHI0 FORCEPH RSVD RS2# RS1# RS0# RN1 8P4R-680R0603 8 31 VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 AM7 AM5 AL4 AK4 AL6 AM3 AL5 AM2 PCREQ# REQ4# REQ3# REQ2# REQ1# REQ0# TDI TDO TMS TRST# TCK THERMDA THERMDC THERMTRIP# GND/SKTOCC# PROCHOT# IGNNE# SMI# A20M# TESTI_13 H_CPURST# VID[0 7] RSVD VID6# VID5# VID4# VID3# VID2# VID1# VID0# AJ3 AK3 ITP_CLK1 ITP_CLK0 AC2 AN3 AN4 AN5 AN6 AJ6 AJ5 AH5 AH4 AG5 AG4 AG6 AF4 AF5 AB4 AC5 AB5 AA5 AD6 AA4 Y4 Y6 W6 AB6 W5 V4 V5 U4 U5 T4 U6 T5 R4 M4 L4 M5 P6 L5 D2 C3 C2 D4 E4 G8 G7 VID_SELECT GTLREF0 GTLREF1 GTLREF_SEL CS_GTLREF BPM5# BPM4# BPM3# BPM2# BPM1# BPM0# H_D#53 B15 H_D#52 C14 H_D#51 C15 H_D#50 A14 H_D#49 D17 H_D#48 D20 H_D#47 G22 H_D#46 D22 H_D#45 E22 H_D#44 G21 H_D#43 F21 H_D#42 E21 H_D#41 F20 H_D#40 E19 H_D#39 E18 H_D#38 F18 H_D#37 F17 H_D#36 G17 H_D#35 G18 H_D#34 E16 H_D#33 E15 H_D#32 G16 H_D#31 G15 H_D#30 F15 H_D#29 G14 H_D#28 F14 H_D#27 G13 H_D#26 E13 H_D#25 D13 H_D#24 F12 H_D#23 F11 H_D#22 D10 H_D#21 E10 H_D#20 D7 H_D#19 E9 H_D#18 F9 H_D#17 F8 H_D#16 G9 H_D#15 D11 H_D#14 C12 H_D#13 B12 H_D#12 D8 H_D#11 C11 H_D#10 B10 H_D#9 A11 H_D#8 A10 H_D#7 A7 H_D#6 B7 H_D#5 B6 H_D#4 A5 H_D#3 C6 H_D#2 A4 H_D#1 C5 H_D#0 B4 H_CPURST# R24 EDRDY# IERR# MCERR# FERR#/PBE# STPCLK# BINIT# INIT# RSP# H_ADS# H_LOCK# H_BNR# H_HIT# H_HITM# H_BPRI# H_DEFER# 51R0402 CPU_GTLREF3 R21 F2 AB2 AB3 R3 M3 AD3 P3 H4 DBSY# DRDY# TRDY# H_PROCHOT# H_IGNNE# H_SMI# H_A20M# H_SLP# R641 Kentsfield H_CPUSLP# DBI0# DBI1# DBI2# DBI3# B2 C1 E3 THERMDA THERMDC 13 TRMTRIP# 4,14 H_PROCHOT# 13 H_IGNNE# 13,32 H_SMI# A8 G11 D19 C20 H_DBSY# H_DRDY# H_TRDY# H_TDI H_TDO H_TMS H_TRST# H_TCK 25 25 A35# A34# A33# A32# A31# A30# A29# A28# A27# A26# A25# A24# A23# A22# A21# A20# A19# A18# A17# A16# A15# A14# A13# A12# A11# A10# A9# A8# A7# A6# A5# A4# A3# H_DBI#0 H_DBI#1 H_DBI#2 H_DBI#3 CPU_GTLREF2 H_IERR# C CPU1A H_DBI#[0 3] H_DBI#[0 3] D53# D52# D51# D50# D49# D48# D47# D46# D45# D44# D43# D42# D41# D40# D39# D38# D37# D36# D35# D34# D33# D32# D31# D30# D29# D28# D27# D26# D25# D24# D23# D22# D21# D20# D19# D18# D17# D16# D15# D14# D13# D12# D11# D10# D9# D8# D7# D6# D5# D4# D3# D2# D1# D0# 0R0402 DBR# H_A#[3 35] H_A#35 H_A#34 H_A#33 H_A#32 H_A#31 H_A#30 H_A#29 H_A#28 H_A#27 H_A#26 H_A#25 H_A#24 H_A#23 H_A#22 H_A#21 H_A#20 H_A#19 H_A#18 H_A#17 H_A#16 H_A#15 H_A#14 H_A#13 H_A#12 H_A#11 H_A#10 H_A#9 H_A#8 H_A#7 H_A#6 H_A#5 H_A#4 H_A#3 VCC_SENSE VSS_SENSE VCC_MB_REGULATION VSS_MB_REGULATION D VTT_OUT_RIGHT C4 C5 C0.1u16Y0402 C0.1u16Y0402 6 6 6 6 6 13 13 R27 51R0402 H_TDO R28 51R0402 H_TRST# R29 51R0402 H_TCK VTT_OUT_RIGHT R30 51R0402 B H_SLP# ZIF-SOCK775-15u A A MICRO-STAR INT'L CO.,LTD Title Intel LGA775 - Signals Size Document Number Custom Date: Rev 31 MS-AE111 Sheet Tuesday, March 09, 2010 of 54 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC CPU1B AF21 AF22 AF8 AF9 AG11 AG12 AG14 AG15 AG18 AG19 AG21 AG22 AG25 AG26 AG27 AG28 AG29 AG30 AG8 AG9 AH11 AH12 AH14 AH15 AH18 AH19 AH21 AH22 AH25 AH26 AH27 AH28 AH29 AH30 AH8 AH9 AJ11 AJ12 AJ14 AJ15 AJ18 AJ19 AJ21 AJ22 AJ25 AJ26 AJ8 AJ9 AK11 AK12 AK14 AK15 AK18 AK19 AK21 AK22 AK25 AK26 AK8 AK9 AL11 AL12 AL14 AL15 AL18 AL19 AL21 AL22 AL25 AL26 AL29 AL30 AL8 AL9 AM11 AM12 AM14 AM15 AM18 AM19 AM21 AM22 AM25 AM26 AM29 AM30 AM8 AM9 AN11 AN12 AN14 AN15 AN18 AN19 AN21 AN22 VCCP VCCP A23 H_VCCA B23 H_VSSA H_VCCPLL D23 C23 H_VCCA H_VCCPLL BIOS wirters Guide PDG:page109 D V_FSB_VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTTPWRGD VTT_OUT_RIGHT VTT_OUT_LEFT VTT_SEL Y8 Y30 Y29 Y28 Y27 Y26 Y25 Y24 Y23 W8 W30 W29 W28 W27 W26 W25 W24 W23 V8 U8 U30 U29 U28 U27 U26 U25 U24 U23 T8 T30 T29 T28 T27 T26 T25 T24 T23 R8 P8 N8 N30 N29 N28 N27 N26 N25 N24 N23 M8 M30 M29 M28 M27 M26 M25 M24 M23 L8 K8 K30 K29 K28 K27 K26 K25 K24 K23 J9 J8 J30 J29 J28 J27 J26 J25 J24 J23 J22 J21 J20 J19 J18 J15 J14 J13 J12 J11 J10 AN9 AN8 AN30 AN29 AN26 AN25 HS1 HS2 HS3 HS4 RSVD VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC C VCCA VSSA VCCPLL VCC-IOPLL VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC A25 A26 A27 A28 A29 A30 B25 B26 B27 B28 B29 B30 C25 C26 C27 C28 C29 C30 D25 D26 D27 D28 D29 D30 AM6 VTT_GD V_FSB_VTT C6 C10u10Y0805 C7 C10u10Y0805 C8 C10u10Y0805 CAPS FOR FSB GENERIC AA1 VTT_OUT_RIGHT VTT_OUT_LEFT J1 F27 FSB_VTT_SEL 28 C F29 ZIF-SOCK775-15u D AF19 AF18 AF15 AF14 AF12 AF11 AE9 AE23 AE22 AE21 AE19 AE18 AE15 AE14 AE12 AE11 AD8 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AC8 AC30 AC29 AC28 AC27 AC26 AC25 AC24 AC23 AB8 AA8 VCCP VTT_OUT_RIGHT R744 57.6R1%0402-RH GTLREF VOLTAGE SHOULD BE 0.635*VTT = 0.762V GTL_REF0 R743 100R1%0402 R745 10R0402-1 C674 C1u6.3X50402-1 CPU_GTLREF0 CPU_GTLREF0 V_1P5_ICH C673 C220p25N0402 CP1 X_COPPER H_VCCPLL C11 C10u10Y0805 C12 C0.1u16Y0402 VTT_PWG SPEC : High > 0.9V Low < 0.3V Trise < 150ns VTT_OUT_RIGHT B R372 57.6R1%0402-RH C675 C10u10Y0805 GTL_REF3 R370 100R1%0402 R345 10R0402-1 C678 C1u6.3X50402-1 CPU_GTLREF3 CPU_GTLREF3 680R0402-RH C677 C220p25N0402 B V_FSB_VTT R581 0R R38 1KR0402 H_VCCA C595 C10u10Y0805 C594 C0.1u16Y0402 H_VSSA V_FSB_VTT 31 R40 0B change to V_FSB_VTT VTT_OUT_RIGHT R374 R34 VCC5_SB VTT_OUT_RIGHT 51R1%0402 GTLREF VOLTAGE SHOULD BE 0.667*VTT = 0.8004V GTL_REF1 R344 100R1%0402 R741 10R0402-1 C392 C1u6.3X50402-1 CPU_GTLREF1 R39 VID_GD# 10KR0402 VTT_GD 4.7KR0402 VTT_GD 17 Q1 N-MMBT3904_NL_SOT23 Q2 N-MMBT3904_NL_SOT23 C16 C1u10X CPU_GTLREF1 C679 C220p25N0402 VTT_OUT_RIGHT R740 A 51R1%0402 C676 C10u10Y0805 3,5,31 VTT_OUT_RIGHT 3,5 VTT_OUT_LEFT GTL_REF2 R373 100R1%0402 VTT_OUT_RIGHT VTT_OUT_LEFT R69 R68 R70 R71 R72 R742 10R0402-1 C680 C1u6.3X50402-1 130R1%0402 62R0402 X_100R0402 62R0402 62R0402 CPU_GTLREF2 CPU_GTLREF2 C681 C220p25N0402 H_PROCHOT# H_IERR# H_PWRGD H_BR#0 H_CPURST# A MICRO-STAR INT'L CO.,LTD H_PROCHOT# 3,14 H_IERR# H_PWRGD H_BR#0 H_CPURST# Title 3,13 3,6 3,6 Date: Intel LGA775 - Power Size Document Number Custom Rev 31 MS-AE111 Sheet Tuesday, March 09, 2010 of 54 TP13 C B VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS R77 X_51R0402 NC MSID0 NC R78 0R0402 H_TESTHI12 H_TESTHI12 H28 H27 H26 H25 H24 H23 H22 H21 H20 H19 H18 H17 MSID1 MSID0 R74 24.9R1%0402 MSID1 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Y7 Y5 Y2 W7 W4 V7 V6 V30 V3 V29 V28 V27 V26 V25 V24 V23 U7 U1 T7 T6 T3 R7 R5 R30 R29 R28 R27 R26 R25 R24 R23 R2 P7 P4 P30 P29 P28 P27 P26 P25 P24 P23 N7 N6 N3 M7 M1 L7 L6 L30 L3 L29 L28 L27 L26 L25 L24 L23 K7 K5 K2 J7 J4 H9 H8 H7 H6 H3 V1 W1 AC4 R76 X_51R0402 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS MSID[1] MSID[0] RSVD J3 N4 P5 TP11 TP12 VSS VSS VSS X_1KR0402 A12 A15 A18 A2 A21 A24 A6 A9 AA23 AA24 AA25 AA26 AA27 AA28 AA29 AA3 AA30 AA6 AA7 AB1 AB23 AB24 AB25 AB26 AB27 AB28 AB29 AB30 AB7 AC3 AC6 AC7 AD4 AD7 AE10 AE13 AE16 AE17 AE2 AE20 AE24 AE25 AE26 AE27 AE28 H_COMP8 R75 51R0402 RSVD RSVD RSVD CPU1C E5 E6 E7 F23 F6 B13 3,4,31 VTT_OUT_RIGHT B1 B11 B14 R63 0R0402 Y3 AE3 H_COMP7 AE4 D1 D14 E23 D RSVD RSVD RSVD RSVD IMPSEL# RSVD R480 COMP6 COMP7 RSVD RSVD RSVD RSVD Intel Core Due or Wolfadale processor VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 31 PSI# AN1 AN10 AN13 AN16 AN17 AN2 AN20 AN23 AN24 AN27 AN28 AE29 AE30 AE5 AE7 AF10 AF13 AF16 AF17 AF20 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF3 AF30 AF6 AF7 AG10 AG13 AG16 AG17 AG20 AG23 AG24 AG7 AH1 AH10 AH13 AH16 AH17 AH20 AH23 AH24 AH3 AH6 AH7 AJ10 AJ13 AJ16 AJ17 AJ20 AJ23 AJ24 AJ27 AJ28 AJ29 AJ30 AJ4 AJ7 AK10 AK13 AK16 AK17 AK2 AK20 AK23 AK24 AK27 AK28 AK29 AK30 AK5 AK7 AL10 AL13 AL16 AL17 AL20 AL23 AL24 AL27 AL28 AL3 AL7 AM1 AM10 AM13 AM16 AM17 AM20 AM23 AM24 AM27 AM28 AM4 Intel Core Quad or Yorkfield Processer D R73 X_49.9R1%0402 For Kentsfield CPU support (Intel CRB stuff it) VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS H14 H13 H12 H11 H10 G1 F7 F4 F22 F19 F16 F13 F10 E8 E29 E28 E27 E26 E25 E20 E2 E17 E14 E11 D9 D6 D5 D3 D24 D21 D18 D15 D12 C7 C4 C24 C22 C19 C16 C13 C10 B8 B5 B24 B20 B17 Title Date: R61 51R0402 VTT_OUT_LEFT VTT_OUT_L R64 R62 X_0R0402 Tuesday, March 09, 2010 Size Document Number Custom MS-AE111 VTT_OUT_LEFT 3,4 Kentsfield H_BPM#0 Sheet H_BPM#0 of C 0R0402 B ZIF-SOCK775-15u VRD_SEL A A MICRO-STAR INT'L CO.,LTD Intel LGA775 - GND 54 Rev 31 H_REQ#[0 4] H_REQ#[0 4] C H_D#[0 63] H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 L36 L37 J38 F40 H39 L38 L43 N39 N35 N37 J41 N40 M45 R35 T36 R36 R34 R37 R39 U38 T37 U34 U40 T34 Y36 U35 AA35 U37 Y37 Y34 Y38 AA37 AA36 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 G38 K35 J39 C43 G39 FSB_REQB_0 FSB_REQB_1 FSB_REQB_2 FSB_REQB_3 FSB_REQB_4 FSB_AB_3 FSB_AB_4 FSB_AB_5 FSB_AB_6 FSB_AB_7 FSB_AB_8 FSB_AB_9 FSB_AB_10 FSB_AB_11 FSB_AB_12 FSB_AB_13 FSB_AB_14 FSB_AB_15 FSB_AB_16 FSB_AB_17 FSB_AB_18 FSB_AB_19 FSB_AB_20 FSB_AB_21 FSB_AB_22 FSB_AB_23 FSB_AB_24 FSB_AB_25 FSB_AB_26 FSB_AB_27 FSB_AB_28 FSB_AB_29 FSB_AB_30 FSB_AB_31 FSB_AB_32 FSB_AB_33 FSB_AB_34 FSB_AB_35 3 H_ADSTB#0 H_ADSTB#1 H_ADSTB#0 H_ADSTB#1 J40 T39 FSB_ADSTBB_0 FSB_ADSTBB_1 3 3 3 3 H_DSTBP#0 H_DSTBN#0 H_DSTBP#1 H_DSTBN#1 H_DSTBP#2 H_DSTBN#2 H_DSTBP#3 H_DSTBN#3 H_DSTBP#0 H_DSTBN#0 H_DSTBP#1 H_DSTBN#1 H_DSTBP#2 H_DSTBN#2 H_DSTBP#3 H_DSTBN#3 C39 B39 K31 J31 J25 K25 C32 D32 FSB_DSTBPB_0 FSB_DSTBNB_0 FSB_DSTBPB_1 FSB_DSTBNB_1 FSB_DSTBPB_2 FSB_DSTBNB_2 FSB_DSTBPB_3 FSB_DSTBNB_3 H_DBI#0 H_DBI#1 H_DBI#2 B40 F33 F26 FSB_DINVB_0 FSB_DINVB_1 FSB_DINVB_2 H_DBI#3 H_ADS# H_TRDY# H_DRDY# H_DEFER# H_HITM# H_HIT# H_LOCK# H_BR#0 H_BNR# H_BPRI# H_DBSY# H_RS#0 H_RS#1 H_RS#2 H_CPURST# D30 J42 L40 J43 G44 K44 H45 H40 L42 J44 H37 H42 G43 L44 G42 D27 FSB_DINVB_3 FSB_ADSB FSB_TRDYB FSB_DRDYB FSB_DEFERB FSB_HITMB FSB_HITB FSB_LOCKB FSB_BREQ0B FSB_BNRB FSB_BPRIB FSB_DBSYB FSB_RSB_0 FSB_RSB_1 FSB_RSB_2 FSB_CPURSTB N25 RSVD5 H_DBI#[0 3] H_DBI#[0 3] H_ADS# H_TRDY# H_DRDY# H_DEFER# H_HITM# H_HIT# H_LOCK# 3,4 H_BR#0 H_BNR# H_BPRI# H_DBSY# H_RS#0 H_RS#1 H_RS#2 3,4 H_CPURST# B U47B EAGLELAKE_DDR2 FSB_DB_0 FSB_DB_1 FSB_DB_2 FSB_DB_3 FSB_DB_4 FSB_DB_5 FSB_DB_6 FSB_DB_7 FSB_DB_8 FSB_DB_9 FSB_DB_10 FSB_DB_11 FSB_DB_12 FSB_DB_13 FSB_DB_14 FSB_DB_15 FSB_DB_16 FSB_DB_17 FSB_DB_18 FSB_DB_19 FSB_DB_20 FSB_DB_21 FSB_DB_22 FSB_DB_23 FSB_DB_24 FSB_DB_25 FSB_DB_26 FSB_DB_27 FSB_DB_28 FSB_DB_29 FSB_DB_30 FSB_DB_31 FSB_DB_32 FSB_DB_33 FSB_DB_34 FSB_DB_35 FSB_DB_36 FSB_DB_37 FSB_DB_38 FSB_DB_39 FSB_DB_40 FSB_DB_41 FSB_DB_42 FSB_DB_43 FSB_DB_44 FSB_DB_45 FSB_DB_46 FSB_DB_47 FSB_DB_48 FSB_DB_49 FSB_DB_50 FSB_DB_51 FSB_DB_52 FSB_DB_53 FSB_DB_54 FSB_DB_55 FSB_DB_56 FSB_DB_57 FSB_DB_58 FSB_DB_59 FSB_DB_60 FSB_DB_61 FSB_DB_62 FSB_DB_63 F44 C44 D44 C41 E43 B43 D40 B42 B38 F38 A38 B37 D38 C37 D37 B36 E37 J35 H35 F37 G37 J33 L33 G33 L31 M31 M30 J30 G31 K30 M29 G30 J29 F29 H29 L25 K26 L29 J26 M26 H26 F25 F24 G25 H24 L24 J24 N24 C28 B31 F35 C35 B35 D35 D31 A34 B32 F31 D28 A29 C30 B30 E27 B28 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 FSB_SWING FSB_RCOMP B24 A23 HXSWING HXRCOMP FSB_DVREF FSB_ACCVREF C22 B23 MCH_GTLREF HPL_CLKINP HPL_CLKINN P29 P30 H_D#[0 63] 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 13 13 13 13 13 13 13 13 PCIE_GFX_RX0P PCIE_GFX_RX0N PCIE_GFX_RX1P PCIE_GFX_RX1N PCIE_GFX_RX2P PCIE_GFX_RX2N PCIE_GFX_RX3P PCIE_GFX_RX3N PCIE_GFX_RX4P PCIE_GFX_RX4N PCIE_GFX_RX5P PCIE_GFX_RX5N PCIE_GFX_RX6P PCIE_GFX_RX6N PCIE_GFX_RX7P PCIE_GFX_RX7N PCIE_GFX_RX8P PCIE_GFX_RX8N PCIE_GFX_RX9P PCIE_GFX_RX9N PCIE_GFX_RX10P PCIE_GFX_RX10N PCIE_GFX_RX11P PCIE_GFX_RX11N PCIE_GFX_RX12P PCIE_GFX_RX12N PCIE_GFX_RX13P PCIE_GFX_RX13N PCIE_GFX_RX14P PCIE_GFX_RX14N PCIE_GFX_RX15P PCIE_GFX_RX15N DMI_ITP_MRP_0 DMI_ITN_MRN_0 DMI_ITP_MRP_1 DMI_ITN_MRN_1 DMI_ITP_MRP_2 DMI_ITN_MRN_2 DMI_ITP_MRP_3 DMI_ITN_MRN_3 38 CK_PE_100M_MCH 38 CK_PE_100M_MCH# DMI_ITP_MRP_0 DMI_ITN_MRN_0 DMI_ITP_MRP_1 DMI_ITN_MRN_1 DMI_ITP_MRP_2 DMI_ITN_MRN_2 DMI_ITP_MRP_3 DMI_ITN_MRN_3 CK_PE_100M_MCH CK_PE_100M_MCH# PEG_RXP_0 PEG_RXN_0 PEG_RXP_1 PEG_RXN_1 PEG_RXP_2 PEG_RXN_2 PEG_RXP_3 PEG_RXN_3 PEG_RXP_4 PEG_RXN_4 PEG_RXP_5 PEG_RXN_5 PEG_RXP_6 PEG_RXN_6 PEG_RXP_7 PEG_RXN_7 PEG_RXP_8 PEG_RXN_8 PEG_RXP_9 PEG_RXN_9 PEG_RXP_10 PEG_RXN_10 PEG_RXP_11 PEG_RXN_11 PEG_RXP_12 PEG_RXN_12 PEG_RXP_13 PEG_RXN_13 PEG_RXP_14 PEG_RXN_14 PEG_RXP_15 PEG_RXN_15 AD7 AD8 AE9 AE10 AE6 AE7 AF9 AF8 DMI_RXP_0 DMI_RXN_0 DMI_RXP_1 DMI_RXN_1 DMI_RXP_2 DMI_RXN_2 DMI_RXP_3 DMI_RXN_3 D9 E9 J13 G13 AB13 AD13 EAGLELAKE_DDR2 F6 G7 H6 G4 J6 J7 L6 L7 N9 N10 N7 N6 R7 R6 R9 R10 U10 U9 U6 U7 AA9 AA10 R4 P4 AA7 AA6 AB10 AB9 AB3 AA2 AD10 AD11 PCIE U47A D 3 H_A#[3 35] H_A#[3 35] FSB DMI GFX_TX0P_C GFX_TX0N_C GFX_TX1P_C GFX_TX1N_C GFX_TX2P_C GFX_TX2N_C GFX_TX3P_C GFX_TX3N_C GFX_TX4P_C GFX_TX4N_C GFX_TX5P_C GFX_TX5N_C GFX_TX6P_C GFX_TX6N_C GFX_TX7P_C GFX_TX7N_C GFX_TX8P_C GFX_TX8N_C GFX_TX9P_C GFX_TX9N_C GFX_TX10P_C GFX_TX10N_C GFX_TX11P_C GFX_TX11N_C GFX_TX12P_C GFX_TX12N_C GFX_TX13P_C GFX_TX13N_C GFX_TX14P_C GFX_TX14N_C GFX_TX15P_C GFX_TX15N_C PEG_TXP_0 PEG_TXN_0 PEG_TXP_1 PEG_TXN_1 PEG_TXP_2 PEG_TXN_2 PEG_TXP_3 PEG_TXN_3 PEG_TXP_4 PEG_TXN_4 PEG_TXP_5 PEG_TXN_5 PEG_TXP_6 PEG_TXN_6 PEG_TXP_7 PEG_TXN_7 PEG_TXP_8 PEG_TXN_8 PEG_TXP_9 PEG_TXN_9 PEG_TXP_10 PEG_TXN_10 PEG_TXP_11 PEG_TXN_11 PEG_TXP_12 PEG_TXN_12 PEG_TXP_13 PEG_TXN_13 PEG_TXP_14 PEG_TXN_14 PEG_TXP_15 PEG_TXN_15 C11 B11 A10 B9 C9 D8 B8 C7 B7 B6 B3 B4 D2 C2 H2 G2 J2 K2 K1 L2 P2 M2 T2 R1 U2 V2 W4 V3 AA4 Y4 AC1 AB2 DMI_TXP_0 DMI_TXN_0 DMI_TXP_1 DMI_TXN_1 DMI_TXP_2 DMI_TXN_2 DMI_TXP_3 DMI_TXN_3 AC2 AD2 AD4 AE4 AE2 AF2 AF4 AG4 DMI_NB_TXP0 DMI_NB_TXN0 DMI_NB_TXP1 DMI_NB_TXN1 DMI_NB_TXP2 DMI_NB_TXN2 DMI_NB_TXP3 DMI_NB_TXN3 Y7 Y8 Y6 GRCOMP C174 C175 C241 C242 C245 C246 C178 C176 C170 C169 C181 C183 C172 C173 C167 C168 C229 C230 C235 C236 C237 C243 C232 C231 C198 C191 C233 C234 C200 C201 C186 C190 C544 C547 C273 C541 C542 C543 C545 C546 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 C0.1u10X0402 PCIE_GFX_TX0P 39 PCIE_GFX_TX0N 39 PCIE_GFX_TX1P 39 PCIE_GFX_TX1N 39 PCIE_GFX_TX2P 39 PCIE_GFX_TX2N 39 PCIE_GFX_TX3P 39 PCIE_GFX_TX3N 39 PCIE_GFX_TX4P 39 PCIE_GFX_TX4N 39 PCIE_GFX_TX5P 39 PCIE_GFX_TX5N 39 PCIE_GFX_TX6P 39 PCIE_GFX_TX6N 39 PCIE_GFX_TX7P 39 PCIE_GFX_TX7N 39 PCIE_GFX_TX8P 39 PCIE_GFX_TX8N 39 PCIE_GFX_TX9P 39 PCIE_GFX_TX9N 39 PCIE_GFX_TX10P 39 PCIE_GFX_TX10N 39 PCIE_GFX_TX11P 39 PCIE_GFX_TX11N 39 PCIE_GFX_TX12P 39 PCIE_GFX_TX12N 39 PCIE_GFX_TX13P 39 PCIE_GFX_TX13N 39 PCIE_GFX_TX14P 39 PCIE_GFX_TX14N 39 PCIE_GFX_TX15P 39 PCIE_GFX_TX15N 39 DMI_MTP_IRP_0 DMI_MTN_IRN_0 DMI_MTP_IRP_1 DMI_MTN_IRN_1 DMI_MTP_IRP_2 DMI_MTN_IRN_2 DMI_MTP_IRP_3 DMI_MTN_IRN_3 D DMI_MTP_IRP_0 DMI_MTN_IRN_0 DMI_MTP_IRP_1 DMI_MTN_IRN_1 DMI_MTP_IRP_2 DMI_MTN_IRN_2 DMI_MTP_IRP_3 DMI_MTN_IRN_3 13 13 13 13 13 13 13 13 V_1P1_CORE EXP_CLKP EXP_CLKN EXP_RCOMPO EXP_COMPI EXP_ICOMPO SDVO_CTRLDATA SDVO_CTRLCLK EXP_RBIAS RSVD17 RSVD16 AG1 EXP_RBIAS R239 49.9R1%0402 R661 X_750R1%0402 R662 750R1%0402 C V_1P1_CORE INTEL-AC82G45-A3-HF V_1P1_CORE C162 W10/S5 W10/S7 R148 16.5R1%0402-RH CK_H_MCH CK_H_MCH# 38 38 C0.1u16Y0402 R224 5.1KR0402 DMI_ITP_MRP_0 R226 5.1KR0402 DMI_ITP_MRP_1 R230 5.1KR0402 DMI_ITP_MRP_2 R478 5.1KR0402 DMI_ITP_MRP_3 B INTEL-AC82G45-A3-HF V_FSB_VTT V_FSB_VTT HXSWING SHOULD BE 1/4*VTT R156 301R1%0402 *GTLREF VOLTAGE SHOULD BE 0.63*VTT=0.756V R149 57.6R1%0402-RH HX_SWING R187 R157 100R1%0402 C208 C0.1u10X0402 51R1%0402 HXSWING W10/S5 R168 R155 100R1%0402 CPU_MCH_GTLREF 51R1%0402 C194 C1u6.3X50402-1 CPU_MCH_GTLREF MCH_GTLREF C222 C220p25N0402 A A MICRO-STAR INT'L CO.,LTD Title Eaglelake - FSB , PCIE Size Document Number Custom Date: MS-AE111 Tuesday, March 09, 2010 Rev 31 Sheet of 54 M_A_DQS#[7:0] 11 M_A_A[14:1] M_A_A[14:0] D BC41 M_A_A1 BC35 M_A_A2 BB32 M_A_A3 BC32 M_A_A4 BD32 M_A_A5 BB31 M_A_A6 AY31 M_A_A7 BA31 M_A_A8 BD31 M_A_A9 BD30 M_A_A10AW43 M_A_A11 BC30 M_A_A12 BB30 M_A_A13 AM42 M_A_A14 BD28 T33 11 11 C M_A_CAS# M_A_RAS# M_A_CAS# M_A_RAS# 11 M_A_BS[0 2] 11 M_CS#0 M_A_BS[0 2] M_CKE0 M_CKE1 11 M_ODT[0 1] M_ODT[0 1] AV45 AY44 BC28 DDR_A_BS_0 DDR_A_BS_1 DDR_A_BS_2 M_CS#0 AU43 AR40 AU44 AM43 DDR_A_CSB_0 DDR_A_CSB_1 DDR_A_CSB_2 DDR_A_CSB_3 BB27 BD27 BA27 AY26 DDR_A_CKE_0 DDR_A_CKE_1 DDR_A_CKE_2 DDR_A_CKE_3 AR42 AM44 AR44 AL40 DDR_A_ODT_0 DDR_A_ODT_1 DDR_A_ODT_2 DDR_A_ODT_3 M_ODT0 M_ODT1 M_CLK_DDR0 M_CLK_DDR#0 11 M_CLK_DDR0 11 M_CLK_DDR#0 M_CLK_DDR1 M_CLK_DDR#1 11 M_CLK_DDR1 11 M_CLK_DDR#1 DDR_A_WEB DDR_A_CASB DDR_A_RASB M_A_BS0 M_A_BS1 M_A_BS2 T32 11 11 AW42 AU42 AV42 DDR_A_MA_0 DDR_A_MA_1 DDR_A_MA_2 DDR_A_MA_3 DDR_A_MA_4 DDR_A_MA_5 DDR_A_MA_6 DDR_A_MA_7 DDR_A_MA_8 DDR_A_MA_9 DDR_A_MA_10 DDR_A_MA_11 DDR_A_MA_12 DDR_A_MA_13 DDR_A_MA_14 AY37 BA37 AW29 AY29 AU37 AV37 AU33 AT33 AT30 AR30 AW38 AY38 DDR_A_CK_0 DDR_A_CKB_0 DDR_A_CK_1 DDR_A_CKB_1 DDR_A_CK_2 DDR_A_CKB_2 DDR_A_CK_3 DDR_A_CKB_3 DDR_A_CK_4 DDR_A_CKB_4 DDR_A_CK_5 DDR_A_CKB_5 VCC_DDR B 11 R667 1KR0402 VCC5_SB M_CS#1 M_A_A0 11 M_A_A0 M_A_WE# 11 M_A_WE# T34 DRAM_PWROK DDR3_RST# AR43 BB40 AT44 AV40 AR6 BC24 DDR3_A_CSB1 DDR3_A_MA0 DDR3_A_WEB DDR3_B_ODT3 DDR3_DRAM_PWROK DDR3_DRAMRSTB 11,12 DDR3_RST# D R666 1KR0402 S G 8.2KR0402 R831 Q52 Q18 C1u10X N-2N7002_SOT23 C18 DDR_A Change 0B C B E C1117 C1000p16X N-SST3904_SOT23 SLP_S4# DDR_A_DQS_0 DDR_A_DQSB_0 DDR_A_DQS_1 DDR_A_DQSB_1 DDR_A_DQS_2 DDR_A_DQSB_2 DDR_A_DQS_3 DDR_A_DQSB_3 DDR_A_DQS_4 DDR_A_DQSB_4 DDR_A_DQS_5 DDR_A_DQSB_5 DDR_A_DQS_6 DDR_A_DQSB_6 DDR_A_DQS_7 DDR_A_DQSB_7 DDR_A_DM_0 DDR_A_DM_1 DDR_A_DM_2 DDR_A_DM_3 DDR_A_DM_4 DDR_A_DM_5 DDR_A_DM_6 DDR_A_DM_7 DDR_A_DQ_0 DDR_A_DQ_1 DDR_A_DQ_2 DDR_A_DQ_3 DDR_A_DQ_4 DDR_A_DQ_5 DDR_A_DQ_6 DDR_A_DQ_7 DDR_A_DQ_8 DDR_A_DQ_9 DDR_A_DQ_10 DDR_A_DQ_11 DDR_A_DQ_12 DDR_A_DQ_13 DDR_A_DQ_14 DDR_A_DQ_15 DDR_A_DQ_16 DDR_A_DQ_17 DDR_A_DQ_18 DDR_A_DQ_19 DDR_A_DQ_20 DDR_A_DQ_21 DDR_A_DQ_22 DDR_A_DQ_23 DDR_A_DQ_24 DDR_A_DQ_25 DDR_A_DQ_26 DDR_A_DQ_27 DDR_A_DQ_28 DDR_A_DQ_29 DDR_A_DQ_30 DDR_A_DQ_31 DDR_A_DQ_32 DDR_A_DQ_33 DDR_A_DQ_34 DDR_A_DQ_35 DDR_A_DQ_36 DDR_A_DQ_37 DDR_A_DQ_38 DDR_A_DQ_39 DDR_A_DQ_40 DDR_A_DQ_41 DDR_A_DQ_42 DDR_A_DQ_43 DDR_A_DQ_44 DDR_A_DQ_45 DDR_A_DQ_46 DDR_A_DQ_47 DDR_A_DQ_48 DDR_A_DQ_49 DDR_A_DQ_50 DDR_A_DQ_51 DDR_A_DQ_52 DDR_A_DQ_53 DDR_A_DQ_54 DDR_A_DQ_55 DDR_A_DQ_56 DDR_A_DQ_57 DDR_A_DQ_58 DDR_A_DQ_59 DDR_A_DQ_60 DDR_A_DQ_61 DDR_A_DQ_62 DDR_A_DQ_63 BC5 BD4 BB9 BC9 BD15 BB15 AR22 AT22 AH43 AH42 AD43 AE42 Y43 Y42 T44 T43 M_A_DQS0 M_A_DQS#0 M_A_DQS1 M_A_DQS#1 M_A_DQS2 M_A_DQS#2 M_A_DQS3 M_A_DQS#3 M_A_DQS4 M_A_DQS#4 M_A_DQS5 M_A_DQS#5 M_A_DQS6 M_A_DQS#6 M_A_DQS7 M_A_DQS#7 12 M_A_DQS0 M_A_DQS#0 M_A_DQS1 M_A_DQS#1 M_A_DQS2 M_A_DQS#2 M_A_DQS3 M_A_DQS#3 M_A_DQS4 M_A_DQS#4 M_A_DQS5 M_A_DQS#5 M_A_DQS6 M_A_DQS#6 M_A_DQS7 M_A_DQS#7 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 M_A_DM[7:0] BC3 M_A_DM0 BD9 M_A_DM1 BD14 M_A_DM2 AV22 M_A_DM3 AK42 M_A_DM4 AE45 M_A_DM5 AA45 M_A_DM6 T42 M_A_DM7 BC2 BD3 BD7 BB7 BB2 BA3 BE6 BD6 BB8 AY8 BD11 BB11 BC7 BE8 BD10 AY11 BB14 BC14 BC16 BB16 BC11 BE12 BA15 BD16 AW21 AY22 AV24 AY24 AU21 AT21 AR24 AU24 AL41 AK43 AG42 AG44 AL42 AK44 AH44 AG41 AF43 AF42 AC44 AC42 AF40 AF44 AD44 AC41 AB43 AA42 W42 W41 AB42 AB44 Y44 Y40 V42 U45 R40 P44 V44 V43 R41 R44 M_A_DQS#[7:0] 11 EAGLELAKE_DDR2 U47C T16 M_A_DM[7:0] 11 0B change M_A_DQ[63:0] 11 M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 M_B_A[0 14] 12 12 12 M_B_WE# M_B_CAS# M_B_RAS# 12 M_B_BS[0 2] 12 12 M_CS#2 M_CS#3 12 12 M_CKE2 M_CKE3 12 M_ODT[2 3] 12 12 M_CLK_DDR2 M_CLK_DDR#2 12 12 M_CLK_DDR3 M_CLK_DDR#3 EAGLELAKE_DDR2 U47D M_B_A[0 14] M_B_BS[0 2] M_ODT[2 3] M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 BD24 BB23 BB24 BD23 BB22 BD22 BC22 BC20 BB20 BD20 BC26 BD19 BB19 BE38 BA19 DDR_B_MA_0 DDR_B_MA_1 DDR_B_MA_2 DDR_B_MA_3 DDR_B_MA_4 DDR_B_MA_5 DDR_B_MA_6 DDR_B_MA_7 DDR_B_MA_8 DDR_B_MA_9 DDR_B_MA_10 DDR_B_MA_11 DDR_B_MA_12 DDR_B_MA_13 DDR_B_MA_14 M_B_WE# M_B_CAS# M_B_RAS# BD36 BC37 BD35 DDR_B_WEB DDR_B_CASB DDR_B_RASB M_B_BS0 M_B_BS1 M_B_BS2 BD26 BB26 BD18 DDR_B_BS_0 DDR_B_BS_1 DDR_B_BS_2 M_CS#2 M_CS#3 BB35 BD39 BB37 BD40 DDR_B_CSB_0 DDR_B_CSB_1 DDR_B_CSB_2 DDR_B_CSB_3 M_CKE2 M_CKE3 BC18 AY20 BE17 BB18 DDR_B_CKE_0 DDR_B_CKE_1 DDR_B_CKE_2 DDR_B_CKE_3 M_ODT2 M_ODT3 BD37 BC39 BB38 BD42 DDR_B_ODT_0 DDR_B_ODT_1 DDR_B_ODT_2 DDR_B_ODT_3 AY33 AW33 AV31 AW31 AW35 AY35 AT31 AU31 AP31 AP30 AW37 AV35 DDR_B_CK_0 DDR_B_CKB_0 DDR_B_CK_1 DDR_B_CKB_1 DDR_B_CK_2 DDR_B_CKB_2 DDR_B_CK_3 DDR_B_CKB_3 DDR_B_CK_4 DDR_B_CKB_4 DDR_B_CK_5 DDR_B_CKB_5 M_CLK_DDR2 M_CLK_DDR#2 M_CLK_DDR3 M_CLK_DDR#3 DDR_B_DQS_0 DDR_B_DQSB_0 DDR_B_DQS_1 DDR_B_DQSB_1 DDR_B_DQS_2 DDR_B_DQSB_2 DDR_B_DQS_3 DDR_B_DQSB_3 DDR_B_DQS_4 DDR_B_DQSB_4 DDR_B_DQS_5 DDR_B_DQSB_5 DDR_B_DQS_6 DDR_B_DQSB_6 DDR_B_DQS_7 DDR_B_DQSB_7 DDR_B_DM_0 DDR_B_DM_1 DDR_B_DM_2 DDR_B_DM_3 DDR_B_DM_4 DDR_B_DM_5 DDR_B_DM_6 DDR_B_DM_7 VCC_DDR R286 1KR1%0402 C338 C1u10X R287 1KR1%0402 DDR_B DDR_VREF 10W/10S C336 C0.1u16Y0402 BB44 DDR_VREF AY42 BA43 BC43 BC44 DDR_RPD DDR_RPU DDR_SPD DDR_SPU AN29 AN30 AJ33 AK33 RSVD1 RSVD2 RSVD3 RSVD4 VCC_DDR R275 R274 R281 R280 80.6R1%0402 80.6R1%0402 249R1%0402 80.6R1%0402 SRCOMP0 SRCOMP1 SRCOMP2 SRCOMP3 5W/10S C550 C0.1u16Y0402 DDR_B_DQ_0 DDR_B_DQ_1 DDR_B_DQ_2 DDR_B_DQ_3 DDR_B_DQ_4 DDR_B_DQ_5 DDR_B_DQ_6 DDR_B_DQ_7 DDR_B_DQ_8 DDR_B_DQ_9 DDR_B_DQ_10 DDR_B_DQ_11 DDR_B_DQ_12 DDR_B_DQ_13 DDR_B_DQ_14 DDR_B_DQ_15 DDR_B_DQ_16 DDR_B_DQ_17 DDR_B_DQ_18 DDR_B_DQ_19 DDR_B_DQ_20 DDR_B_DQ_21 DDR_B_DQ_22 DDR_B_DQ_23 DDR_B_DQ_24 DDR_B_DQ_25 DDR_B_DQ_26 DDR_B_DQ_27 DDR_B_DQ_28 DDR_B_DQ_29 DDR_B_DQ_30 DDR_B_DQ_31 DDR_B_DQ_32 DDR_B_DQ_33 DDR_B_DQ_34 DDR_B_DQ_35 DDR_B_DQ_36 DDR_B_DQ_37 DDR_B_DQ_38 DDR_B_DQ_39 DDR_B_DQ_40 DDR_B_DQ_41 DDR_B_DQ_42 DDR_B_DQ_43 DDR_B_DQ_44 DDR_B_DQ_45 DDR_B_DQ_46 DDR_B_DQ_47 DDR_B_DQ_48 DDR_B_DQ_49 DDR_B_DQ_50 DDR_B_DQ_51 DDR_B_DQ_52 DDR_B_DQ_53 DDR_B_DQ_54 DDR_B_DQ_55 DDR_B_DQ_56 DDR_B_DQ_57 DDR_B_DQ_58 DDR_B_DQ_59 DDR_B_DQ_60 DDR_B_DQ_61 DDR_B_DQ_62 DDR_B_DQ_63 AW8 AW9 AT15 AU15 AR20 AR17 AU26 AT26 AR38 AR37 AK34 AL34 AF37 AF36 AB35 AD35 M_B_DQS0 M_B_DQS#0 M_B_DQS1 M_B_DQS#1 M_B_DQS2 M_B_DQS#2 M_B_DQS3 M_B_DQS#3 M_B_DQS4 M_B_DQS#4 M_B_DQS5 M_B_DQS#5 M_B_DQS6 M_B_DQS#6 M_B_DQS7 DQS_B#7 M_B_DQS0 M_B_DQS#0 M_B_DQS1 M_B_DQS#1 M_B_DQS2 M_B_DQS#2 M_B_DQS3 M_B_DQS#3 M_B_DQS4 M_B_DQS#4 M_B_DQS5 M_B_DQS#5 M_B_DQS6 M_B_DQS#6 M_B_DQS7 M_B_DQS#7 D M_B_DM[7:0] AY6 M_B_DM0 AR15 M_B_DM1 AU17 M_B_DM2 AV25 M_B_DM3 AU39 M_B_DM4 AL37 M_B_DM5 AJ35 M_B_DM6 AD37 M_B_DM7 AV7 AW4 BA9 AU11 AU7 AU8 AW7 AY9 AY13 AP15 AW15 AT16 AU13 AW13 AP16 AU16 AY17 AV17 AR21 AV20 AP17 AW16 AT20 AN20 AT25 AV26 AU29 AV29 AW25 AR25 AP26 AR29 AR36 AU38 AN35 AN37 AV39 AW39 AU40 AU41 AL35 AL36 AK36 AJ34 AN39 AN40 AK37 AL39 AJ38 AJ37 AF38 AE37 AK40 AJ40 AF34 AE35 AD40 AD38 AB40 AA39 AE36 AE39 AB37 AB38 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 12 M_B_DM[7:0] 12 M_B_DQ[63:0] 12 M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 C B 14,17,30 INTEL-AC82G45-A3-HF INTEL-AC82G45-A3-HF A A MICRO-STAR INT'L CO.,LTD Title Eaglelake - Memory DDR2 Size Document Number Custom Date: MS-AE111 Tuesday, March 09, 2010 Rev 31 Sheet of 54 EAGLELAKE_DDR2 D VCC3 H_BSL0 H_BSL0 H_BSL1 H_BSL1 H_BSL2 H_BSL2 T17 T18 R655 X_1KR0402 EXP_SLR R656 X_1KR0402 R659 R657 R658 X_0R0402 X_1KR0402 X_1KR0402 EXP_EN MCH_TCEN T19 T20 T21 T22 T23 T24 T25 CL_VREF_MCH 13,32 PLTRST# 14,17,32 PWRGD F17 G16 P15 M20 N17 K16 F15 G15 H17 L17 BSEL0 BSEL1 BSEL2 ALLZTEST XORTEST RSVD40 EXP_SLR RSVD11 EXP_SM ITPM_ENB M17 J17 G20 J16 M16 J15 J20 F20 RSVD6 CEN BSCANTEST RSVD7 RSVD8 RSVD9 RSVD10 DUALX8_ENABLE AY4 AY2 AN13 AW2 AN8 CL_DATA CL_CLK CL_VREF CL_RSTB CL_PWROK AR7 AN10 AN11 AN9 JTAG_TDI JTAG_TDO JTAG_TCK JTAG_TMS AN17 B45 AW44 AN16 AD42 W30 U32 R42 BE44 BE2 BD45 BD1 A44 AK15 B14 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC18 NC19 MISC 38 38 38 VGA U47E C V_1P1_CORE R664 1KR0402 CL_VREF_MCH R665 464R1%0402-RH C666 C0.01u16X0402 CRT_HSYNC CRT_VSYNC D14 MCH_HSYNC C14 MCH_VSYNC CRT_RED CRT_GREEN CRT_BLUE CRT_IRTN B18 VGA_RED D18 VGA_GRN C18 VGA_BLU F13 CRT_DDC_DATA CRT_DDC_CLK B15 DPL_REFCLKINP DPL_REFCLKINN DPL_REFSSCLKINP DPL_REFSSCLKINN E15 D15 G8 G9 R670 AN6 AR4 K15 ICHSYNC# HDA_BCLK HDA_RSTB HDA_SDI HDA_SDO HDA_SYNC AU4 AV4 AU2 AV1 AU3 RSVD12 RSVD13 RSVD14 RSVD15 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD23 RSVD24 RSVD25 RSVD26 RSVD27 RSVD28 R650 R651 R652 R653 R654 J11 F11 P43 R668 P42 R669 A45 B2 BE1 BE45 R15 R14 T15 T14 AB15 R32 R31 U31 U30 L11 L13 HSYNC VSYNC 16 16 D 33 33 33 Close MCH VGA_RED VGA_GRN VGA_BLU R179 R180 R181 150R1%0402 150R1%0402 150R1%0402 MCH_DDC_DATA 16 MCH_DDC_CLK 16 1KR1%0402 CK_96M_DREF CK_96M_DREF# DPL_REFSSCLKIN_DP DPL_REFSSCLKIN_DN RSTINB PWROK ICH_SYNCB DDPC_CTRLCLK DDPC_CTRLDATA DPRSTPB SLPB VGA_RED VGA_GRN VGA_BLU L15 MCH_DDC_DATA M15 MCH_DDC_CLK DAC_IREF W10/S6 39R0402 39R0402 R248 R246 R249 CK_96M_DREF 38 CK_96M_DREF# 38 DPL_REFSSCLKIN_DP DPL_REFSSCLKIN_DN 0R0402 PLTRST# PWRGD ICH_SYNC# VCC3 38 38 MCH_DDC_DATA R242 MCH_DDC_CLK R243 2.2KR0402 2.2KR0402 13,32 14,17,32 14 0R0402 0R0402 0R0402 0R0402 0R0402 0R0402 0R0402 T26 T27 H_COMP5_R PM_SLP_N EMI Close MCH 3,14 VGA_RED VGA_GRN VGA_BLU C736 C737 C738 C X_C10p50N0402 X_C10p50N0402 X_C10p50N0402 VCC3 R663 X_10KR0402 INTEL-AC82G45-A3-HF B B A A MICRO-STAR INT'L CO.,LTD Title Eaglelake - VGA , MSIC Size Document Number Custom Date: Rev 31 MS-AE111 Sheet Tuesday, March 09, 2010 of 54 V_1P1_CORE VCC3 C370 C0.1u16Y0402 VCCA_DPLLA L16 0.1u50mA C188 X_C10u10Y0805 C206 C0.1u16Y0402 V_FSB_VTT D VCC3 V_1P1_CORE V_3P3_DAC_FILTERED VCCA_DPLLB L34 0.1u50mA L13 0.1u50mA C362 C10u10Y0805 C179 X_C10u10Y0805 C364 C0.1u16Y0402 C177 C0.1u16Y0402 L33 0.1u50mA C361 C0.1u16Y0402 V_1P1_CORE V_1P1_HPL V_1P1_CORE L32 C C351 C0.1u16Y0402 H_VCCPLL H_VCCPLL R357 VCCA_HPLL 0.1u50mA C0.1u16Y0402 VCCDQ_CRT 0R0402 V_1P1_CORE C220 V_1P1_CORE VCCDQ_CRT B16 A21 B22 B12 U33 VCCAPLL_EXP VCCA_MPLL VCCA_HPLL VCCDPLL_EXP VCCD_HPLL VCCA_DPLLA VCCA_DPLLB D20 C20 VCCA_DPLLA VCCA_DPLLB V_3P3_DAC_FILTERED D19 B19 VCCA_DAC VCCA_DAC E19 A17 VCC3_3 VCCA_EXP C667 V_1P1_CORE V_1P5_ICH C207 C0.22u16X C221 C0.1u16Y0402 VCCA_MPLL VCC3 R674 R366 R371 R380 0R0402 X_0R0402 X_0R0402 X_18R R675 X_15R C374 X_C0.1u16Y0402 V_1P1_CORE V_CKDDR POWER R311 1R0402 R318 1R0402 C372 C1u10X AG2 VCCAVRM_EXP AR2 B17 VCC_HDA VSS 0R0402 T22 T23 AP44 AT45 AV44 AY40 BA41 BB39 BD21 BD25 BD29 BD34 BD38 BE23 BE27 BE31 BE36 VCC_DDR V_CKDDR AK32 AL31 AL32 AM31 AM30 VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM VCC_SM C V_1P1_CORE VCC_SMCLK VCC_SMCLK VCC_SMCLK VCC_SMCLK VCCCML_DDR B C380 C0.1u16Y0402 V_CK_DDR VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL VCC_CL 1U500m_0805-RH R381 T24 T25 T26 T27 T29 U21 U22 U23 U24 U25 U26 U27 U29 W19 W21 W23 W25 W27 W29 Y20 Y22 Y24 Y26 D VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC VCC VCC VCC VCC VCC VCC AJ1 AJ2 AK2 AK3 AK4 AK13 AK12 AK11 AK10 AK9 AK8 AK7 AK6 AJ14 AJ13 AJ12 AJ11 AJ10 AJ9 AJ8 AJ7 AJ6 AG15 AF15 AF14 AE15 AE14 AD15 AD14 AC15 AB14 AA15 AA14 Y15 Y14 W15 U15 U14 AF3 AC4 V4 P3 L3 H4 F9 C375 C10u10Y0805 INTEL-AC82G45-A3-HF AK14 AJ15 AM29 AM26 AM25 AM24 AM22 AM21 AM20 AM17 AM16 AM15 AL30 AK31 AJ32 AF32 AE33 AE32 AD33 AD32 AB33 AB32 AA33 AA32 Y33 Y32 AP2 AP1 AM4 AM3 AM2 AL29 AL27 AL26 AL25 AL24 AL23 AL22 AL21 AL20 AL19 AL17 AL16 AL15 AL14 AL12 AL11 AL10 AL9 AL8 AL7 AL6 AL5 AL4 AL2 AL1 AK30 AK29 AK27 AK26 AK25 AK24 AK23 AK22 AK21 AK20 AK19 AK17 AK16 AJ31 AJ30 AG31 AG30 AF31 AE31 AD31 AC31 AB31 AA31 Y31 AJ29 AJ27 Y30 Y29 W31 L27 V_1P1_CORE X_C4.7u10Y0805 B VCC_DDR VTT_FSB VTT_FSB VTT_FSB B20 VCCA_EXP 0.1u50mA R23 R24 R22 VCCA_GPLL VCCA_MPLL VCCA_HPLL VCCA_GPLLD V_1P1_HPL VCC3 C309 C0.1u25Y L17 VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VTT_FSB VCCA_GPLLD 0.1u50mA R671 X_200R1%0402 L41 A25 B25 B26 C24 C26 D22 D23 D24 E23 F21 F22 G21 G22 H21 H22 J21 J22 K21 K22 L21 L22 M21 M22 N20 N21 N22 P20 P21 P22 P24 R20 R21 VCC VCC C365 C10u10Y0805 EAGLELAKE_DDR2 U47F VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC R673 39.2R1% V_1P1_CORE VCCA_EXP 0.1u50mA VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC L35 AA19 AA21 AA23 AA25 AA27 AA29 AA30 AB20 AB22 AB24 AB26 AB29 AB30 AC16 AC17 AC19 AC21 AC23 AC25 AC27 AC29 AD16 AD17 AD20 AD22 AD24 AD26 AD29 AE16 AE17 AE19 AE21 AE23 AE25 AE27 AE29 AF16 AF17 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF29 AG16 AG17 AG20 AG22 AG24 AG26 AG29 AJ16 AJ17 AJ19 AJ21 AJ23 AJ25 R25 R26 R27 R29 T21 R672 40.2R1% V_1P1_CORE V_1P1_CORE VCCAGPLL L11 1U500m_0805-RH R146 1R0402 R144 1R0402 VCCA_GPLL V_1P1_CORE C202 A C0.1u16Y0402 V_1P1_CORE VCC_DDR V_1P1_CORE MCH MEMORY DECOUPLING Place close to GMCH V_FSB_VTT V_FSB_VTT C305 C10u10Y0805 C318 C0.1u16Y0402 C109 C0.1u16Y0402 C501 C2.2u6.3Y C128 C1u6.3Y0402-RH C287 C10u10Y0805 C300 C10u10Y0805 C299 C0.1u16Y0402 C110 C0.1u16Y0402 C532 C2.2u6.3Y C131 C1u6.3Y0402-RH C290 C0.1u16Y0402 C151 C10u10Y0805 C321 C0.1u16Y0402 C117 C0.1u16Y0402 C538 C2.2u6.3Y C133 C1u6.3Y0402-RH C298 C0.1u16Y0402 C138 C10u10Y0805 C107 C0.1u16Y0402 C118 C0.1u16Y0402 C517 C2.2u6.3Y C282 C1u6.3Y0402-RH C301 C0.1u16Y0402 C303 C10u10Y0805 C289 C0.1u16Y0402 C120 C0.1u16Y0402 C539 C2.2u6.3Y C285 C1u6.3Y0402-RH C302 C0.1u16Y0402 C288 C10u10Y0805 C314 C0.1u16Y0402 C123 C0.1u16Y0402 C286 C1u6.3Y0402-RH C149 C10u10Y0805 C158 C0.1u16Y0402 C125 C0.1u16Y0402 C165 C10u10Y0805 C319 C0.1u16Y0402 C127 C0.1u16Y0402 C150 C10u10Y0805 C153 C10u10Y0805 A MICRO-STAR INT'L CO.,LTD Title Eaglelake - Power Size Document Number Custom Date: MS-AE111 Tuesday, March 09, 2010 Rev 31 Sheet of 54 D C VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS GND VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS N8 N38 N36 N33 N30 N29 N26 N16 N13 N11 M44 M25 M24 M1 L9 L8 L4 L39 L35 L30 L26 L20 L16 L10 K45 K33 K29 K24 K20 K17 K13 K11 J9 J8 J5 J4 J37 J3 H9 H8 H7 H44 H38 H33 H31 H30 H25 H20 H16 H15 H13 H11 H1 G35 G3 G29 G26 G24 G17 G11 F8 F45 F42 F4 F30 F2 F16 E5 E41 E31 E3 D7 D6 D39 D26 D25 D21 D16 D11 C5 C3 VSS VSS VSS VSS VSS VSS VSS VSS VSS BE40 BE34 BE29 BE25 BE21 BE19 BE15 BE10 BD8 VSS VSS BD17 BD12 NC14 NC15 NC16 NC17 AD30 AC30 AF30 AE30 D C B AJ36 AJ39 AJ44 AJ45 AK35 AK38 AK39 AL38 AL44 AL45 AN21 AN22 AN24 AN25 AN26 AN33 AN36 AN38 AN7 AP20 AP21 AP22 AP24 AP25 AP29 AP45 AR10 AR11 AR13 AR16 AR26 AR3 AR31 AR33 AR35 AR39 AR8 AR9 AT1 AT11 AT13 AT17 AT2 AT24 AT29 AT35 AU20 AU22 AU25 AU30 AU35 AU5 AU6 AU9 AV11 AV13 AV15 AV16 AV2 AV21 AV30 AV33 AV38 AV6 AV8 AV9 AW11 AW17 AW20 AW22 AW24 AW26 AW3 AW30 AY1 AY15 AY16 AY21 AY25 AY30 AY45 B10 B21 B27 B29 B34 BA23 BA5 BB21 BB25 BB28 BB6 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS B VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A12 A15 A19 A27 A31 A36 A40 A8 AA1 AA11 AA12 AA13 AA16 AA17 AA20 AA22 AA24 AA26 AA34 AA38 AA40 AA44 AA8 AB11 AB12 AB16 AB17 AB19 AB21 AB23 AB25 AB27 AB34 AB36 AB39 AB4 AB6 AB7 AB8 AC20 AC22 AC24 AC26 AC45 AC5 AD12 AD19 AD21 AD23 AD25 AD27 AD3 AD34 AD36 AD39 AD6 AD9 AE1 AE11 AE12 AE13 AE20 AE22 AE24 AE26 AE34 AE38 AE40 AE44 AE8 AF10 AF11 AF12 AF13 AF33 AF35 AF39 AF6 AF7 AG19 AG21 AG23 AG25 AG27 AG45 AG5 AH2 AH3 AH4 AJ20 AJ22 AJ24 AJ26 VSS VSS U47G A3 A6 A43 B44 C1 C45 F1 BC1 BC45 BD2 BD44 BE3 BE43 Y9 Y39 Y35 Y3 Y27 Y25 Y23 Y21 Y2 Y19 Y17 Y16 Y13 Y12 Y11 Y10 W5 W45 W44 W26 W24 W22 W20 W2 W17 W16 W1 U8 U44 U39 U36 U20 U19 U17 U16 U13 U12 U11 U1 T9 T8 T7 T6 T40 T4 T38 T35 T33 T32 T31 T30 T3 T20 T19 T17 T16 T13 T12 T11 T10 R8 R5 R45 R38 R30 R2 R19 R17 R16 R12 R11 P31 P26 P25 P17 P16 C16 BD43 A A INTEL-AC82G45-A3-HF MICRO-STAR INT'L CO.,LTD Title Eaglelake - GND Size Document Number Custom Date: Rev 31 MS-AE111 Tuesday, March 09, 2010 Sheet 10 of 54 B C D E COMPONENTS SHOWN ARE EXAMPLES ONLY AND NOT NECESSARILY QUALIFIED U95B DPD I2C 0B change to SMBUS R465 R466 11,14,20,22,25,38 SMBCLK_MAIN 11,14,20,22,25,38 SMBDATA_MAIN X_0R0402 X_0R0402 AK26 AJ26 GGPIO5 42 GGPIO5 GGPIO0 GGPIO1 GGPIO2 3.1 modify R1077 10KR0402 R0402 AK24 GPIO_0 GPIO_1 GPIO_2 GPIO_3_SMBDATA GPIO_4_SMBCLK GPIO_5_AC_BATT GPIO_6 GPIO_7_BLON GPIO_8_ROMSO GPIO_9_ROMSI GPIO_10_ROMSCK GPIO_11 GPIO_12 GPIO_13 GPIO_14_HPD2 GPIO_15_PWRCNTL_0 GPIO_16_SSIN GPIO_17_THERMAL_INT GPIO_18_HPD3 GPIO_19_CTF GPIO_20_PWRCNTL_1 GPIO_21_BB_EN GPIO_22_ROMCSB GPIO_23_CLKREQB JTAG_TRSTB JTAG_TDI JTAG_TCK JTAG_TMS JTAG_TDO GENERICA GENERICB GENERICC GENERICD GENERICE_HPD4 GENERICF GENERICG DAC1 HPD1 R504 499R1%0402 VREFG = 1.80 V / (or 0.60 V typ) Park: (1.8V@75mA DPLL_PVDD) +1.8V_REG L43 M2:(1.8V@120mA DPLL_PVDD) DPLL_PVDD 470L1.5A-150-RH C775 C771 C778 R509 Park: (1.0V@125mA DPLL_VDDC) M2: (1.1V@300mA DPLL_VDDC) 249R1%0402 C0.1u16Y0402 PLL/CLOCK C773 C782 C774 C10u10Y0805 X_C1u6.3Y0402-RH C0.1u16Y0402 C779 C22p50N0402 C780 C22p50N0402 470L1.5A-150-RH AM32 AN32 DPLL_PVDD DPLL_PVSS AN31 DPLL_VDDC AV33 AU34 XTALIN XTALOUT DPLL_VDDC L37 VREFG C781 X_C10u10Y0805 C1u6.3Y0402-RH C0.1u16Y0402 +1_1VRUN AH13 XTALIN R506 0R0402 XTALOUT R507 0R0402 Y9 27MHZ20P_S-3 R514 1MR0402 25 M92_THRMDA 25 M92_THRMDC M92_THRMDA M92_THRMDC AF29 AG29 DPLUS DMINUS +1.8V_REG X_COPPER JNC6 TSVDD (1.8V@20mA TSVDD) C776 JNC10 C777 AK32 AJ32 AJ33 AR32 AT31 TX5P_DPB0P TX5M_DPB0N AT33 AU32 TXCCP_DPC3P TXCCM_DPC3N AU14 AV13 TXCCP_DPC3P TXCCM_DPC3N TX0P_DPC2P TX0M_DPC2N AT15 AR14 TX0P_DPC2P TX0M_DPC2N C325 C350 C0.1u10X0402 C0.1u10X0402 DL_TMDS_TX0P DL_TMDS_TX0N DL_TMDS_TX0P 48 DL_TMDS_TX0N 48 TX1P_DPC1P TX1M_DPC1N AU16 AV15 TX1P_DPC1P TX1M_DPC1N C360 C424 C0.1u10X0402 C0.1u10X0402 DL_TMDS_TX1P DL_TMDS_TX1N DL_TMDS_TX1P 48 DL_TMDS_TX1N 48 TX2P_DPC0P TX2M_DPC0N AT17 AR16 TX2P_DPC0P TX2M_DPC0N C425 C426 C0.1u10X0402 C0.1u10X0402 TXCDP_DPD3P TXCDM_DPD3N AU20 AT19 TX3P_DPD2P TX3M_DPD2N AT21 AR20 TX3P_DPD2P TX3M_DPD2N C429 C430 C0.1u10X0402 C0.1u10X0402 DL_TMDS_TX3P DL_TMDS_TX3N DL_TMDS_TX3P 48 DL_TMDS_TX3N 48 TX4P_DPD1P TX4M_DPD1N AU22 AV21 TX4P_DPD1P TX4M_DPD1N C433 C436 C0.1u10X0402 C0.1u10X0402 DL_TMDS_TX4P DL_TMDS_TX4N DL_TMDS_TX4P 48 DL_TMDS_TX4N 48 TX5P_DPD0P TX5M_DPD0N AT23 AR22 TX5P_DPD0P TX5M_DPD0N C437 C438 C0.1u10X0402 C0.1u10X0402 DL_TMDS_TX5P DL_TMDS_TX5N DL_TMDS_TX5P 48 DL_TMDS_TX5N 48 C256 C258 2X_COPPER L30 C758 C10u10Y0805 C1u6.3Y0402-RH (1.8V@100mA VDD1DI) D VDD1DI G S Q49 N-2N7002_SOT23-1 C761 C760 120L500mA-150 C762 C10u10Y0805 C1u6.3Y0402-RH C0.1u16Y0402 L63 DL_TMDS_TXCP DL_TMDS_TXCN C0.1u10X0402 C0.1u10X0402 DL_TMDS_TXCP 48 DL_TMDS_TXCN 48 DL_TMDS_TX2P DL_TMDS_TX2N DL_TMDS_TX0N R33 (1.8V@2mA A2VDDQ) X_220R0402DL_TMDS_TX0P DL_TMDS_TX2P 48 DL_TMDS_TX2N 48 DL_TMDS_TX1N R35 X_220R0402DL_TMDS_TX1P DL_TMDS_TX2N R36 X_220R0402DL_TMDS_TX2P DL_TMDS_TX3N R37 X_220R0402DL_TMDS_TX3P DL_TMDS_TX4N R41 X_220R0402DL_TMDS_TX4P DL_TMDS_TX5N R42 X_220R0402DL_TMDS_TX5P DL_TMDS_TXCN R43 X_220R0402DL_TMDS_TXCP A2VDDQ C621 120L500mA-150 C756 X_C1u6.3Y0402-RH X_C0.1u16Y0402 DGPU_VDD_3.3V L107 (3.3V@130mA A2VDD) 120L500mA-150 A2VDD C764 C0.1u16Y0402 3.1 modify TS_FDO TSVDD TSVSS 2X_COPPER THERMAL R RB AD39 AD37 VGA_R_DGPU 16 G GB AE36 AD35 VGA_G_DGPU 16 B BB AF37 AE38 HSYNC VSYNC AC36 AC38 RSET AB34 AVDD AVSSQ AD34 AE34 VDD1DI VSS1DI AC33 AC34 R2 R2B AC30 AC31 G2 G2B AD30 AD31 B2 B2B AF30 AF31 C Y COMP AC32 AD32 AF32 H2SYNC V2SYNC AD29 AC29 VDD2DI VSS2DI AG31 AG32 A2VDD AG33 A2VDDQ AD33 A2VSSQ AF33 DGPU_VDD_3.3V 8P4R-4.7KR0402 VGA_B_DGPU 16 VGA_HSYNC_DGPU 16,42 VGA_VSYNC_DGPU 16,42 R255 499R1%0402 AVDD DDC/AUX R2SET AA29 DDC1CLK DDC1DATA AM26 AN26 AUX1P AUX1N AM27 AL27 DDC2CLK DDC2DATA AM19 AL19 AUX2P AUX2N AN20 AM20 DDCCLK_AUX3P DDCDATA_AUX3N AL30 AM30 DDCCLK_AUX4P DDCDATA_AUX4N AL29 AM29 DDCCLK_AUX5P DDCDATA_AUX5N AN21 AM21 DDC6CLK DDC6DATA AJ30 AJ31 NC_DDCCLK_AUX7P NC_DDCDATA_AUX7N AK30 AK29 R225 R228 R229 1KR R521 Q33 10KR0402 C1129 R546 1KR 11/25 C772 C769 C770 X_C10p25N0402-RH-3 X_C10p25N0402-RH-3 X_C10p25N0402-RH-3 EMC Q32 G 17,24,26 RUN_ON JNC4 X_COPPER JTAG_TDI JTAG_TCK R1082 R1085 10KR0402 R0402 10KR0402 R0402 JTAG_TDO R1084 10KR0402 R0402 43 DC_19V RN24 3.1 modify R542 VGA_R_DGPU VGA_G_DGPU VGA_B_DGPU SMBCLK_MAIN SMBDATA_MAIN GFX_ALERT# +19V_OUT DC_19V VDD1DI TESTEN X_P-AO4413_SOIC8 JTAG_TRST R1081 R1080 10KR0402 R0402 X_10KR0402 R0402 JTAG_TMS 10KR0402 R0402 R1083 11/12 AMD recommend N-2N7002_SOT23-1 FOR MXM DESIGN: PLACE RGB 150 Ohm TERMINATION RESISTORS CLOSE TO ASIC DAC2 +1.8V_REG PLACE VREFG DIVIDER AND CAP CLOSE TO ASIC AV31 AU30 TX4P_DPB1P TX4M_DPB1N C1u25X0805-RH TX3P_DPB2P TX3M_DPB2N JNC12 VCC5 AVDD (1.8V@65mA AVDD) 120L500mA-150 C757 150R1%0402 GPIO21 pull dlown for park TXCBP_DPB3P TXCBM_DPB3N AR30 AT29 L31 HDMI0_TXD_P2 33 HDMI0_TXD_N2 33 150R1%0402 R515 10KR0402 GGPIO0 GGPIO1 GGPIO2 HDMI0_TXD_P2 HDMI0_TXD_N2 150R1%0402 AH20 AH18 AN16 AH23 AJ23 R508 0R0402 AC_OK_GPU AH17 AJ17 LVDS_BLON-G AK17 GGPIO8 AJ13 42 GGPIO8 GGPIO9 AH15 42 GGPIO9 GGPIO10 AJ16 GGPIO11 AK16 42 GGPIO11 GGPIO12 AL16 42 GGPIO12 GGPIO13 AM16 42 GGPIO13 AM14 35 HDMI1_HPDET AM13 29 GPIO15_PSW_0 TPJNC4JNC AK14 GFX_ALERT# TPJNC2 AG30 090526修改 HPD_3 AN14 48 HPD_3 AM17 AL13 29 GPIO20_PSW_1 R511 X_10KR0402 AJ14 GGPIO22 AK13 42 GGPIO22 DGPU_CLKREQ# AN13 42 DGPU_CLKREQ# JTAG_TRST AM23 JTAG DEBUG PORT JTAG_TDI AN23 JTAG_TCK AK23 JTAG_TMS AL24 JTAG_TDO AM24 DGPU_VDD_3.3V GENERICB R517 X_0R0402 AJ19 48 GENERICB R518 0R0402 AK19 R1078 X_10KR0402 R0402 AJ20 AK20 R1076 10KR0402 R0402 AJ24 R1079 AH26 AH24 X_10KR0402 R0402 42 42 42 AT27 AR26 +1.8V_REG 0B &2 exchange SCL SDA GENERAL PURPOSE I/O GPIO15 & GPIO20 VGA PWM TX2P_DPA0P TX2M_DPA0N HDMI0_TXD_P1 33 HDMI0_TXD_N1 33 HDMI0_TXD_P1 HDMI0_TXD_N1 DVPDATA20 DVPDATA21 DVPDATA22 DVPDATA23 AU26 AV25 150mA (1.8V@100mA VDD2DI) A2VDD 3.1 modify A2VDDQ A2VSSQ R411 3.1 modify JNC9 2X_COPPER VCC3_SB 715R1%0402 GGPIO9 R395 GGPIO10 R396 33R0402 33R0402 U48 X_MX25L8005M2C-15G-RH HOLD# VCC SI WP# SCK SO GND CS# C0.1u16Y0402 C1918 R397 R393 VCC3_SB S D Q120 R1071 100KR0402 R0402 +1.8V_REG R1073 HDMI R505 R516 X_0R0805 P-NDS352AP_SOT23-3-RH VCC5 DDCCLK_AUX3P DDCDATA_AUX3N VCC3 R502 R392 33R0402 R394 X_33R0402 GGPIO8 33R0402 GGPIO22 33R0402 VGA_CLK_DGPU 16 VGA_DATA_DGPU 16 CRT HDMI0_DDCSCL 33,35 HDMI0_DDCDAT 33,35 R572 2KR0402 DGPU_VDD_3.3V G 42 42 42 42 DPC TX1P_DPA1P TX1M_DPA1N HDMI0_TXC_P 33 HDMI0_TXC_N 33 HDMI0_TXD_P0 33 HDMI0_TXD_N0 33 C R512 X_10KR0402 DPB HDMI0_TXD_P0 HDMI0_TXD_N0 D DGPU_VDD_3.3V LVDS_BLON-G R513 X_10KR0402 DVPCNTL_MVP_0 DVPCNTL_MVP_1 DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 HDMI0_TXC_P HDMI0_TXC_N AT25 AR24 S 090722修改 For Park AR8 AU8 AP8 AW8 AR3 AR1 AU1 AU3 AW3 AP6 AW5 AU5 AR6 AW6 AU6 AT7 AV7 AN7 AV9 AT9 AR10 AW10 AU10 AP10 AV11 AT11 AR12 AW12 AU12 AP12 AU24 AV23 TX0P_DPA2P TX0M_DPA2N R391 R388 R389 R390 R382 R379 R290 R316 R378 R387 R386 R383 R384 R385 DPA TXCAP_DPA3P TXCAM_DPA3N 499R1%0402 499R1%0402 499R1%0402 499R1%0402 499R1%0402 499R1%0402 499R1%0402 499R1%0402 499R1%0402 499R1%0402 499R1%0402 499R1%0402 499R1%0402 499R1%0402 MUTI GFX 47KR0402 R0402 CheckSequence OPTIONAL RC NETWORK TO FINE TUNE POWER SEQUENCING R573 2KR0402 0R0402 0R0402 R231 R232 33R0402 DDCCLK_DAC1_R 33R0402 DDCDATA_DAC1_R DDCCLK_DAC1_R 48 DDCDATA_DAC1_R 48 Q119 N-PMBS3904_SOT23-RH B C2178 X_C0.1u16Y0402 C0402 E A M96 Only (NC on M92-M2) MICRO-STAR INT'L CO.,LTD X_C1u6.3Y0402-RH C0.1u16Y0402 Title 216-0729042 M92-M2_IO Size Document Number Custom Date: A B C D MS-AE111 Tuesday, March 09, 2010 E Rev 31 Sheet 40 of 54 A B C D E For DDR3,MVDDQ=1.5V 2A +MVDDQ U95F U95E PCIE_VDDR MEM I/O C788 C10u6.3X5-RH C42 C44 C793 C10u10Y0805 C45 C829 C831 C809 C1u6.3Y0402-RH C37 C841 C1u6.3Y0402-RH C0.1u10X0402 C876 C10u6.3X5-RH C33 C811 C1u6.3Y0402-RH C0.1u10X0402 C32 C846 C1u6.3Y0402-RH C0.1u10X0402 C27 C804 C1u6.3Y0402-RH C791 C1u6.3Y0402-RH C0.1u10X0402 C30 C855 C1u6.3Y0402-RH C821 C1u6.3Y0402-RHC0.1u10X0402 C31 C792 C1u6.3Y0402-RH C0.1u10X0402 C29 C795 C1u6.3Y0402-RH C0.1u10X0402 AC7 AD11 AF7 AG10 AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10 J7 J9 K11 K13 K8 L12 L16 L21 L23 L26 L7 M11 N11 P7 R11 U11 U7 Y11 Y7 C833 C10u10Y0805 VDDR1#1 VDDR1#2 VDDR1#3 VDDR1#4 VDDR1#5 VDDR1#6 VDDR1#7 VDDR1#8 VDDR1#9 VDDR1#10 VDDR1#11 VDDR1#12 VDDR1#13 VDDR1#14 VDDR1#15 VDDR1#16 VDDR1#17 VDDR1#18 VDDR1#19 VDDR1#20 VDDR1#21 VDDR1#22 VDDR1#23 VDDR1#24 VDDR1#25 VDDR1#26 VDDR1#27 VDDR1#28 VDDR1#29 VDDR1#30 VDDR1#31 VDDR1#32 VDDR1#33 VDDR1#34 PCIE +1.8V_REG VDDC_CT L47 (1.8V@110mA VDD_CT) 120L500mA-150 Pin AH29: Park為FB_GND R533 C784 C0.1u10X0402 DGPU_VDD_3.3V C796 C1000p50X0402 Park:(1.8V@60mA VDDR3) M2:(1.8V@50mA VDDR3) X_0R0402 C853 C0.1u10X0402 VDD_CT#1 VDD_CT#2 VDD_CT#3 VDD_CT#4 I/O C823 C1u6.3Y0402-RH AF23 AF24 AG23 AG24 VDDR3#1 VDDR3#2 VDDR3#3 VDDR3#4 AF13 AF15 AG13 AG15 VDDR5#1 VDDR5#2 VDDR5#3 VDDR5#4 AD12 AF11 AF12 AG11 VDDR4#1 VDDR4#2 VDDR4#3 VDDR4#4 VDDR5 VDDR5 for DVPDATA[0 11] (1.8V@170mA VDDR5) VDDR4 L68 LEVEL TRANSLATION AF26 AF27 AG26 AG27 VDDR4 R520 0R0402 120L500mA-150 C830 C802 C10u6.3X50805-RH-3 C1u6.3Y0402-RH C0.1u10X0402 L66 C786 VDDR4 for DVPDATA[12 23] (1.8V@170mA VDDR4) VDDR5 +MVDDQ 120L500mA-150 C816 C843 C785 L69 C10u6.3X50805-RH-3 C1u6.3Y0402-RH C0.1u10X0402 M96 ONLY VDDRHA C827 X_C1u6.3Y0402-RH X_120L500mA-150 L64 (1.8V@40mA PCIE_PVDD) 120L500mA-150 C851 PCIE_PVDD C847 M96 X_C1u6.3Y0402-RH PLL AB37 C838 (For M96/M92 SPV10 = VDDC) (For Park SPV10 =PCIE_VDDC) X_C10u6.3X50805-RH-3 C1u6.3Y0402-RH C0.1u10X0402 R522 GPU_CORE R523 +1_1VRUN C857 MPV18 L67 X_0R 0R0402 JNC11 For Park 090526修改 (0.95V-1.1V@120mA SPV10) SPV10 C848 470L1.5A-150-RH X_COPPER SPVSS C835 C790 C803 C1u6.3Y0402-RH SPV18 H7 H8 AM10 C787 C0.1u10X0402 PCIE_PVDD NC_MPV18#1 NC_MPV18#2 NC_SPV18 AN9 SPV10 AN10 SPVSS AA13 Y13 BBP#1 BBP#2 X_C10u6.3X50805-RH-3 C1u6.3Y0402-RH C0.1u10X0402 VDDCI L45 VDDRHB VSSRHB AND M92 ONLY SPV18 R519 0R0402 VDDRHA VSSRHA V12 U12 VDDRHB L48 X_120L500mA-150 MEM CLK M20 M21 PCIE_VDDR#1 PCIE_VDDR#2 PCIE_VDDR#3 PCIE_VDDR#4 PCIE_VDDR#5 PCIE_VDDR#6 PCIE_VDDR#7 PCIE_VDDR#8 AA31 AA32 AA33 AA34 V28 W29 W30 Y31 PCIE_VDDC#1 PCIE_VDDC#2 PCIE_VDDC#3 PCIE_VDDC#4 PCIE_VDDC#5 PCIE_VDDC#6 PCIE_VDDC#7 PCIE_VDDC#8 PCIE_VDDC#9 PCIE_VDDC#10 PCIE_VDDC#11 PCIE_VDDC#12 G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28 CORE POWER GND C819 C1u6.3Y0402-RH C0.1u10X0402 GND#101 GND#102 GND#103 GND#104 GND#105 GND#106 GND#107 GND#108 GND#109 GND#110 GND#111 GND#112 GND#113 GND#114 GND#115 GND#116 GND#117 GND#118 GND#119 GND#120 GND#121 GND#122 GND#123 GND#124 GND#125 GND#126 GND#127 GND#128 GND#129 GND#130 GND#131 GND#132 GND#133 GND#134 GND#135 GND#136 GND#137 GND#138 GND#139 GND#140 GND#141 GND#142 GND#143 GND#144 GND#145 GND#146 GND#147 GND#148 GND#149 GND#150 GND#151 GND#152 GND#153 GND#154 GND#155 GND#156 GND#157 GND#158 GND#159 GND#160 GND#161 GND#162 GND#163 GND#164 GND#165 GND#166 GND#167 GND#168 GND#169 GND#170 GND#171 GND#172 GND#173 GND#174 GND#175 GND#176 GND#1 GND#2 GND#3 GND#4 GND#5 GND#6 GND#7 GND#8 GND#9 GND#10 GND#11 GND#12 GND#13 GND#14 GND#15 GND#16 GND#17 GND#18 GND#19 GND#20 GND#21 GND#22 GND#23 GND#24 GND#25 GND#26 GND#27 GND#28 GND#29 GND#30 GND#31 GND#32 GND#33 GND#34 GND#35 GND#36 GND#37 GND#38 GND#39 GND#40 GND#41 GND#42 GND#43 GND#44 GND#45 GND#46 GND#47 GND#48 GND#49 GND#50 GND#51 GND#52 GND#53 GND#54 GND#55 GND#56 GND#57 GND#58 GND#59 GND#60 GND#61 GND#62 GND#63 GND#64 GND#65 GND#66 GND#67 GND#68 GND#69 GND#70 GND#71 GND#72 GND#73 GND#74 GND#75 GND#76 GND#77 GND#78 GND#79 GND#80 GND#81 GND#82 GND#83 GND#84 GND#85 GND#86 GND#87 GND#88 GND#89 GND#90 GND#91 GND#92 GND#93 GND#94 GND#95 GND#96 GND#97 GND#98 GND#99 GND#100 C1u6.3Y0402-RH C0.1u10X0402 F15 F17 F19 F21 F23 F25 F27 F29 F31 F33 F7 F9 G2 G6 H9 J2 J27 J6 J8 K14 K7 L11 L17 L2 L22 L24 L6 M17 M22 M24 N16 N18 N2 N21 N23 N26 N6 R15 R17 R2 R20 R22 R24 R27 R6 T11 T13 T16 T18 T21 T23 T26 U15 U17 U2 U20 U22 U24 U27 U6 V11 V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27 U13 V13 PCIE_VSS#1 PCIE_VSS#2 PCIE_VSS#3 PCIE_VSS#4 PCIE_VSS#5 PCIE_VSS#6 PCIE_VSS#7 PCIE_VSS#8 PCIE_VSS#9 PCIE_VSS#10 PCIE_VSS#11 PCIE_VSS#12 PCIE_VSS#13 PCIE_VSS#14 PCIE_VSS#15 PCIE_VSS#16 PCIE_VSS#17 PCIE_VSS#18 PCIE_VSS#19 PCIE_VSS#20 PCIE_VSS#21 PCIE_VSS#22 PCIE_VSS#23 PCIE_VSS#24 PCIE_VSS#25 PCIE_VSS#26 PCIE_VSS#27 PCIE_VSS#28 PCIE_VSS#29 PCIE_VSS#30 PCIE_VSS#31 PCIE_VSS#32 PCIE_VSS#33 PCIE_VSS#34 PCIE_VSS#35 A3 A37 AA16 AA18 AA2 AA21 AA23 AA26 AA28 AA6 AB12 AB15 AB17 AB20 AB22 AB24 AB27 AC11 AC13 AC16 AC18 AC2 AC21 AC23 AC26 AC28 AC6 AD15 AD17 AD20 AD22 AD24 AD27 AD9 AE2 AE6 AF10 AF16 AF18 AF21 AG17 AG2 AG20 AG22 AG6 AG9 AH21 AH29 AJ10 AJ11 AJ2 AJ28 AJ6 AK11 AK31 AK7 AL11 AL14 AL17 AL2 AL20 AL21 AL23 AL26 AL32 AL6 AL8 AM11 AM31 AM9 AN11 AN2 AN30 AN6 AN8 AP11 AP7 AP9 AR5 AW34 B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33 B7 B9 C1 C39 E35 E5 F11 F13 C1u6.3Y0402-RH C0.1u10X0402 AB39 E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39 BACK BIAS VDDC#1 VDDC#2 VDDC#3 VDDC#4 VDDC#5 VDDC#6 VDDC#7 VDDC#8 VDDC#9 VDDC#10 VDDC#11 VDDC#12 VDDC#13 VDDC#14 VDDC#15 VDDC#16 VDDC#17 VDDC#18 VDDC#19 VDDC#20 VDDC#21 VDDC#22 VDDC#23 VDDC#24 VDDC#25 VDDC#26 VDDC#27 VDDC#28 VDDC#29 VDDC#30 VDDC#31 VDDC#32 VDDC#33 VDDC#34 VDDC#35 VDDC#36 VDDC#37 VDDC#38 VDDC#39 VDDC#40 VDDC#41 VDDC#42 VDDC#43 VDDC#44 VDDC#45 VDDC#46 VDDC#47 VDDC#48 VDDC#49 VDDC#50 VDDC#51 VDDC#52 VDDC#53 VDDC#54 VDDC#55 VDDC#56 VDDC#57 VDDC#58 VDDC#59 VDDC#60 VDDC#61 VDDC#62 VDDC#63 VDDC#64 VDDC#65 VDDC#66 VDDC#67 VDDC#68 VDDC#69 VDDC#70 VDDC#71 VDDC#72 VDDC#73 VDDC#74 ISOLATED VDDCI#1 CORE I/O VDDCI#2 VDDCI#3 VDDCI#4 AA15 AA17 AA20 AA22 AA24 AA27 AB13 AB16 AB18 AB21 AB23 AB26 AB28 AC12 AC15 AC17 AC20 AC22 AC24 AC27 AD13 AD16 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 M16 M18 M23 M26 N15 N17 N20 N22 N24 N27 R13 R16 R18 R21 R23 R26 T15 T17 T20 T22 T24 T27 U16 U18 U21 U23 U26 V15 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28 AH27 AH28 M15 N13 R12 T12 120L500mA-150 JNC41 NC_0603 220L2A-50-RH C822 C799 C815 C826 C1u6.3Y0402-RH C1u6.3Y0402-RH C1u6.3Y0402-RH C10u6.3X5-RH For M96/M92 PCIE_VDDC = 1.1V PCIE_VDDC (1.1V@1920mA PCIE_VDDC) C840 C1u6.3Y0402-RH C856 C807 C0.1u10X0402 C1u6.3Y0402-RH C817 JNC42 C836 C1u6.3Y0402-RH +1_1VRUN C808 NC_0603 C789 C10u6.3X5-RH C1u6.3Y0402-RH C10u6.3X5-RH GPU_CORE SEE DATABOOK FOR REQUIRED EDP C849 C832 C1u6.3Y0402-RH C845 C834 C797 C1u6.3Y0402-RH C1u6.3Y0402-RH C839 C1u6.3Y0402-RH C1u6.3Y0402-RH C805 C1u6.3Y0402-RH C1u6.3Y0402-RH C818 C825 C1u6.3Y0402-RH C801 C1u6.3Y0402-RH C1u6.3Y0402-RH C852 C810 C842 C1u6.3Y0402-RH C1u6.3Y0402-RH C813 C1u6.3Y0402-RH C1u6.3Y0402-RH C820 C824 C1u6.3Y0402-RH C1u6.3Y0402-RH C828 C858 C10u6.3X50805-RH-3 C1u6.3Y0402-RH C806 C837 C812 C10u6.3X50805-RH-3 C10u6.3X50805-RH-3 C844 C798 C10u6.3X50805-RH-3 C10u6.3X50805-RH-3 C794 C10u6.3X50805-RH-3 C10u6.3X50805-RH-3 VDDCI (For Park DDR3, 0.95V-1.1V@4A VDDCI) GPU_COREI L70 (For M96/92, 0.95V-1.1V@2A VDDCI) 220L2A-50-RH C850 (For Park 1.8V@75mA SPV18) C800 C814 C10u6.3X50805-RH-3 C1u6.3Y0402-RH 216-0729042 VSS_MECH#1 VSS_MECH#2 VSS_MECH#3 C860 C0.1u10X0402 +1.8V_REG L65 (1.8V@504mA PCIE_VDDR) C1u6.3Y0402-RH C854 C0.1u10X0402 SPVSS A39 AW1 AW39 090525修改 MPV18 L46 216-0729042 (For Park 1.8V@75mA MPV18) 120L500mA-150 C859 C0.1u10X0402 For Park 090526修改 MICRO-STAR INT'L CO.,LTD Title M92-M2_Power Size Document Number Custom Date: A B C D MS-AE111 Tuesday, March 09, 2010 E Rev 31 Sheet 41 of 54 A B Park:(1.8V@130mA DPA_VDD18) M2:(1.8V@110mA DPA_VDD18) +1.8V_REG DP C/D POWER 1 Park:(1.1V@110mA DPC_VDD10) M2:(1.1V@200mA DPC_VDD10) DP A/B POWER X_COPPER AP20 AP21 NC_DPC_VDD18#1 NC_DPC_VDD18#2 NC_DPA_VDD18#1 NC_DPA_VDD18#2 AP13 AT13 DPC_VDD10#1 DPC_VDD10#2 DPC_VSSR#1 DPC_VSSR#2 DPC_VSSR#3 DPC_VSSR#4 DPC_VSSR#5 DPA_VDD10#1 DPA_VDD10#2 DPA_VSSR#1 DPA_VSSR#2 DPA_VSSR#3 DPA_VSSR#4 DPA_VSSR#5 Park:(1.8V@130mA L74 DPA_VDD18) M2:(1.8V@110mA DPA_VDD18) AP22 AP23 X_COPPER L79 +1_1VRUN +1.8V_REG X_COPPER 120L500mA-150 AP31 AP32 C0.1u16Y0402 C1u6.3Y0402-RH C10u10Y0805 C1122 C1120 NC_DPD_VDD18#1 NC_DPD_VDD18#2 +1.8V_REG NC_DPB_VDD18#1 NC_DPB_VDD18#2 AP25 AP26 DPD_VDD10#1 DPD_VDD10#2 DPB_VDD10#1 DPB_VDD10#2 AN33 AP33 AN19 AP18 AP19 AW20 AW22 DPD_VSSR#1 DPD_VSSR#2 DPD_VSSR#3 DPD_VSSR#4 DPD_VSSR#5 DPB_VSSR#1 DPB_VSSR#2 DPB_VSSR#3 DPB_VSSR#4 DPB_VSSR#5 AN29 AP29 AP30 AW30 AW32 DGPU_CLKREQ#? X_COPPER +1.8V_REG L80 DPE_VDD18 AH34 AJ34 120L500mA-150 C861 C862 X_C10u10Y0805 X_C1u6.3Y0402-RH C0.1u16Y0402 L84 Park: (1.1V@120mA DPE_VDD10) M2:(1.1V@170mA DPE_VDD10) 120L500mA-150 C866 C868 DP PLL POWER DPA_PVDD DPA_PVSS AU28 AV27 C871 R595 0R0402 DPE_VDD10#1 DPE_VDD10#2 DPB_PVDD DPB_PVSS AV29 AR28 AN34 AP39 AR39 AU37 AW35 DPE_VSSR#1 DPE_VSSR#2 DPE_VSSR#3 DPE_VSSR#4 DPE_VSSR#5 DPC_PVDD DPC_PVSS AU18 AV17 (1.8V@20mA DPA_PVDD) DPE_VDD10 AK33 AK34 DPF_VDD10#1 DPF_VDD10#2 AF39 AH39 AK39 AL34 AM34 DPF_VSSR#1 DPF_VSSR#2 DPF_VSSR#3 DPF_VSSR#4 DPF_VSSR#5 AM39 DPEF_CALR Park: (1.1V@120mA DPF_VDD10) DPE_PVDD DPE_PVSS AM37 AN38 DPB_PVDD DPC_PVDD 10KR0402 40 GGPIO2 GGPIO2 R770 10KR0402 40 GGPIO5 GGPIO5 R783 10KR0402 40 GGPIO8 GGPIO8 R774 10KR0402 40 GGPIO9 GGPIO9 R765 X_10KR0402 40 GGPIO11 GGPIO11 R773 10KR0402 40 GGPIO12 GGPIO12 R781 X_10KR0402 40 GGPIO13 GGPIO13 R779 X_10KR0402 40 GGPIO22 GGPIO22 R766 X_10KR0402 R769 X_10KR0402 R775 X_10KR0402 R777 X_10KR0402 40 DGPU_CLKREQ# DGPU_CLKREQ# 16,40 VGA_HSYNC_DGPU C872 C874 C0.1u16Y0402 C1u6.3Y0402-RH C10u10Y0805 DVPDATA20 40 DVPDATA21 40 DVPDATA22 40 DVPDATA23 C869 (1.8V@20mA DPC_PVDD) (1.8V@20mA DPD_PVDD) L78 C1119 C867 PIN TX_PWRS_ENB GPIO0 TX_DEEMPH_EN GPIO1 BIF_GEN2_EN GPIO2 L82 X_10KR0402 R780 X_10KR0402 R768 X_10KR0402 R764 X_10KR0402 090525修改 L75 C1118 RECOMMENDED SETTINGS 0= DO NOT INSTALL RESISTOR = INSTALL 10K RESISTOR X = DESIGN DEPENDANT NA = NOT APPLICABLE DESCRIPTION OF DEFAULT SETTINGS Transmitter Power Savings Enable 0:50% Tx output swing for mobile mode 1:full Tx output swing (defuat setting for desktop) 2 STRAP_BIF_CLK_PM_EN X_COPPER GPIO8 PCI Express Transmitter De-emphasis Enable 0:Tx de-emphasis disabled for mobile mode 1:Tx de-emphasis enable (defuat setting for desktop) = Advertises the PCI-E device as 2.5 GT/s capatle at power-on = Advertises the PCI-E device as 5.0 GT/s capatle at power-on 5.0 GT/s Capabilly will be controlled by Enable CLKREQ# Power Mangement 0- CLKREQ# Power Mangement capability is disable 1- CLKREQ# Power Mangement capability is ebable BIF_VGA DIS GPIO9 VGA ENABLED BIF_RX_PLL_CALIB_BP GPIO21 BIF_RX_PLL_CALIB_BP Enable extrnal BIOS ROM device 0- disable extrnal BIOS ROM device 1-enable extrnal BIOS ROM device L73 120L500mA-150 C864 GPIO_22_ROMCSB BIOS_ROM_EN 216-0729042 R782 ALLOW FOR PULLUP PADS FOR THESE STRAPS AND IF THESE GPIOS ARE USED, THEY MUST NOT CONFLICT DURING RESET X_COPPER (1.8V@20mA DPE_PVDD) C865 7/3 update C1026 X_COPPER C1028 C1116 CONFIGURATION STRAPS STRAPS C0.1u16Y0402 C1u6.3Y0402-RH C10u10Y0805 DPE_PVDD +1.8V_REG 40 C870 (1.8V@20mA DPB_PVDD) C1017 DPE_PVDD AL38 AM35 10KR0402 R772 X_COPPER C873 C875 C0.1u16Y0402 C1u6.3Y0402-RH C10u10Y0805 DPD_PVDD NC_DPF_PVDD NC_DPF_PVSS R767 150R1%0402 AV19 AR18 DPF_VDD18#1 DPF_VDD18#2 L81 150R1%0402 C0.1u16Y0402 C1u6.3Y0402-RH C10u10Y0805 C10u10Y0805 DPE_VDD18 DPD_PVDD DPD_PVSS R776 GGPIO1 +1.8V_REG C1u6.3Y0402-RH AF34 AG34 GGPIO0 GGPIO1 3.1 modify AL33 AM33 GGPIO0 40 C1124 X_COPPER C0.1u16Y0402 C10u10Y0805 X_C1u6.3Y0402-RH C0.1u16Y0402 DP E/F POWER DPE_VDD18#1 DPE_VDD18#2 DPAB_CALR R771 Park:(1.1V@200mA DPB_VDD10) M2:(1.1V@200mA DPB_VDD10) PCIE_VDDC L71 C863 DPE_VDD10 +1_1VRUN DPCD_CALR AW28 40 16,40 VGA_VSYNC_DGPU DPA_PVDD (1.8V@200mA DPE_VDD18) (1.8V@200mA DPF_VDD18) GPIO5? Park:(1.8V@130mA DPA_VDD18) M2:(1.8V@110mA DPA_VDD18) AP14 AP15 R778 AW18 150R1%0402 Park:(1.1V@110mA DPA_VDD10) M2:(1.1V@200mA DPA_VDD10) C1121 120L500mA-150 C10u10Y0805 PCIE_VDDC AN27 AP27 AP28 AW24 AW26 L72 Park:(1.1V@110mA DPC_VDD10) M2:(1.1V@200mA DPC_VDD10) AN24 AP24 E DGPU_VDD_3.3V PIN STRAPS For M96/92, DPx_VDD10 = 1.1V For M97 DPx_VDD10 = 1.0V L77 AN17 AP16 AP17 AW14 AW16 +1.8V_REG D Park:(1.8V@130mA DPA_VDD18) M2:(1.8V@110mA DPA_VDD18) L76 X_COPPER L83 U95H L85 +1_1VRUN C DV DATA 23 22 21 20 SAMSUNG 0 0 32*16 Hynix 0 32*16 SAMSUNG 0 64*16 Hynix 0 64*16 config(2: 1: 0) GPIO[13: 12: 11] Mem type DVDATA[20,21,22] VIP_DEVICE_STRAP_ENA V2SYNC RSVD RSVD AUD[1] AUD[0] H2SYNC GENERICC HSYNC VSYNC GPIO 9,13,12,11(CONFIG 3,2,1,0) a> if BIOS_ROM_EN =1 ,then Config [3:0] defines the rom type b> if BIOS_ROM_EN =0 ,then Config [3:0] defines the Aperture size if VIP_DEVICE_STRAP_ENA is set to '1',then this pin is used to sense whether a VIP slave device is connected to the VIP Host interface.if VIP_DEVICE_STRAP_ENA is set to '0' then this pin is not used as a strap at all (i.e its value during reset is unimportant), and it can be used as a regular GPIO 0 256MB 0 vendor 0 1 MICRO-STAR INT'L CO.,LTD Title M92-M2_Power straps Size Document Number Custom Date: A B C D MS-AE111 Tuesday, March 09, 2010 E Rev 31 Sheet 42 of 54 B C D U95C +MVDDQ M2:DDRII = 0.5*VDDR1 Park:DDRII = 0.7*VDDR1 R795 40.2R1% R796 100R0402 L18 L20 +MVDDQ For Park 090717修改 +MVDDQ R827 R789 R828 R800 R801 R799 243R1%0402 243R1%0402 243R1%0402 243R1%0402 243R1%0402 243R1%0402 L27 N12 AG12 M12 M27 AH12 MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 A_BA2 A_BA0 A_BA1 MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8 MAA_9 MAA_10 MAA_11 MAA_12 MAA_13/BA2 MAA_14/BA0 MAA_15/BA1 G24 J23 H24 J24 H26 J26 H21 G21 H19 H20 L13 G16 J16 H16 J17 H17 DQMA_0 DQMA_1 DQMA_2 DQMA_3 DQMA_4 DQMA_5 DQMA_6 DQMA_7 A32 C32 D23 E22 C14 A14 E10 D9 DQMA#0 DQMA#1 DQMA#2 DQMA#3 DQMA#4 DQMA#5 DQMA#6 DQMA#7 QSA_0/RDQSA_0 QSA_1/RDQSA_1 QSA_2/RDQSA_2 QSA_3/RDQSA_3 QSA_4/RDQSA_4 QSA_5/RDQSA_5 QSA_6/RDQSA_6 QSA_7/RDQSA_7 C34 D29 D25 E20 E16 E12 J10 D7 QSA0 QSA1 QSA2 QSA3 QSA4 QSA5 QSA6 QSA7 QSA_0B/WDQSA_0 QSA_1B/WDQSA_1 QSA_2B/WDQSA_2 QSA_3B/WDQSA_3 QSA_4B/WDQSA_4 QSA_5B/WDQSA_5 QSA_6B/WDQSA_6 QSA_7B/WDQSA_7 A34 E30 E26 C20 C16 C12 J11 F8 QSA#0 QSA#1 QSA#2 QSA#3 QSA#4 QSA#5 QSA#6 QSA#7 ODTA0 ODTA1 J21 G19 CSA0#_0 CSA1#_0 46 47 ODTA0 ODTA1 46 47 CKEA0 CKEA1 46 46 CLKA0 CLKA0# 47 47 CLKA1 CLKA1# RASA0B RASA1B K23 K19 RASA0# RASA1# CASA0B CASA1B K20 K17 CASA0# CASA1# CSA0B_0 CSA0B_1 K24 K27 CSA0#_0 CSA1B_0 CSA1B_1 M13 K16 CSA1#_0 MVREFDA MVREFSA CKEA0 CKEA1 K21 J20 CKEA0 CKEA1 NC_MEM_CALRN0 NC_MEM_CALRN1 NC_MEM_CALRN2 WEA0B WEA1B K26 L15 WEA0# WEA1# AF28 AG28 AL31 RSVD#5 RSVD#6 H23 J19 MAA13 RSVD#9 RSVD#11 T8 W8 MAB13 GDDR3 DRR3 1.8V 1.5V Ra 40.2R 100R Rb 100R 100R CKEA0 CKEA1 CLKA0 CLKA0# CLKA1 CLKA1# QSA#[7 0] QSA[7 0] DQMA#[7 0] MDA[63 0] MAA[13 0] A_BA0 A_BA1 A_BA2 A_BA0 A_BA1 A_BA2 +MVDDQ M2:DDRII = 0.5*VDDR1 R797 40.2R1% R798 100R0402 Park:DDRII = 0.7*VDDR1 C879 C0.1u16Y0402 C5 C3 E3 E1 F1 F3 F5 G4 H5 H6 J4 K6 K5 L4 M6 M1 M3 M5 N4 P6 P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1 Y3 Y5 AA4 AB6 AB1 AB3 AD6 AD1 AD3 AD5 AF1 AF3 AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7 AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3 AP1 AP5 Y12 AA12 T13 T14 T15 RSVD#1 RSVD#2 RSVD#3 MVDDQ ODTA0 ODTA1 MAA[13 0] +MVDDQ DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63 MVREFDB MVREFSB M2:DDRII = 0.5*VDDR1 Park:DDRII = 0.7*VDDR1 AD28 R792 40.2R1% TEST_MCLK AK10 TEST_YCLK AL10 MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8 MAB_9 MAB_10 MAB_11 MAB_12 MAB_13/BA2 MAB_14/BA0 MAB_15/BA1 P8 T9 P9 N7 N8 N9 U9 U8 Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 B_BA2 B_BA0 B_BA1 DQMB_0 DQMB_1 DQMB_2 DQMB_3 DQMB_4 DQMB_5 DQMB_6 DQMB_7 H3 H1 T3 T5 AE4 AF5 AK6 AK5 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 QSB_0/RDQSB_0 QSB_1/RDQSB_1 QSB_2/RDQSB_2 QSB_3/RDQSB_3 QSB_4/RDQSB_4 QSB_5/RDQSB_5 QSB_6/RDQSB_6 QSB_7/RDQSB_7 F6 K3 P3 V5 AB5 AH1 AJ9 AM5 QSB0 QSB1 QSB2 QSB3 QSB4 QSB5 QSB6 QSB7 QSB_0B/WDQSB_0 QSB_1B/WDQSB_1 QSB_2B/WDQSB_2 QSB_3B/WDQSB_3 QSB_4B/WDQSB_4 QSB_5B/WDQSB_5 QSB_6B/WDQSB_6 QSB_7B/WDQSB_7 G7 K1 P1 W4 AC4 AH3 AJ8 AM3 QSB#0 QSB#1 QSB#2 QSB#3 QSB#4 QSB#5 QSB#6 QSB#7 R802 100R0402 C878 C0.1u16Y0402 40 R788 TESTEN CLKB0 CLKB0B L9 L8 CLKB0 CLKB0# CLKB1 CLKB1B AD8 AD7 CLKB1 CLKB1# RASB0B RASB1B T10 Y10 RASB0# RASB1# CASB0B CASB1B W10 AA10 CASB0# CASB1# CSB0B_0 CSB0B_1 P10 L10 CSB0#_0 CSB1B_0 CSB1B_1 AD10 AC10 CSB1#_0 CKEB0 CKEB1 U10 AA11 CKEB0 CKEB1 WEB0B WEB1B N10 AB11 WEB0# WEB1# 51R1%0402 51R1%0402 44 45 CASB0# CASB1# 44 45 WEB0# WEB1# 44 45 CSB0#_0 CSB1#_0 44 45 ODTB0 ODTB1 44 45 CKEB0 CKEB1 44 44 CLKB0 CLKB0# 45 45 CLKB1 CLKB1# RASB0# RASB1# CASB0# CASB1# WEB0# WEB1# CSB0#_0 CSB1#_0 ODTB0 ODTB1 CKEB0 CKEB1 CLKB0 CLKB0# CLKB1 CLKB1# QSB#[7 0] 44,45 QSB#[7 0] QSB[7 0] 44,45 QSB[7 0] 44,45 DQMB#[7 0] 44,45 MAB[13 0] 44,45 44,45 44,45 B_BA0 B_BA1 B_BA2 DQMB#[7 0] MDB[63 0] MAB[13 0] B_BA0 B_BA1 B_BA2 DRAM_RST AH11 TESTEN CLKTESTA CLKTESTB 216-0729042 R793 R794 Pin AF28: Park為FB_VDDC Pin AG28: Park為FB_VDDCI RASB0# RASB1# ODTB0 ODTB1 T7 W7 R2 C249 C250 10KR0402 M2:1K Park:10K 44 45 44,45 MDB[63 0] ODTB0 ODTB1 R200 DDR3/GDDR3 Memory Stuff Option R900 100R0402 CSA0#_0 CSA1#_0 ODTA0 ODTA1 CLKA1 CLKA1# MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63 WEA0# WEA1# 46,47 QSA#[7 0] 46,47 46,47 46,47 J14 H14 216-0729042 46 47 46,47 CLKA1 CLKA1B Park:DDRII = 0.7*VDDR1 WEA0# WEA1# 46,47 MDA[63 0] H27 G27 R865 40.2R1% 46 47 CASA0# CASA1# 46,47 DQMA#[7 0] CLKA0 CLKA0B M2:DDRII = 0.5*VDDR1 CASA0# CASA1# U95D RASA0# RASA1# 46,47 QSA[7 0] CLKA0 CLKA0# MEM_CALRP1 NC_MEM_CALRP0 NC_MEM_CALRP2 46 47 E 680R0402-RH MEM_RST C877 C0.01u16X0402 44,45,46,47 R787 X_4.7KR0402 10KR0402 C0.1u10X0402 DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63 RASA0# RASA1# C0.1u10X0402 C37 C35 A35 E34 G32 D33 F32 E32 D31 F30 C30 A30 F28 C28 A28 E28 D27 F26 C26 A26 F24 C24 A24 E24 C22 A22 F22 D21 A20 F20 D19 E18 C18 A18 F18 D17 A16 F16 D15 E14 F14 D13 F12 A12 D11 F10 A10 C10 G13 H13 J13 H11 G10 G8 K9 K10 G9 A8 C8 E8 A6 C6 E6 A5 MEMORY INTERFACE A MDA0 MDA1 MDA2 MDA3 MDA4 MDA5 MDA6 MDA7 MDA8 MDA9 MDA10 MDA11 MDA12 MDA13 MDA14 MDA15 MDA16 MDA17 MDA18 MDA19 MDA20 MDA21 MDA22 MDA23 MDA24 MDA25 MDA26 MDA27 MDA28 MDA29 MDA30 MDA31 MDA32 MDA33 MDA34 MDA35 MDA36 MDA37 MDA38 MDA39 MDA40 MDA41 MDA42 MDA43 MDA44 MDA45 MDA46 MDA47 MDA48 MDA49 MDA50 MDA51 MDA52 MDA53 MDA54 MDA55 MDA56 MDA57 MDA58 MDA59 MDA60 MDA61 MDA62 MDA63 46 47 MEMORY INTERFACE B A +MVDDQ M2:4.7K to GND Park:100nF串接 50 Ohm to GND 090722修改 MICRO-STAR INT'L CO.,LTD Title M92-M2_MEM Interface Size Document Number Custom Date: A B C D Rev 31 MS-AE111 Tuesday, March 09, 2010 Sheet E 43 of 54 A B C D U37 VREFCA_D1 VREFDQ_D1 M8 H1 VREFCA VREFDQ MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 B_BA0 B_BA1 B_BA2 M2 N8 M3 BA0 BA1 BA2 CLKB0 CLKB0# CKEB0 J7 K7 K9 CK CK CKE ODTB0 CSB0#_0 RASB0# CASB0# WEB0# K1 L2 J3 K3 L3 ODT CS RAS CAS WE QSB1 QSB0 F3 C7 DQSL DQSU DQMB#1 DQMB#0 E7 D3 DML DMU QSB#1 QSB#0 G3 B7 DQSL DQSU T2 RESET L8 ZQ 43,45,46,47 MEM_RST Should be 240 Ohm +-1% R811 243R1%0402 J1 L1 J9 L9 NC1 NC2 NC3 NC4 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 MDB15 MDB10 MDB14 MDB11 MDB12 MDB9 MDB13 MDB8 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDB1 MDB4 MDB0 MDB7 MDB3 MDB6 MDB2 MDB5 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VREFCA_D2 VREFDQ_D2 Group1 Group0 M8 H1 VREFCA VREFDQ MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 B_BA0 B_BA1 B_BA2 M2 N8 M3 BA0 BA1 BA2 CLKB0 CLKB0# CKEB0 J7 K7 K9 CK CK CKE ODTB0 CSB0#_0 RASB0# CASB0# WEB0# K1 L2 J3 K3 L3 ODT CS RAS CAS WE QSB3 QSB2 F3 C7 DQSL DQSU DQMB#3 DQMB#2 E7 D3 DML DMU QSB#3 QSB#2 G3 B7 DQSL DQSU T2 RESET L8 ZQ +MVDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C889 C1u6.3Y0402-RH C895 C1u6.3Y0402-RH C898 C1u6.3Y0402-RH +MVDDQ C902 C1u6.3Y0402-RH C904 C1u6.3Y0402-RH C880 C1u6.3Y0402-RH C881 C1u6.3Y0402-RH C882 C1u6.3Y0402-RH 43,45,46,47 MEM_RST Should be 240 Ohm +-1% B1 B9 D1 D8 E2 E8 F9 G1 G9 R812 243R1%0402 J1 L1 J9 L9 INFINEON 96-BALL SDRAM DDR3 H5TQ1G63BFR-12C-HF +MVDDQ E U36 NC1 NC2 NC3 NC4 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 MDB27 MDB29 MDB24 MDB30 MDB26 MDB31 MDB25 MDB28 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDB19 MDB20 MDB21 MDB16 MDB22 MDB17 MDB23 MDB18 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 Group3 Group2 +MVDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C886 C1u6.3Y0402-RH C887 C1u6.3Y0402-RH C888 C1u6.3Y0402-RH C893 C1u6.3Y0402-RH C894 C1u6.3Y0402-RH C890 C1u6.3Y0402-RH +MVDDQ C892 C1u6.3Y0402-RH 43,45 43,45 43,45 43,45 B1 B9 D1 D8 E2 E8 F9 G1 G9 B_BA0 B_BA1 B_BA2 B_BA0 B_BA1 B_BA2 MAB[13 0] MAB[13 0] 43 CKEB0 43 CSB0#_0 43 WEB0# 43 RASB0# 43 CASB0# CKEB0 CSB0#_0 WEB0# RASB0# CASB0# DQMB#[7 0] 43,45 DQMB#[7 0] INFINEON 96-BALL SDRAM DDR3 H5TQ1G63BFR-12C-HF +MVDDQ C891 C1u6.3Y0402-RH 43 ODTB0 ODTB0 3 R807 4.99KR1%0402 R803 4.99KR1%0402 VREFCA_D1 R808 4.99KR1%0402 43,45 QSB#[7 0] +MVDDQ C885 C0.1u16Y0402 43 43 C896 C10u10Y0805 C900 C10u10Y0805 C901 C10u10Y0805 C903 C10u10Y0805 CLKB0 CLKB0# CLKB0 CLKB0# R813 56R0402 C905 C10u10Y0805 R809 4.99KR1%0402 R804 4.99KR1%0402 VREFDQ_D1 R810 4.99KR1%0402 MDB[63 0] 43,45 MDB[63 0] R805 4.99KR1%0402 +MVDDQ +MVDDQ QSB[7 0] 43,45 QSB[7 0] VREFCA_D2 C897 C0.1u16Y0402 QSB#[7 0] C899 C0.01u16X0402 VREFDQ_D2 R806 4.99KR1%0402 C883 C0.1u16Y0402 R814 56R0402 C884 C0.1u16Y0402 4 MICRO-STAR INT'L CO.,LTD Title M92-M2_DDR3_B0 Size Document Number Custom Date: A B C D Rev 31 MS-AE111 Sheet Tuesday, March 09, 2010 E 44 of 54 A B C D U39 VREFCA_D3 VREFDQ_D3 M8 H1 VREFCA VREFDQ MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 B_BA0 B_BA1 B_BA2 M2 N8 M3 BA0 BA1 BA2 CLKB1 CLKB1# CKEB1 J7 K7 K9 CK CK CKE ODTB1 CSB1#_0 RASB1# CASB1# WEB1# K1 L2 J3 K3 L3 ODT CS RAS CAS WE QSB5 QSB4 F3 C7 DQSL DQSU DQMB#5 DQMB#4 E7 D3 DML DMU QSB#5 QSB#4 G3 B7 DQSL DQSU T2 RESET L8 ZQ 43,44,46,47 MEM_RST Should be 240 Ohm +-1% R826 243R1%0402 J1 L1 J9 L9 +MVDDQ U38 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 MDB46 MDB41 MDB44 MDB40 MDB45 MDB42 MDB47 MDB43 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDB37 MDB39 MDB32 MDB36 MDB34 MDB33 MDB35 MDB38 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 VREFCA_D4 VREFDQ_D4 Group5 Group4 C908 C1u6.3Y0402-RH C910 C1u6.3Y0402-RH C909 C1u6.3Y0402-RH +MVDDQ C926 C1u6.3Y0402-RH C927 C1u6.3Y0402-RH C923 C1u6.3Y0402-RH C924 C1u6.3Y0402-RH C925 C1u6.3Y0402-RH Should be 240 Ohm +-1% MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 MAB12 MAB13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 B_BA0 B_BA1 B_BA2 M2 N8 M3 BA0 BA1 BA2 CLKB1 CLKB1# CKEB1 J7 K7 K9 CK CK CKE ODTB1 CSB1#_0 RASB1# CASB1# WEB1# K1 L2 J3 K3 L3 ODT CS RAS CAS WE QSB7 QSB6 F3 C7 DQSL DQSU DQMB#7 DQMB#6 E7 D3 DML DMU QSB#7 QSB#6 G3 B7 DQSL DQSU T2 RESET L8 ZQ R821 243R1%0402 J1 L1 J9 L9 +MVDDQ NC1 NC2 NC3 NC4 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 MDB56 MDB61 MDB57 MDB62 MDB60 MDB58 MDB59 MDB63 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDB54 MDB48 MDB55 MDB49 MDB52 MDB51 MDB53 MDB50 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ B1 B9 D1 D8 E2 E8 F9 G1 G9 Group7 Group6 +MVDDQ C930 C1u6.3Y0402-RH C931 C1u6.3Y0402-RH C929 C1u6.3Y0402-RH C919 C1u6.3Y0402-RH C920 C1u6.3Y0402-RH C917 C1u6.3Y0402-RH +MVDDQ C916 C1u6.3Y0402-RH 43,44 43,44 43,44 43,44 B_BA0 B_BA1 B_BA2 B_BA0 B_BA1 B_BA2 MAB[13 0] MAB[13 0] 43 CKEB1 CKEB1 43 CSB1#_0 43 WEB1# 43 RASB1# 43 CASB1# CSB1#_0 WEB1# RASB1# CASB1# DQMB#[7 0] 43,44 DQMB#[7 0] 43 VREFCA_D4 ODTB1 ODTB1 QSB#[7 0] 43,44 QSB#[7 0] R818 4.99KR1%0402 C907 C0.1u16Y0402 QSB[7 0] 43,44 QSB[7 0] MDB[63 0] 43,44 MDB[63 0] +MVDDQ C911 C10u10Y0805 R823 4.99KR1%0402 C912 C10u10Y0805 C913 C10u10Y0805 C914 C10u10Y0805 +MVDDQ C915 C10u10Y0805 43 43 R825 4.99KR1%0402 R815 56R0402 VREFDQ_D4 C921 C0.1u16Y0402 R820 4.99KR1%0402 CLKB1 CLKB1# CLKB1 CLKB1# R819 4.99KR1%0402 VREFDQ_D3 C918 C1u6.3Y0402-RH INFINEON 96-BALL SDRAM DDR3 H5TQ1G63BFR-12C-HF R817 4.99KR1%0402 +MVDDQ C922 C0.1u16Y0402 VREFCA VREFDQ 43,44,46,47 MEM_RST VREFCA_D3 R824 4.99KR1%0402 M8 H1 +MVDDQ INFINEON 96-BALL SDRAM DDR3 H5TQ1G63BFR-12C-HF R822 4.99KR1%0402 NC1 NC2 NC3 NC4 E C906 C0.1u16Y0402 R816 56R0402 C928 C0.01u16X0402 4 MICRO-STAR INT'L CO.,LTD Title M92-M2_DDR3_B1 Size Document Number Custom Date: A B C D Rev 31 MS-AE111 Sheet Tuesday, March 09, 2010 E 45 of 54 A B C D U42 VREFCA_D5 VREFDQ_D5 M8 H1 VREFCA VREFDQ MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 A_BA0 A_BA1 A_BA2 M2 N8 M3 BA0 BA1 BA2 CLKA0 CLKA0# CKEA0 J7 K7 K9 CK CK CKE ODTA0 CSA0#_0 RASA0# CASA0# WEA0# K1 L2 J3 K3 L3 ODT CS RAS CAS WE QSA1 QSA0 F3 C7 DQSL DQSU DQMA#1 DQMA#0 E7 D3 DML DMU QSA#1 QSA#0 G3 B7 DQSL DQSU T2 RESET L8 ZQ 43,44,45,47 MEM_RST Should be 240 Ohm +-1% R855 243R1%0402 J1 L1 J9 L9 NC1 NC2 NC3 NC4 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 MDA15 MDA10 MDA14 MDA11 MDA12 MDA9 MDA13 MDA8 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDA1 MDA4 MDA0 MDA7 MDA3 MDA6 MDA2 MDA5 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VREFCA_D6 VREFDQ_D6 Group1 Group0 M8 H1 VREFCA VREFDQ MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 A_BA0 A_BA1 A_BA2 M2 N8 M3 BA0 BA1 BA2 CLKA0 CLKA0# CKEA0 J7 K7 K9 CK CK CKE ODTA0 CSA0#_0 RASA0# CASA0# WEA0# K1 L2 J3 K3 L3 ODT CS RAS CAS WE QSA3 QSA2 F3 C7 DQSL DQSU DQMA#3 DQMA#2 E7 D3 DML DMU QSA#3 QSA#2 G3 B7 DQSL DQSU T2 RESET L8 ZQ +MVDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C973 C1u6.3Y0402-RH C979 C1u6.3Y0402-RH C982 C1u6.3Y0402-RH +MVDDQ C986 C1u6.3Y0402-RH C988 C1u6.3Y0402-RH C964 C1u6.3Y0402-RH C965 C1u6.3Y0402-RH C966 C1u6.3Y0402-RH 43,44,45,47 MEM_RST Should be 240 Ohm +-1% B1 B9 D1 D8 E2 E8 F9 G1 G9 R856 243R1%0402 J1 L1 J9 L9 INFINEON 96-BALL SDRAM DDR3 H5TQ1G63BFR-12C-HF +MVDDQ E U41 NC1 NC2 NC3 NC4 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 MDA27 MDA29 MDA24 MDA30 MDA26 MDA31 MDA25 MDA28 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDA19 MDA20 MDA21 MDA16 MDA22 MDA17 MDA23 MDA18 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 Group3 Group2 +MVDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C970 C1u6.3Y0402-RH C971 C1u6.3Y0402-RH C972 C1u6.3Y0402-RH C978 C1u6.3Y0402-RH C977 C1u6.3Y0402-RH C974 C1u6.3Y0402-RH +MVDDQ C976 C1u6.3Y0402-RH 43,47 43,47 43,47 43,47 B1 B9 D1 D8 E2 E8 F9 G1 G9 A_BA0 A_BA1 A_BA2 A_BA0 A_BA1 A_BA2 MAA[13 0] MAA[13 0] 43 CKEA0 43 CSA0#_0 43 WEA0# 43 RASA0# 43 CASA0# CKEA0 CSA0#_0 WEA0# RASA0# CASA0# DQMA#[7 0] 43,47 DQMA#[7 0] INFINEON 96-BALL SDRAM DDR3 H5TQ1G63BFR-12C-HF +MVDDQ C975 C1u6.3Y0402-RH 43 ODTA0 ODTA0 3 R843 4.99KR1%0402 R837 4.99KR1%0402 VREFCA_D5 R852 4.99KR1%0402 43,47 QSA#[7 0] +MVDDQ C980 C10u10Y0805 C984 C10u10Y0805 C985 C10u10Y0805 C987 C10u10Y0805 C969 C0.1u16Y0402 R853 4.99KR1%0402 R857 56R0402 R840 4.99KR1%0402 VREFDQ_D5 R854 4.99KR1%0402 CLKA0 CLKA0# CLKA0 CLKA0# +MVDDQ C989 C10u10Y0805 MDA[63 0] 43,47 MDA[63 0] R841 4.99KR1%0402 43 43 +MVDDQ QSA[7 0] 43,47 QSA[7 0] VREFCA_D6 C981 C0.1u16Y0402 QSA#[7 0] C983 C0.01u16X0402 VREFDQ_D6 R842 4.99KR1%0402 C967 C0.1u16Y0402 R858 56R0402 C968 C0.1u16Y0402 4 MICRO-STAR INT'L CO.,LTD Title M92-M2_DDR3_A0 Size Document Number Custom Date: A B C D Rev 31 MS-AE111 Sheet Tuesday, March 09, 2010 E 46 of 54 A B C D VREFCA_D7 VREFDQ_D7 M8 H1 VREFCA VREFDQ MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 A_BA0 A_BA1 A_BA2 M2 N8 M3 BA0 BA1 BA2 CLKA1 CLKA1# CKEA1 J7 K7 K9 CK CK CKE ODTA1 CSA1#_0 RASA1# CASA1# WEA1# K1 L2 J3 K3 L3 ODT CS RAS CAS WE QSA5 QSA4 F3 C7 DQSL DQSU DQMA#5 DQMA#4 E7 D3 DML DMU QSA#5 QSA#4 G3 B7 DQSL DQSU T2 RESET L8 ZQ 43,44,45,46 MEM_RST Should be 240 Ohm +-1% R872 243R1%0402 J1 L1 J9 L9 NC1 NC2 NC3 NC4 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 MDA46 MDA41 MDA44 MDA40 MDA45 MDA42 MDA47 MDA43 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDA37 MDA39 MDA32 MDA36 MDA34 MDA33 MDA35 MDA38 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 VREFCA_D8 VREFDQ_D8 Group5 Group4 M8 H1 VREFCA VREFDQ MAA0 MAA1 MAA2 MAA3 MAA4 MAA5 MAA6 MAA7 MAA8 MAA9 MAA10 MAA11 MAA12 MAA13 N3 P7 P3 N2 P8 P2 R8 R2 T8 R3 L7 R7 N7 T3 T7 M7 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 A15 A_BA0 A_BA1 A_BA2 M2 N8 M3 BA0 BA1 BA2 CLKA1 CLKA1# CKEA1 J7 K7 K9 CK CK CKE ODTA1 CSA1#_0 RASA1# CASA1# WEA1# K1 L2 J3 K3 L3 ODT CS RAS CAS WE QSA7 QSA6 F3 C7 DQSL DQSU DQMA#7 DQMA#6 E7 D3 DML DMU QSA#7 QSA#6 G3 B7 DQSL DQSU T2 RESET L8 ZQ +MVDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C999 C1u6.3Y0402-RH C1005 C1u6.3Y0402-RH C1008 C1u6.3Y0402-RH +MVDDQ C1012 C1u6.3Y0402-RH C1014 C1u6.3Y0402-RH C990 C1u6.3Y0402-RH C991 C1u6.3Y0402-RH C992 C1u6.3Y0402-RH 43,44,45,46 MEM_RST Should be 240 Ohm +-1% B1 B9 D1 D8 E2 E8 F9 G1 G9 R873 243R1%0402 J1 L1 J9 L9 INFINEON 96-BALL SDRAM DDR3 H5TQ1G63BFR-12C-HF +MVDDQ E U43 U44 NC1 NC2 NC3 NC4 DQL0 DQL1 DQL2 DQL3 DQL4 DQL5 DQL6 DQL7 E3 F7 F2 F8 H3 H8 G2 H7 MDA56 MDA61 MDA57 MDA62 MDA60 MDA58 MDA59 MDA63 DQU0 DQU1 DQU2 DQU3 DQU4 DQU5 DQU6 DQU7 D7 C3 C8 C2 A7 A2 B8 A3 MDA54 MDA48 MDA55 MDA49 MDA52 MDA51 MDA53 MDA50 VDD VDD VDD VDD VDD VDD VDD VDD VDD B2 D9 G7 K2 K8 N1 N9 R1 R9 VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ A1 A8 C1 C9 D2 E9 F1 H2 H9 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS A9 B3 E1 G8 J2 J8 M1 M9 P1 P9 T1 T9 Group7 Group6 +MVDDQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ VSSQ C996 C1u6.3Y0402-RH C997 C1u6.3Y0402-RH C998 C1u6.3Y0402-RH C1004 C1u6.3Y0402-RH C1003 C1u6.3Y0402-RH C1000 C1u6.3Y0402-RH +MVDDQ 43,46 43,46 43,46 43,46 B1 B9 D1 D8 E2 E8 F9 G1 G9 R867 4.99KR1%0402 CKEA1 43 CSA1#_0 43 WEA1# 43 RASA1# 43 CASA1# +MVDDQ C1006 C10u10Y0805 C1011 C10u10Y0805 C1013 C10u10Y0805 CASA1# DQMA#[7 0] ODTA1 QSA[7 0] MDA[63 0] CLKA1 CLKA1# CLKA1 CLKA1# R874 56R0402 R860 4.99KR1%0402 VREFDQ_D7 R863 4.99KR1%0402 R875 56R0402 C1009 C0.01u16X0402 VREFDQ_D8 C993 C0.1u16Y0402 QSA#[7 0] C995 C0.1u16Y0402 R870 4.99KR1%0402 R871 4.99KR1%0402 RASA1# ODTA1 +MVDDQ C1015 C10u10Y0805 WEA1# 43,46 MDA[63 0] R861 4.99KR1%0402 C1010 C10u10Y0805 CSA1#_0 43,46 QSA[7 0] 43 43 +MVDDQ CKEA1 43,46 QSA#[7 0] VREFCA_D8 C1007 C0.1u16Y0402 MAA[13 0] MAA[13 0] 43 43 R859 4.99KR1%0402 VREFCA_D7 A_BA0 A_BA1 A_BA2 A_BA0 A_BA1 A_BA2 43,46 DQMA#[7 0] R866 4.99KR1%0402 C1002 C1u6.3Y0402-RH INFINEON 96-BALL SDRAM DDR3 H5TQ1G63BFR-12C-HF +MVDDQ C1001 C1u6.3Y0402-RH C994 C0.1u16Y0402 4 MICRO-STAR INT'L CO.,LTD Title M92-M2_DDR3_A1 Size Document Number Custom Date: A B C D Rev 31 MS-AE111 Sheet Tuesday, March 09, 2010 E 47 of 54 D D 3.1 modify 55 ISP_CLK ISP_DAT ISP_DAT2 ISP_CLK2 HPD_DVI DL_TMDS_TX2P DL_TMDS_TX2N DL_TMDS_TX1P DL_TMDS_TX1N DL_TMDS_TX0P DL_TMDS_TX0N DL_TMDS_TXCN DL_TMDS_TXCP DL_TMDS_TX5P DL_TMDS_TX5N DL_TMDS_TX4P DL_TMDS_TX4N DL_TMDS_TX3P DL_TMDS_TX3N DDCCLK_DAC1_R DDCDATA_DAC1_R EDID_WP X_0R0402 X_0R0402 X_0R0402 X_0R0402 X_0R0402 BL_EN BL_ADJ LC_COT X_100R0402 R1010 X_0R0402 (From GPU GENERICA or GENERICB KEY33 R1002 KEY22 R1006 KEY11 R1009 R1003 R1007 R999 DL_TMDS_TX2P 40 DL_TMDS_TX2N 40 DL_TMDS_TX1P 40 DL_TMDS_TX1N 40 DL_TMDS_TX0P 40 DL_TMDS_TX0N 40 DL_TMDS_TXCN 40 DL_TMDS_TXCP 40 DL_TMDS_TX5P 40 DL_TMDS_TX5N 40 DL_TMDS_TX4P 40 DL_TMDS_TX4N 40 DL_TMDS_TX3P 40 DL_TMDS_TX3N 40 2.Remove R659,R660,R661,R662 and Conection R553 X_0R0805 20100126 1.Re-define J8,J4 2.Added R1004,R1008,R1009 4A C1131 C1130 C1126 C765 C1127 DGPU_VDD_3.3V N32-1100240-A81 BHEADSMD1X10 X_J_3D_Power1 J_3D_Power1 10 LC_COT BL_EN BL_ADJ HPD_DVI 12 Reserved GENERICB Default use B) GENERICB KEY2 KEY1 KEY0 17,35,36 17,35,36 17,35,36 HPD_3 HPD_3 40 11 JISP1 X_BH1X8HS-1.25PITCH_WHITE N32-1080060-H06 53398_08 2010/01/26 Modify 40 Q63 X_N-PMBS3904_SOT23-RH B X_10KR0402 R1021 VCC5 ISP_CLK2 ISP_DAT2 ISP_CLK ISP_DAT EDID_WP R1020 X_200KR0402 R1022 X_200KR0402 DDCCLK_DAC1_R 40 DDCDATA_DAC1_R 40 KEY2 to scaler board scaler pin 53 and EC pin 71 KEY1 to scaler board scaler pin 51 and EC pin 70 KEY0 to scaler board scaler pin 52 and EC pin 68 LED11 TP17 LED22 TP18 C R990 R992 R902 R903 R1012 X_0R0402 J_ISP_CLK2 X_0R0402 J_ISP_DAT2 X_0R0402 J_ISP_CLK X_0R0402 J_ISP_DAT X_0R0402 J_EDID_WP 10 52 54 R552 X_0R0805 X_C10u25X51206-RH 56 1.Added J4 ISP Connector and remove motherboard ISP connector(CN1) to save space VOLUME_PWM 35 AMP_SD# 23,35 X_C10u25X51206-RH 57 X_0R0402to scaler board scaler PIN65 X_0R0402to scaler board scaler PIN66 X_C10u25X51206-RH 58 Revision History 20100120 +19V_OUT C451 X_C10u10Y0805 X_C10u25X51206-RH 59 C450 X_C10u10Y0805 X_C10u25X51206-RH C R1005 R1008 2010/01/26 Modify C449 X_C10u10Y0805 C 60 C447 X_C10u10Y0805 From GPU Dual-Link DVI 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 91213-051XX (3A) 53 61 E VCC5 JLVDS2 X_LVDS51P_BLACK-RH B B ISP_CLK2 C46 X_C0.1u16Y0402 ISP_CLK C47 X_C0.1u16Y0402 A A Title Size C Date: Document Number MS-AE111 Rev 31 Sheet Tuesday, March 09, 2010 48 of 54 A B C D E VIN_PWM VCC5_SB EM1-1 HS-MS1011-RH EM1-2 1 C1098 C1099 C1100 C1101 C1102 C0.1u50Y C0.1u50Y C0.1u50Y C0.1u50Y C0.1u50Y C623 X_C100p50N0402 C759 X_C100p50N0402 1 X_E23-1029060-RH EM1-3 1 HS-MS1011-RH VCC5 EM1-4 1 X_ES-MS15211-RH EM1-5 C763 X_C100p50N0402 C1024 X_C100p50N0402 X_E23-1029060-RH EM1-12 1 E23-1029060-RH VTT_DDR 2 EM1-13 1 E23-1029060-RH EM1-14 C1075 C100p50N0402 C1076 C100p50N0402 C1077 C100p50N0402 X_E23-1029060-RH EM1-6 1 HS-MS1632-RH VCC_DDR EM1-7 1 X_HS-MS1632-RH EM1-8 1 C1078 C100p50N0402 C1079 C100p50N0402 C1080 C100p50N0402 C1081 C100p50N0402 C1083 C100p50N0402 C1082 C100p50N0402 3 HS-MS1632-RH FOR EMI 4 MICRO-STAR INT'L CO.,LTD Title EMI Size Document Number Custom Date: A B C D MS-AE111 Tuesday, March 09, 2010 E Rev 31 Sheet 49 of 54 A B C D CPU_BACKPLATE Optics Orientation Holes SB HEAT SINK XX1 XX2 PCB1 PCB U2_X2 HS4 HS-0401470-RH MCH_BACKPLATE BIOS_LABEL1 E H1X3[2]M_BLACK-RH-2 FM1 FM2 FM3 FM4 FM15 FM16 U2_X3 XX4 XX3 MS-AE111-3.2,RED GPU_BACKPLATE H1X3[2]M_BLACK-RH-2 Single End 40ohm J7 Single End 50ohm J6 L1_6.5mil_40_Ohm J4 L6_6.5mil_50_ohm X_H1X2_black-RH L1_4mil_50_Ohm X_H1X2_black-RH FM18 FM17 J5 L6_4mil_50_ohm X_H1X2_black-RH X_H1X2_black-RH J11 J9 L4_8mil_50_ohm L4_5mil_50_ohm Mounting Holes X_H1X2_black-RH L6_DIFF_4/5/4_85_Ohm+ X_H1X2_black-RH X_H1X2_black-RH X_H1X2_black-RH J14 J27 J15 MH5 L6_DIFF_4/5/4_85_Ohm- X_H1X2_black-RH X_H1X2_black-RH MH4 (NPTH) MH7 (NPTH) L4_DIFF_5/6/5_85_Ohm- MH6 (NPTH) L1_DIFF_4/5/4_85_Ohm- MH3 (NPTH) (NPTH) (NPTH) J13 L4_DIFF_5/6/5_85_Ohm+ J26 L1_DIFF_4/5/4_85_Ohm+ J12 MH2 (NPTH) MH8 (NPTH) 9 MH1 Diff 85ohm X_H1X2_black-RH X_H1X2_black-RH Diff 95ohm J18 L1_DIFF_4/11/4_95_Ohm+ J19 L4_DIFF_4.5/8.5/4.5_95_Ohm+ L6_DIFF_4/11/4_95_Ohm+ X_H1X2_black-RH X_H1X2_black-RH X_H1X2_black-RH J20 J22 J23 L1_DIFF_4/11/4_95_Ohm- L4_DIFF_4.5/8.5/4.5_95_Ohm- H3 X_H_NR276D161 H7 X_H_NR164D122 L6_DIFF_4/11/4_95_Ohm- J16 3 GPU SINK X_H1X2_black-RH NB SINK H6 X_H_NR276D161 H9 X_H_NR164D122 H10 X_H_NR276D161 H11 X_H_NR276D161 H12 X_H_NR276D161 1 NB FAN Stand off E2B-AE11030-H75 H_R276D161 H4 X_H_NR276D161 NB FAN Stand Off NB FAN Stand off E2B-AE11030-H75 H_R276D161 NB FAN Stand Off GND H13 GND H14 X_H1X2_black-RH X_H1X2_black-RH MICRO-STAR INT'L CO.,LTD Title CPU FAN Stand off CPU SINK Size Document Number Custom Date: A B C Non-Footprint for BOM D Rev 31 MS-AE111 Tuesday, March 09, 2010 Sheet E 50 of 54 EC(KB3926) PIN NAME USAGE D C GA20 OUTPUT GPIO1 KBRST# OUTPUT GPIO2 UNUSED GPIO3 UNUSED GPIO4 UNUSED GPIO5 PCIRST# GPIO6 UNUSED GPIO7 PM_SLP_S3# GPIO8 UNUSED GPIO9 UNUSED GPIO0A UNUSED GPIO0B ESB_CLK GPIO0C ESB_DAT GPIO0D UNUSED GPIO0E KBSCI# GPIO0F UNUSED GPIO10 UNUSED GPIO11 PM_PWRBTN# GPIO12 UNUSED GPIO16 UNUSED GPIO17 UNUSED GPIO18 KBSMI# GPIO19 B INPUT OUTPUT INPUT Power Button detect PCI_CLKRUN# GPIO24 INTERRUPT OUTPUT GPIO40 CIR_EC INPUT GPIO41 UNUSED GPIO44 SCL0 SCL1 GPIO47 SDA1 GPIO4E UNUSED Power Button enable EXT interrupt GPIO1D SDA0 GPIO GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO[15] GPIO[16] GPIO[17] GPIO[18] GPIO[19] GPIO[20] GPIO[21] GPIO[22] GPIO[23] GPIO[24] GPIO[25] GPIO[26] GPIO[27] GPIO[28] GPIO[29] GPIO[30] GPIO[31] GPIO[32] GPIO[33] GPIO[34] GPIO[35] GPIO[36] GPIO[37] GPIO[38] GPIO[39] GPIO[48] GPIO[49] Sleep S3 OUTPUT UNUSED GPIO46 ICH7 OUTPUT PWR_SW_KEY# GPIO45 NOTES INPUT GPIO1A bidirectional GPIO4F UNUSED GPIO52 CAP_RSTD# OUTPUT GPIO53 SUSPWROK INPUT GPIO55 ALLSYSPG INPUT GPIO56 ADT7467_ALERT# GPIO58 A Input/Output GPIO0 INPUT CPU FAN ALERT SPICLK GPIOA05 BT_PWR_ON# OUTPUT Blue Tooth power on GPIOA06 WLAN_PWRON OUTPUT Lan power on GPIOA07 VR_ON OUTPUT CPU vcroe power enable GPIOA08 PWR_LED# OUTPUT Power Led GPIOA09 SUS_LED# OUTPUT Suspend Led GPIOA010 RUN_ON OUTPUT 1.1V, 3.3V, 5V Power enable GPIOA011 RSMRST# OUTPUT RSMRST# GPIOD0 THERMAL_INT# INPUT Thermal detect GPIOD1 VRM_PWGD INPUT CPU Power OK GPIOD3 VTT_PWRGD INPUT FSB Power OK GPIOD6 PWRGD OUTPUT all powers to ICH7 are valid Alt Func BM_BUSY# PCIREQ[5]# PIRQE# PIRQF# PIRQG# PIRQH# unmuxed unmuxed unmuxed unmuxed unmuxed SMBALERT# unmuxed unmuxed unmuxed unmuxed unmuxed PCIGNT[5]# unmuxed SATA1GP unmuxed SATA0GP PCIREQ[4]# LDRQ1# unmuxed unmuxed unmuxed unmuxed unmuxed OC5# OC6# OC7# CLKRUN# unmuxed unmuxed unmuxed SATA2GP SATA3GP unmuxed unmuxed GNT4# CPUPWRGD Pin I/O/NC Power AB18 I/O VCC3 C8 I/O VCC5 G8 I/OD VCC5 F7 I/OD VCC5 F8 I/OD VCC5 G7 I/OD VCC5 AC21 I/O VCC3 AC18 I/O VCC3 E21 I/O VccSus3p3 E20 I/O VccSus3p3 A20 I/O VccSus3p3 B23 I/O VccSus3p3 F19 I/O VccSus3p3 E19 I/O VccSus3p3 R4 I/O VccSus3p3 E22 I/O VccSus3p3 AC22 I/O VCC3 D8 I/O VCC3 AC20 I/O VCC3 AH18 I/O VCC3 AF21 I/O VCC3 AF19 I/O VCC3 A13 I/O VCC3 AA5 I/O VCC3 R3 I/O VccSus3p3 D20 I/O VccSus3p3 A21 I/O VccSus3p3 B21 I/O VccSus3p3 E23 I/O VccSus3p3 C3 I/O VccSus3p3 A2 I/O VccSus3p3 B3 I/O VccSus3p3 AG18 I/O VCC3 AC19 I/O VCC3 U2 I/O VCC3 AD21 I/O VCC3 AH19 I/O VCC3 AE19 I/O VCC3 AD20 I/O VCC3 AE20 I/O VCC3 A14 I/O Vcc3p3 AG24 I/O V_CPU_IO PU N N N N N N N N N N N N N N N N N N N N N N N N N Y N N N N N N N N N N N N N N N N SMI Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y N N N N N N N N N N N N N N N N N N N N N N N N N N Tol 3.3 5 5 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 3.3 CPU Default Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input N/A Output Input Input Input Input No Change Ouput 0 Input Input Input Output Input Input Input Input N/A N/A Following are the GPIOs that need to be terminated properly if not used: GPIO[39:36,23:21,19,7:0]: default as inputs and should be pulled up to Vcc3_3 if unused GPIO[31:29,15:8]: default as inputs and should be pulled up to VccSus3_3 if unused Signal Name KBSMI#_SB PREQ#5 PIRQ#E PIRQ#F PIRQ#G PIRQ#H NC strapped high KBSCI#_SB strapped high strapped high THERMAL_INT# strapped high strapped high strapped high strapped high NC PGNT#5 SPI_HOLD# strapped high NC strapped high PREQ#4 NC NC DMI_MODE USB_WAKE NC NC USB_OCP#4 USB_OCP#4 USB_OCP#4 PCI_CLKRUN# SPI_WP# NC NC strapped high strapped high strapped high strapped high PGNT#4 H_PWRGD D C B JUMPER SETTING (1-2)NORMAL JBAT1 A Micro Star Restricted Secret Title Rev GPIO & Jumper Setting Document Number 31 MS-AE111 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw (2-3)CLEAR Last Revision Date: Tuesday, March 09, 2010 Sheet 51 54 of A B C D E LGA775 - CPU (65W) 1.15V-1.50V Core - 60A 1.2V FSB VTT - 4.6A ISL6312 VCCP 60A 1.15V-1.50V 3-Phase Switch G41 DDRII x2 & TERMINATOR 3.2A VRM 11 60A 1.2V FSB_VTT - 1.0A 1.1V Core 1.1V DMI/PCI Exp 3.3V VCCA_DAC 3.3V VCC33 VTT_DDR 0.42A 0.75V - 3.2A - 250mA 0.83A VCC_DDR 1.5V 4A PWM 3.75A+10A+4A+5A+1.55A - 3.8A -400mA +1.8V_REG - 1.35A +1_1VRUN - 1.55A 3.75A DGPU_VDD_3.3V - 190mA VCC_DDR(1.5V) - 5A GPU_CORE(1.0V) + GPU_COREI(1.0V) V_1P1_CORE Regulator ICH7 1.05V Core - 1.31A 1.5V DMI - 40 mA 1.2V FSB_VTT - 14 mA 1.5V_A USB/SATA 1.5V_B PCI Exp - 0.97A - 0.74A VCCRTC - 3.3V CL - 12 mA 1.5V GbE LAN - 74 mA V_1P1_CORE 22A 1.1V - 25A 1.4A PWM 24A Mini PCI-E slot x2 VCC3_SB - 1A 1.5V - 2A uA 3.3V 10/100 LAN - 12 mA 3.3V GbE LAN - V_FSB_VTT 6.3A 2A - 3.3V HDA - 24 mA mA 3.3V VccSus3_3 - 700mA 3.3V Vcc3_3 - 580mA 5A Linear (S0,S1) (S3) 5A +12V CPU & SYS FAN - 0.7A V_1P5_ICH 1.05V Linear 2A+1A+2A LVDS V_1P05_ICH Regulator 1.31A - 3A - 30mA +5V +5V 6.3A V_1P5_ICH Regulator mA 3.3V SusHDA USB x6 V_FSB_VTT Regulator 1.2V -3.75A 1.55A 5A 10A 24.3A 1.28A 0.74A 1.32A 1.8V VCC_DDR (S0,S1) 1.8V VCC_DDR (S3) GPU (Madsion Pro) Linear VCC_DDR Regulator - 65.8mA - 15.8mA 1.1V Vcc CL - 0.83A W83310DS - 18.1A - 2.5 A 1.5V VCC_DDR (S0,S1) 1.5V VCC_SMCLK 0.9V VTT_DDR INVETER V_1P05_ICH 1.5V Linear - 1A - 1A AMPLIFIER & WOOFER 1.4A - 1.7A +12V HD Audio ALC888 3.3V AUDIO - 40mA 5V AUDIO - 200mA 5VAUD 0.8A 5V 500mA ICS9LPRS113AKLF 3.3V VDD_48/PCI/REF 0.95A DSUB&SATA&ODD&BT - 0.1A Touch - 2A - 0.5A REALTEK/RTL8111DL 3.3V_SB I/O & LED - 58mA 1.2V ANALOG - 289mA 2A VCC5_SB 1.2V 289mA 3.5A+0.5A+3A VCC5 VCC3 3A 1.75A +12V ON Semi/NCP1587DR2G VCC3_SB 1.75A+2A=3.75A 1.7A+0.7A+1A TI/TPS51120 3V 105mA Battery 1.84A 0.65A 7.2A +19V MICRO-STAR INT'L CO.,LTD 2.15A ADAPTER Title POWER MAP Size Document Number Custom Date: A B C D Rev 31 MS-AE111 Tuesday, March 09, 2010 Sheet E 52 of 54 A 01.Page 02.Page 03.Page 04.Page 05.Page 06.Page 07.Page 08.Page 09.Page 10.Page 11.Page 12.Page 13.Page 14.Page 15.Page 16.Page 17.Page 18.Page 19.Page 20.Page 21.Page 22.Page 23.Page 24.Page 25.Page 26.Page 27.Page 28.Page 29.Page 30.Page 31.Page 32.Page 33.Page 34.Page B C D E 27 Add 2N7002 to turn on the 3V/5V voltage 15 VBAT change to +RTC_VCC 31 remove Q37, R3326 39 R829 stuff 04 R40 change to V_FSB_VTT 33 USB_OC#0, USB_OC#1 change to USB_OC#5, USB_OC#6 41 HDMI0_0 & exchange 36 HDMI P & N exchange 18 R270 unstuff 34 remove U24, R532, R533 12 R54, R55 change to connect VCC3, GND 25 R395 unstuff 41 SCL/SDA change to SMBUS and ohm unstuff 25 remove U2, modify amplifier audio in signal 20 modify BT circuit 26 add FS10 32 remove power sequence circuit 24, 25 modify amplifier & woofer enable circuit 20 reserve FS11 23 add B-CAS circuit 14 LAN's PCIE and eSATA 's PCIE exchange 36 add R615, R617 41 R255 change 750R 24 MIC1 change to N54-05F00C1-H06, SPK1 change to N54-05F00B1-H06 26 Q15, Q17 Drain and Source exchange, remove R440 19 USB signal connect 15K ohm to GND 25 change to TI TAS5706 AMPLIFIER 40~44 M92 change to M96 11 reserved SMBUS ESD protect circuit at DIMM side 12 Add memory Vref circuit 27 add Eup circuit 35 add Power source 17 VCC5 change to VCC3 33 Modify 2.5V power circuit 2 3 4 MICRO-STAR INT'L CO.,LTD Title HISTORY Size Document Number Custom Date: A B C D Rev 31 MS-AE111 Tuesday, March 09, 2010 Sheet E 53 of 54 DC_19V +5VALW +3VALW D D VCC3_SB VCC5_SB 10ms 25MHz 15ms RSMRST# 40us SUS_CLK PWRBTN# 15ms S4&S5 C C VCC_DDR 1us S3 VCC3 VCC5 +12V V_1P5_ICH V_FSB_VTT VRM_PWGD PWRGD 300ms SUS_STAT# 1024us PLTRST# 1216us 64us 96us B B ALLSYSPG VTT_GD SUSPWROK RUN_ON VR_ON VRM_PWGD RSMRST# PWRBT# PM_SLP_S3# PWRGD 12 91 11 91 93 EC Power On Step 107 Input 01 SUSPWROK In 91pin 03 PWR_SW_KEY# In 34 pin 05 PM_SLP_S3# In 14 pin 07 VTT_GD In 114 pin 09 VRM_PWGD In 110 pin 11 ALLSYSPG In 93 pin ACPI TPS51125 ISL6333 A ICH7 104 Output 02 RSMRST# delay 15ms 108pin Out 04 PWRBT# 0ms 25 pin Out 06 RUN_ON 0ms 107 pin Out 08 VR_ON 0ms 104 pin Out 10 12 PWRGD delay 300ms 117 pin Out 110 108 25 A 14 117 ENE KB3926D 34 MICRO-STAR INT'L CO.,LTD Title PWR_SW_KEY# Size Document Number Custom Date: POWER Sequence MS-AE111 Tuesday, March 09, 2010 Rev 31 Sheet 54 of 54 ... N N N N N N N N N Tol 3. 3 5 5 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 3. 3 CPU Default Input Input... P 23 R 22 R 23 R24 R25 R26 T 22 T 23 T26 T27 T28 U 22 U 23 V 22 V 23 W 22 W 23 Y 22 Y 23 AA 22 AA 23 AB 22 AB 23 AC 23 AC24 AC25 AC26 AD26 AD27 AD28 VCC1_5_B VCC1_5_B#D27 VCC1_5_B#D28 VCC1_5_B#E24 VCC1_5_B#E25 VCC1_5_B#E26... R671 X _20 0R1%04 02 L41 A25 B25 B26 C24 C26 D 22 D 23 D24 E 23 F21 F 22 G21 G 22 H21 H 22 J21 J 22 K21 K 22 L21 L 22 M21 M 22 N20 N21 N 22 P20 P21 P 22 P24 R20 R21 VCC VCC C365 C10u10Y0805 EAGLELAKE_DDR2 U47F