MSI MS 6506 rev 0a

8 Last Schematic Update Date: 06/01/2001 D MS-6506 Version 0A INTEL (R) Brookdale Chipset Willamette/Northwood 478pin mPGA-B Processor Schematics Cover Sheet Block Diagram GPIO Spec Clock ICS950208 & ATA100 IDE CONNECTORS mPGA478-B INTEL CPU Sockets 5-6 FormFactor : Flex-ATX (22.4 X 19.2mm) for NEC-CI INTEL Brookdale MCH North Bridge 7-8 CPU: Willamette/Northwood mPGA-478B Processor INTEL ICH2 South Bridge - 10 LPC Super I/O Winbond W83627HF 11 AC'97 Codec & Audio Amp TL072 & GAME 12 FWH BIOS & CNR RISER 13 SDR DIMM-168PIN DIMM1,2 14 AGP 4X SLOT (1.5V) 15 BIOS FWH LPC Super I/O W83627HF PCI SLOT & 16 Front Panel & Connectors 17 Clock Generation ICS950208 USB & FAN Connectors 18 Votlage Regulator 19 System Brookdale Chipset: INTEL MCH (North Bridge) + INTEL ICH2 (South Bridge) C C On Board Chipset: Expansion Slots: AGP2.0 SLOT * PCI2.2 SLOT * CNR SLOT * B ERP BOM 601-6506-A10 D HIP6301V CPU Power ( PWM )-VRM9.0 20 IO Connectors 21 Packing 22 Jumper Setting 23 Layout Guide 24-30 Power Delivery 31 History I 32 B Function Description MS-6506 Ver:0A With AGP,CNR,STR NEC-CI Led A A M i c r o S t a r R e s tricted Secret Title Rev Cover Sheet Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Last Revision Date: Monday, June 04, 2001 Sheet 1 of 32 D D Page.17 Power Supply CONN (478PINS) Page.5,6 Page.20 VRM 9.2 Page.4 (100MHz) Willamette/Northwood Socket (mPGA478-B) CK408 Clock (100MHz) Scalable Bus Scalable Bus/2 Page.15 AGP 4X(1.5V) AGP CONN Page.7,8 4X (66MHz) AGP AGP 4X (1.5V) MCH: Memory Controller HUB (593PINS/FCBGA) Page.14 (133MHz) DIMM 1:2 ( 66MHz X ) (14.318MHz) SM Bus Heceta Hardware Monitor PCI Slots 1:2 (360PINS/EBGA) Page.4 C Page.16 PCI (33MHz) ICH2: I/O Controller HUB IDE CONN 1&2 Page.18 LPC Bus USB Port 0:3 (33MHz) (48MHz) (33MHz) C HUB Interface Page.9,10 Page.18 Page.13 AC Link CNR Riser (Shared slot) Page.12 Page.13 Page.11 AC '97 Audio AMP FWH: Firmware HUB Codec SIO W83627HF Line Out Telephone In MIC In Page.19 Audio In B B Line In PS2 Mouse & Keyboard Parallel (1) Serial (2) Floppy Disk Drive CONN CD-ROM A A Micro Star Restricted Secret Title Rev Block Diagram Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Monday, June 04, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 2 of 32 General Purpose I/O Spec D D ICH2 GPIO Pin C B A Type Function GPIO I REQ#A GPIO I PREQ#5 GPIO I INTE# GPIO I INTF# GPIO I INTG# GPIO I INTH# GPIO I AC97 Enabled/Disabled GPIO I None FWH GPIO Pin GPIO I Non Connect GPIO I AC'97 Serial Data In GPIO 10 I Non Connect GPIO 11 I Non Connect GPIO 12 I External SMI GPIO 13 I LPC PME GPIO 14~15 I Not Implemented GPIO 16 O Non Connect GPIO 17 O Non Connect GPIO 18 O Not Implemented GPIO 19 O Not Implemented GPIO 20 O Non GPIO 21 O Vpp Programming Control GPIO 22 O Not Implemented GPIO 23 OD GPIO 24 O Non GPIO 25 O Non GPIO 26 O Non GPIO 27 I/O Non GPIO 28 GPIO 29~31 I/O I/O Type Function GPI I ATA IDE Detect GPI I ATA IDE Detect GPI I Auto Recovery GPI I Reserved DEVICE ICH INT Pin IDSEL PCI Slot INTA# INTB# INTC# INTD# AD16 INTF# INTG# INTH# INTE# AD17 PCI Slot C B BIOS Locked/Unlocked A Micro Star Restricted Secret Title Rev GPIO Spec Document Number non 0A MS-6506 Not Implemented MICRO-STAR INT'L CO.,LTD Last Revision Date: Monday, June 04, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet of 32 *Trace less 0.5" CLOCK GENERATOR BLOCK Shut Source Termination Resistors Pull-Down Capacitors for good filtering from 10K~1M Differential Pair U10 FB12 X_600S/0805 Rubycon CB145 104P 39 + VCC3 CT23 CB81 105P CB77 104P 36 46 CB86 104P 43 32 CB167 104P 29 VCC3V + FB13 X_600S/0805 Rubycon VCC3 CB76 104P R127 X_0 for good filtering from 10K~1M CT24 CB98 105P CB91 104P ELS10/16-B 18 CB89 104P C CPU_VDD CPU0 CPU0# CPU_GND CPU1 CPU1# ELS10/16-B D *Put GND copper under Clock Gen connect to every GND pin * 40 mils Trace on Layer with GND copper around it * put close to every power pin 24 CB93 104P 21 CB95 104P 47 * Trace Width 7mils * Same Group spacing 15mils * Different Group spacing 30mils 34 CB78 104P * Different mode spacing 7mils on itself {10,11,13,14} SMBCLK {10,11,13,14} SMBDATA R115 R116 33 33 CPUCLK CPUCLK# 38 37 R110 R111 33 33 MCHCLK MCHCLK# 45 44 3VMREF/CPU_STP# 3VMREF#/PCI_STP# 26 25 VTT_GD# 19 CPUCLK {5} CPUCLK# {5} C_STP P_STP Trace less 0.2" 49.9ohm for 50ohm M/B impedance FS2/PCI_F0 FS3/PCI_F1 MODE/PCI_F2 PCI_VDD PCI_GND FS4/PCI0 PCI1 PCI2 PCI3 PCI4 PCI5 PCI6 PCI_VDD PCI_GND R117 R118 R119 3V66_3 31 30 28 27 3V66_0 3V66_1 3V66_2 3V66_3 3V66_GND 49.9RST 49.9RST 49.9RST 49.9RST MCHCLK {7} MCHCLK# {7} MREF_GND 3V66_VDD R108 R107 R102 R103 48_VDD FS0/48MHz FS1/24_48MHz MODE RN9 FS2 8P4R-33 33 33 33 MCH_66 ICH_66 AGPCLK C73 10P FS2 FS3 MODE 10 11 12 14 15 16 17 FS4 22 23 FS0 FS1 R153 R137 33 33 ICH_48 SIO_48 48 MUL0 MUL1 R120 33 ICH_14 SIO_PCLK FWH_PCLK ICH_PCLK RN10 8P4R-33 PCICLK0 PCICLK1 MCH_66 {7} ICH_66 {10} AGPCLK {15} MCH_66 ICH_66 AGPCLK CN10 X_10P-8P4C SIO_PCLK FWH_PCLK ICH_PCLK CN15 X_10P-8P4C PCICLK0 PCICLK1 CN16 X_8P4C-10P CLOCK STRAPPING RESISTORS SIO_PCLK {11} FWH_PCLK {13} ICH_PCLK {9} PCICLK0 {16} PCICLK1 {16} ICH_48 {10} SIO_48 {11} FS4 FS3 R151 R141 10K 10K VCC3V VCC3V FS1 R136 R147 X_10K 10K VCC3V FS0 R135 R146 10K X_10K VCC3V FS2 R140 R139 10K X_10K VCC3V MODE R142 10K MUL0 R106 R105 X_10K 10K VCC3V MUL1 R149 R150 X_10K 10K VCC3V SMBCLK SMBDATA R101 R109 4.7K 4.7K C_STP P_STP R112 R113 X_1K X_1K ICH_48 SIO_48 48_GND C93 C89 D 10P 10P C REF_VDD MUL0/REF0 MUL1/REF1 ICH_14 {10} REF_GND C81 18P 32pF 14.318MHZ/32PF C78 18P 35 R104 475RST R134 R114 10K 4.7K X1 CORE_VDD X2 CORE_GND SCLK SDATA IREF 20 42 RST# PWR_DN# VTT_GD# CRST# VCC3V ICH_14 C74 10P VCC3 used only for EMI issue VCC3V Trace less 0.2" ICS950208 ICS950208 CY28324 220 E R157 33 SMBCLK SMBDATA Q19 2N3904S B VCCP MREF_VDD 41 40 X1 C R148 10K VCC3 13 CPUCLK CPUCLK# MCHCLK MCHCLK# PRIMARY IDE BLOCK B HD_RST# PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 {10} PDD[0 7] R186 4.7K R185 33 {10} PD_DREQ {10} PD_IOW# {10} PD_IOR# {10} PD_IORDY {10} PD_DACK# {9} IRQ14 {10} PD_A1 {10} PD_A0 {10} PD_CS#1 {17} PD_LED VCC5 R187 C75 220P 8.2K IDE1 YJ220-CB-1 10 12 14 16 18 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 22 24 26 28 30 32 34 36 38 40 SECONDARY IDE BLOCK ATA100 IDE CONNECTORS PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 R125 PDD[8 15] {10} {10} SDD[0 7] HD_RST# SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0 R172 4.7K R189 33 {10} SD_DREQ {10} SD_IOW# {10} SD_IOR# {10} SD_IORDY {10} SD_DACK# {9} IRQ15 {10} SD_A1 {10} SD_A0 {10} SD_CS#1 {17} SD_LED 470 PD_DET {13} PD_A2 {10} PD_CS#3 {10} R122 8.2K VCC5 R100 8.2K C77 220P VCC3 A R327 {9} PCIRST# PCIRST# U18A 7407S (VCC5_SB) 330 U18D 7407S (VCC5_SB) VCC3 PCIRST#1 {7,11,13} PCIRST# HD_RST# R328 R300 1K R128 SDD[8 15] {10} 470 SD_DET {13} SD_A2 {10} SD_CS#3 {10} R121 8.2K A Micro Star Restricted Secret 330 VCC3 Title Rev Clock CY28323/4 & ATA100 IDE Document Number PCIRST#2 {15,16} U18B 7407S (VCC5_SB) C173 22 24 26 28 30 32 34 36 38 40 B SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 VCC5 0A MS-6506 X_10P IDE2 YJ220-CW-1 10 12 14 16 18 VCC3 PCIRST# RESET BLOCK 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 MICRO-STAR INT'L CO.,LTD Last Revision Date: Monday, June 04, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet of 32 CPU SIGNAL BLOCK CPU GTL REFERNCE VOLTAGE BLOCK VCCPS+ VCCPS- {7} HA#[3 31] VCCP {20} {20} AC3 V6 B6 Y4 AA3 W5 AB2 {9} FERR# {9} STPCLK# {9,13} C HINIT# {7} HDBSY# {7} HDRDY# {7} HTRDY# H5 H2 J6 {7} HADS# {7} HLOCK# {7} HBNR# {7} HIT# {7} HITM# {7} HBPRI# {7} HDEFER# G1 G4 G2 F3 E3 D2 E2 Trace : 10 mil width 10mil space {11,18} CPU_TMPA {11} VTIN_GND {10} THERMTRIP# ITP_TDI ITP_TDO ITP_TMS ITP_TRST# ITP_TCK CPU_TMPA THERMTRIP# PROCHOT# {9} IGNNE# {9} HSMI# {9} A20M# {9} SLP# R82 B X_0 C1 D5 F7 E6 D4 B3 C4 A2 AF26 C3 B2 B5 C6 AB26 A22 A7 AD2 AD3 AE21 AF24 AF25 AD6 AD5 {10} CPU_GD {7} CPURST# {7} HD#[0 63] AB23 CPURST# AB25 HD#63 HD#62 HD#61 HD#60 HD#59 HD#58 HD#57 HD#56 HD#55 HD#54 AA24 AA22 AA25 Y21 Y24 Y23 W25 Y26 W26 V24 AE1 VID4 AE2 VID3 AE3 VID2 AE4 VID1 AE5 VID0 DBSY# DRDY# TRDY# REQ4# REQ3# REQ2# REQ1# REQ0# ADS# LOCK# BNR# HIT# HITM# BPRI# DEFER# TDI TDO TMS TRST# TCK THERMDA THERMDC THERMTRIP# GND/SKTOCC# PROCHOT# IGNNE# SMI# A20M# SLP# HREQ#4 HREQ#3 HREQ#2 HREQ#1 HREQ#0 C35 220P HREQ#[0 4] PWRGOOD ADSTB1# ADSTB0# DSTBP3# DSTBP2# DSTBP1# DSTBP0# DSTBN3# DSTBN2# DSTBN1# DSTBN0# LINT1/NMI LINT0/INTR V22 U21 V25 U23 U24 U26 T23 T22 T25 T26 R24 R25 P24 R21 N25 N26 M26 N23 M24 P21 N22 M23 H25 K23 J24 L22 M21 H24 G26 L21 D26 F26 E25 F24 F23 G23 E24 H22 D25 J21 D23 C26 H21 G22 B25 C24 C23 B24 D22 C21 A25 A23 B22 B21 R66 49.9RST C34 220P C20 105P R64 100RST {7} Every pin put one 220pF cap near it C Trace Width 15mils, Space 15mils R83 4.7K Keep the voltage dividers within 1.5 inches of the R46 4.7K first GTLREF Pin R84 4.7K R51 4.7K CPU ITP BLOCK VCCP CPUCLK# CPUCLK {4} {4} HRS#2 HRS#1 HRS#0 HRS#[0 2] ITP_TMS ITP_TDO ITP_DBR# ITP_TCK {7} R53 R55 R49 39 75 VCCP FP_RST# 27 {17} CPU STRAPPING RESISTORS HBR#0 R56 R81 49.9RST 49.9RST B {7} * Short trace ALL COMPONENTS CLOSE TO CPU PROCHOT# CPU_GD HBR#0 CPURST# THERMTRIP# L25 K26 K25 J26 DP3# DP2# DP1# DP0# Differential Host Data Strobes H3 J3 J4 K5 J1 P1 L24 COMP1 COMP0 D BPM#1 BPM#0 V5 AC1 H6 AP1# AP0# BR0# RESET# BPM#5 BPM#4 F4 G5 F1 RS2# RS1# RS0# BSEL0 BSEL1 Length < 1.5inch 2/3*Vccp AF23 AF22 BCLK1# BCLK0# RESERVED0 RESERVED1 RESERVED2 RESERVED3 RESERVED4 RESERVED5 RESERVED6 GTLREF1 GTLREF2 AB4 AA5 Y6 AC4 AB5 AC6 AD25 A6 Y3 W4 U6 AB22 AA20 AC23 AC24 AC20 AC21 AA2 AD24 TESTHI12 TESTHI11 TESTHI10 TESTHI9 TESTHI8 TESTHI7 TESTHI6 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI1 TESTHI0 R87 100RST GTLREF2 BPM5# BPM4# BPM3# BPM2# BPM1# BPM0# C53 105P VCCP AA21 AA6 F20 F6 GTLREF3 GTLREF2 GTLREF1 GTLREF0 R5 L5 W23 P23 J23 F21 W22 R22 K22 E22 HADSTB#1 HADSTB#0 HDSTBP#3 HDSTBP#2 HDSTBP#1 HDSTBP#0 HDSTBN#3 HDSTBN#2 HDSTBN#1 HDSTBN#0 E5 D1 NMI INTR BPM#0 BPM#1 BPM#4 BPM#5 {7} {7} {7} {7} {7} {7} {7} {7} {7} {7} R48 R88 R70 R85 R74 R61 R62 R63 R57 X_62 300 49.9RST 49.9RST 62 VCCP VCCP R72 150 ITP_TRST# R52 680 R44 VCCP 49.9RST 49.9RST 49.9RST 49.9RST ITP_TDI HINIT# 300 VCCP {9} {9} A Micro Star Restricted Secret SOCKET478 Title Rev I N T E L m P G A478-B CPU1 Document Number HD#53 HD#52 HD#51 HD#50 HD#49 HD#48 HD#47 HD#46 HD#45 HD#44 HD#43 HD#42 HD#41 HD#40 HD#39 HD#38 HD#37 HD#36 HD#35 HD#34 HD#33 HD#32 HD#31 HD#30 HD#29 HD#28 HD#27 HD#26 HD#25 HD#24 HD#23 HD#22 HD#21 HD#20 HD#19 HD#18 HD#17 HD#16 HD#15 HD#14 HD#13 HD#12 HD#11 HD#10 HD#9 HD#8 HD#7 HD#6 HD#5 HD#4 HD#3 HD#2 HD#1 HD#0 C43 220P VID4# VID3# VID2# VID1# VID0# AD26 AC26 ITP_DBR# A5 A4 AE25 GTLREF1 C44 220P IERR# MCERR# FERR# STPCLK# BINIT# INIT# RSP# D63# D62# D61# D60# D59# D58# D57# D56# D55# D54# R86 49.9RST 2/3*Vccp {11,20} D53# D52# D51# D50# D49# D48# D47# D46# D45# D44# D43# D42# D41# D40# D39# D38# D37# D36# D35# D34# D33# D32# D31# D30# D29# D28# D27# D26# D25# D24# D23# D22# D21# D20# D19# D18# D17# D16# D15# D14# D13# D12# D11# D10# D9# D8# D7# D6# D5# D4# D3# D2# D1# D0# A CPU_GD DBI0# DBI1# DBI2# DBI3# ITP_CLK1 ITP_CLK0 E21 G25 P26 V21 DBR# HDBI#0 HDBI#1 HDBI#2 HDBI#3 {7} HDBI#[0 3] VID[0 4] VCC_SENSE VSS_SENSE A35# A34# A33# A32# A31# A30# A29# A28# A27# A26# A25# A24# A23# A22# A21# A20# A19# A18# A17# A16# A15# A14# A13# A12# A11# A10# A9# A8# A7# A6# A5# A4# A3# U7A HA#31 HA#30 HA#29 HA#28 HA#27 HA#26 HA#25 HA#24 HA#23 HA#22 HA#21 HA#20 HA#19 HA#18 HA#17 HA#16 HA#15 HA#14 HA#13 HA#12 HA#11 HA#10 HA#9 HA#8 HA#7 HA#6 HA#5 HA#4 HA#3 D AB1 Y1 W2 V3 U4 T5 W1 R6 V2 T4 U3 P6 U1 T2 R3 P4 P3 R2 T1 N5 N4 N2 M1 N1 M4 M3 L2 M6 L3 K1 L6 K4 K2 Length < 1.5inch 0A MS-6506 MICRO-STAR INT'L CO.,LTD L a s t R e vision Date: M o n d a y , June 04, 2001 N o , L i - D e S t , Jung-He City, T a i p ei Hsien, Taiwan h t t p : //www.msi.com.tw Sheet of 32 CPU VOLTAGE BLOCK VCC_VID {19} AE23 AF3 AF4 AD20 VCCA VCC-IOPLL VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS AD10 VSS AD12 VSS AD14 VSS AD16 AD18VSS VSS AD21 VSS AD23 VSS AD4 VSS AD8 VSS AE11 VSS AE13 VSS AE15 VSS AE17 VSS AE19 AE22VSS VSS AE24 VSS AE26 VSS AE7 VSS AE9 VSS AF1 VSS AF10 VSS AF12 VSS AF14 VSS AF16 AF18VSS VSS AF20 VSS AF6 VSS AF8 VSS B10 VSS B12 VSS B14 VSS B16 VSS B18 VSS B20 B23 VSS VSS B26 VSS B4 VSS B8 VSS C11 VSS C13 VSS C15 VSS C17 VSS C19 VSS C2 C22 VSS VSS C25 VSS C5 VSS C7 VSS C9 VSS D12 VSS D14 VSS D16 VSS D18 VSS D20 D21 VSS VSS D24 VSS D3 VSS D6 VSS D8 VSS E1 VSS E11 VSS E13 VSS E15 VSS E17 E19 VSS VSS E23 VSS E26 VSS E4 VSS E7 VSS E9 VSS F10 VSS F12 VSS F14 VSS F16 F18 VSS VSS F2 VSS F22 VSS F25 VSS F5 VSS F8 VSS G21 VSS G24 VSS G3 VSS G6 H1 VSS VSS H23 VSS H26 VSS H4 VSS J2 VSS J22 VSS J25 VSS J5 VSS K21 VSS C D10 A11 A13 A15 A17 A19 A21 A24 A26 A3 A9 AA1 AA11 AA13 AA15 AA17 AA19 AA23 AA26 AA4 AA7 AA9 AB10 AB12 AB14 AB16 AB18 AB20 AB21 AB24 AB3 AB6 AB8 AC11 AC13 AC15 AC17 AC19 AC2 AC22 AC25 AC5 AC7 AC9 AD1 VCC-VID D VCC-VIDPRG VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC U7B A10 A12 A14 A16 A18 A20 A8 AA10 AA12 AA14 AA16 AA18 AA8 AB11 AB13 AB15 AB17 AB19 AB7 AB9 AC10 AC12 AC14 AC16 AC18 AC8 AD11 AD13 AD15 AD17 AD19 AD7 AD9 AE10 AE12 AE14 AE16 AE18 AE20 AE6 AE8 AF11 AF13 AF15 AF17 AF19 AF2 AF21 AF5 AF7 AF9 B11 B13 B15 B17 B19 B7 B9 C10 C12 C14 C16 C18 C20 C8 D11 D13 D15 D17 D19 D7 D9 E10 E12 E14 E16 E18 E20 E8 F11 F13 F15 F17 F19 F9 VCCP C51 106P/1206 VSSA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS C48 106P/1206 C50 226P/1206 L2 4.7UH/1206 L1 4.7UH/1206 VCCP C47 226P/1206 AD22 D Y5 Y25 Y22 Y2 W6 W3 W24 W21 V4 V26 V23 V1 U5 U25 U22 U2 T6 T3 T24 T21 R4 R26 R23 R1 P5 P25 P22 P2 N6 N3 N24 N21 M5 M25 M22 M2 L4 L26 L23 L1 K6 K3 K24 C SOCKET478 B B CPU DECOUPLING CAPACITORS CPU DECOUPLING CAPACITORS BOTTOM VCCP VCCP CB29 106P/1206 CB49 106P/1206 CB55 106P/1206 CB32 106P/1206 CB13 106P/1206 CB30 106P/1206 CB34 106P/1206 CB36 106P/1206 CB41 106P/1206 CB26 106P/1206 A VCCP CB46 106P/1206 CB24 106P/1206 CB27 106P/1206 CB22 106P/1206 CB50 106P/1206 CB43 106P/1206 CB47 106P/1206 CB51 106P/1206 CB19 106P/1206 VCCP CB20 106P/1206 CB18 106P/1206 CB15 106P/1206 CB48 106P/1206 CB39 106P/1206 CB45 106P/1206 CB42 106P/1206 CB23 106P/1206 CB37 106P/1206 CB188 106P/1206 CB189 106P/1206 CB190 106P/1206 CB191 106P/1206 CB192 106P/1206 CB193 106P/1206 CB194 106P/1206 CB195 106P/1206 CB196 106P/1206 CB197 106P/1206 5020 5020 5020 5020 5020 5020 5020 5020 PLACE CAPS WITHIN CPU CAVITY SOLDER 5020 A 5020 Micro Star Restricted Secret Title Rev INTEL mPGA478-B CPU2 Document Number MS-6506 Last Revision Date: MICRO-STAR INT'L CO.,LTD Monday, June 04, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan Sheet http://www.msi.com.tw of 32 PLACE CAPS WITHIN CPU CAVITY 0A U11A HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 {5} HA#[3 31] D V7 W3 Y7 W5 {5} HBR#0 {5} HBNR# {5} HBPRI# {5} HLOCK# {5} HADS# {5} HREQ#[0 4] HREQ#0 HREQ#1 HREQ#2 HREQ#3 HREQ#4 C {5} HTRDY# HRS#0 HRS#1 HRS#2 {5} HRS#[0 2] R5 N6 {5} HADSTB#0 {5} HADSTB#1 AD4 AD3 AE6 AE7 AE11 AD11 AC15 AC16 HDSTBN#0 HDSTBP#0 HDSTBN#1 HDSTBP#1 HDSTBN#2 HDSTBP#2 HDSTBN#3 HDSTBP#3 HDBI#0 HDBI#1 HDBI#2 HDBI#3 {5} HDBI#[0 3] B R97 R123 24.9RST 24.9RST HL0 HL1 HL2 HL3 HL4 HL5 AC2 AC13 P25 P24 N27 P23 M26 M25 N25 N24 {9} HL_STB {9} HL_STB# VCCP A AD5 AG4 AH9 AD15 J8 K8 {4} MCHCLK {4} MCHCLK# HL[0 10] U7 W2 W7 W6 V5 V4 {5} HDBSY# {5} HDRDY# {9} HL[0 10] V3 U6 T7 R7 U5 U2 Y5 Y3 Y4 {5} HIT# {5} HITM# {5} HDEFER# {5} {5} {5} {5} {5} {5} {5} {5} T4 T5 T3 U3 R3 P7 R2 P4 R6 P5 P3 N2 N7 N3 K4 M4 M3 L3 L5 K3 J2 M5 J3 L2 H4 N5 G2 M6 L7 M8 U8 AA9 AB8 AB18 AB20 AC19 AD18 AD20 AE19 AE21 AF18 AF20 AG19 AG21 AG23 AJ19 AJ21 AJ23 HOST HA3# HA4# HA5# HA6# HA7# HA8# HA9# HA10# HA11# HA12# HA13# HA14# HA15# HA16# HA17# HA18# HA19# HA20# HA21# HA22# HA23# HA24# HA25# HA26# HA27# HA28# HA29# HA30# HA31# HD0# HD1# HD2# HD3# HD4# HD5# HD6# HD7# HD8# HD9# HD10# HD11# HD12# HD13# HD14# HD15# HD16# HD17# HD18# HD19# HD20# HD21# HD22# HD23# HD24# HD25# HD26# HD27# HD28# HD29# HD30# HD31# HD32# HD33# HD34# HD35# HD36# HD37# HD38# HD39# HD40# HD41# HD42# HD43# HD44# HD45# HD46# HD47# HD48# HD49# HD50# HD51# HD52# HD53# HD54# HD55# HD56# HD57# HD58# HD59# HD60# HD61# HD62# HD63# BR0# BNR# BPRI# HLOCK# ADS# HREQ0# HREQ1# HREQ2# HREQ3# HREQ4# HIT# HITM# DEFER# HTRDY# RS0# RS1# RS2# DBSY# DRDY# HAD_STB0# HAD_STB1# HD_STBN0# HD_STBP0# HD_STBN1# HD_STBP1# HD_STBN2# HD_STBP2# HD_STBN3# HD_STBP3# 66IN RSTIN# CPURST# DBI0# DBI1# DBI2# DBI3# BCLK BCLK# H_VREF0 H_VREF1 H_VREF2 H_VREF3 H_VREF4 H_RCOMP0 H_RCOMP1 H_SWNG0 H_SWNG1 HI0 HI1 HI2 HI3 HI4 HI5 HUB LINK HI6 HI7 HI8 HI9 HI10 HI_REF HI_STB HI_STB# VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT VTT HL_RCOMP POWER VCC1_8 VCC1_8 VCC1_8 VCC1_8 VCC1_8 RSVD0 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 NC0 NC1 AA2 AB5 AA5 AB3 AB4 AC5 AA3 AA6 AE3 AB7 AD7 AC7 AC6 AC3 AC8 AE2 AG5 AG2 AE8 AF6 AH2 AF3 AG3 AE5 AH7 AH3 AF4 AG8 AG7 AG6 AF8 AH5 AC11 AC12 AE9 AC9 AE10 AD9 AG9 AC10 AE12 AF10 AG11 AG10 AH11 AG12 AE13 AF12 AG13 AH13 AC14 AF14 AG14 AE14 AG15 AG16 AG17 AH15 AC17 AF16 AE15 AH17 AD17 AE16 HD#[0 63] VCC_DIMM MCH_66 {4} PCIRST#1 {4,11,13} CPURST# {5} M7 R8 Y8 AB11 AB17 HVREF AA7 AD13 HSWNG P26 P27 L25 L29 M22 N23 N26 VCC_AGP VTT1 VTT2 P22 J27 AE17 L28 L27 M27 N28 M24 {5} VTT_GND1 VTT_GND2 HL[0 10] HL6 HL7 HL8 HL9 HL10 HUB_MREF R171 40.2RST VCC1_8 VCC1_8 B19 C5 C8 C23 C26 D12 F26 H27 K23 K25 AD26 AD27 R22 R29 U22 U26 W22 W29 AA22 AA26 AB21 AC29 AD21 AD23 AE26 AF23 AG29 AJ25 N14 N16 P13 P15 P17 R14 R16 T15 U14 U16 T13 T17 A5 A9 A13 A17 A21 A25 C1 C29 D7 D11 D15 D19 D23 D25 F6 F10 F14 F18 F22 G1 G4 G29 H8 H10 H12 H14 H16 H18 H20 H22 H24 J5 J7 K6 K22 K24 K26 L23 U13 U17 AD12 AD14 AD16 AD19 AD22 AE1 AE4 AE18 AE20 AE29 AF5 AF7 AF9 AF11 AF13 AF15 AF17 AF19 AF21 AF25 AG1 AG18 AG20 AG22 AH19 AH21 AH23 AJ3 AJ5 AJ7 AJ9 AJ11 AJ13 AJ15 AJ17 AJ27 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCC1_5 VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM VCCSM GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND POWER GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 82845-A1 82845-A1 U11C HD#0 HD#1 HD#2 HD#3 HD#4 HD#5 HD#6 HD#7 HD#8 HD#9 HD#10 HD#11 HD#12 HD#13 HD#14 HD#15 HD#16 HD#17 HD#18 HD#19 HD#20 HD#21 HD#22 HD#23 HD#24 HD#25 HD#26 HD#27 HD#28 HD#29 HD#30 HD#31 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 A3 A7 A11 A15 A19 A23 A27 D5 D9 D13 D17 D21 E1 E4 E26 E29 F8 F12 F16 F20 F24 G26 H9 H11 H13 H15 H17 H19 H21 J1 J4 J6 J22 J26 J29 K5 K7 K27 L1 L4 L6 L8 L22 L24 L26 M23 N1 N4 N8 N13 N15 N17 N22 N29 P6 P8 P14 P16 R1 R4 R13 R15 R17 R26 T6 T8 T14 T16 T22 U1 U4 U15 U29 V6 V8 V22 W1 W4 W8 W26 Y6 Y22 AA1 AA4 AA8 AA29 AB6 AB9 AB10 AB12 AB13 AB14 AB15 AB16 AB19 AB22 AC1 AC4 AC18 AC20 AC21 AC23 AC26 AD6 AD8 AD10 MCH REFERENCE BLOCK L4 VTT1 CB92 104P C86 226P/1206 CB96 104P C92 106P/1206 4.7UH/1206 VCC_AGP C85 106P/1206 VTT_GND1 L6 VTT2 4.7UH/1206 VCC_AGP C91 226P/1206 D VTT_GND2 VCCP R126 301RST Length < 3inch.Width at 12mils HSWNG C65 104P C82 103P C80 103P R131 150RST Place Cap as Close as possible to every pin of MCH Trace width use 15 mils and 15mils space VCCP Length < 3inch.Width at 12mils R99 49.9RST C HVREF C87 103P C67 103P C66 103P C84 103P C68 103P R98 C69 104P 100RST Place Cap as Close as possible to every pin of MCH Trace width use 15 mils and 15mils space VCC1_8 R170 150RST HUB_MREF C98 103P C99 104P C100 104P R169 150RST Place 0.01uF Cap as Close as possible to MCH B Trace width use 15 mils and 15mils space MCH Trace Decoupling Capacitors VCCP VCC1_8 CB199 X_104P CB202 X_104P CB139 104P CB121 104P 5020 5020 MCH & ICH2 BOTTOM A Micro Star Restricted Secret Title Rev Brookdale MCH Document Number 0A MS-6506 Last Revision Date: MICRO-STAR INT'L CO.,LTD Monday, June 04, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan Sheet http://www.msi.com.tw of 32 U11B MD0 MD1 MD2 MD3 MD4 MD5 MD6 MD7 MD8 MD9 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 {14} MD[0 63] D C B G3 H3 Trace Length:50mils with TP {15} GAD[0 31] A {15} {15} {15} {15} GC_BE#0 GC_BE#1 GC_BE#2 GC_BE#3 F27 E27 B28 C27 D26 E25 B25 D24 F23 B23 C22 C21 D20 C19 C18 C17 B13 E13 C12 B11 E11 C10 F9 C9 E8 E7 C7 D6 B5 D4 C3 B2 G28 E28 C28 D27 B27 F25 C25 E24 C24 E23 D22 E22 B21 C20 D18 E18 E14 C13 E12 F11 C11 E10 D10 B9 E9 D8 B7 E6 C6 C4 B3 D3 GAD0 GAD1 GAD2 GAD3 GAD4 GAD5 GAD6 GAD7 GAD8 GAD9 GAD10 GAD11 GAD12 GAD13 GAD14 GAD15 GAD16 GAD17 GAD18 GAD19 GAD20 GAD21 GAD22 GAD23 GAD24 GAD25 GAD26 GAD27 GAD28 GAD29 GAD30 GAD31 R27 R28 T25 R25 T26 T27 U27 U28 V26 V27 T23 U23 T24 U24 U25 V24 Y27 Y26 AA28 AB25 AB27 AA27 AB26 Y23 AB23 AA24 AA25 AB24 AC25 AC24 AC22 AD24 GC_BE#0 GC_BE#1 GC_BE#2 GC_BE#3 V25 V23 Y25 AA23 SDQ0 SDQ1 SDQ2 SDQ3 SDQ4 SDQ5 SDQ6 SDQ7 SDQ8 SDQ9 SDQ10 SDQ11 SDQ12 SDQ13 SDQ14 SDQ15 SDQ16 SDQ17 SDQ18 SDQ19 SDQ20 SDQ21 SDQ22 SDQ23 SDQ24 SDQ25 SDQ26 SDQ27 SDQ28 SDQ29 SDQ30 SDQ31 SDQ32 SDQ33 SDQ34 SDQ35 SDQ36 SDQ37 SDQ38 SDQ39 SDQ40 SDQ41 SDQ42 SDQ43 SDQ44 SDQ45 SDQ46 SDQ47 SDQ48 SDQ49 SDQ50 SDQ51 SDQ52 SDQ53 SDQ54 SDQ55 SDQ56 SDQ57 SDQ58 SDQ59 SDQ60 SDQ61 SDQ62 SDQ63 SDRAM SMA0 SMA1 SMA2 SMA3 SMA4 SMA5 SMA6 SMA7 SMA8 SMA9 SMA10 SMA11 SMA12 SCS0# SCS1# SCS2# SCS3# SCS4# SCS5# SCS6# SCS7# SCS8# SCS9# SCS10# SCS11# Data line SDRAM ECC SCKE0 SCKE1 SCKE2 SCKE3 SCKE4 SCKE5 Bank Select SBS0 SBS1 SCK0 SCK1 SCK2 SCK3 SCK4 SCK5 SCK6 SCK7 SCK8 SCK9 SCK10 SCK11 System memory clock SRAS# SCAS# SWE# SM_RCOMP SD_REF0 SD_REF1 RD_CLKIN RD_CLKO G_AD0 G_AD1 G_AD2 G_AD3 G_AD4 G_AD5 G_AD6 G_AD7 G_AD8 G_AD9 G_AD10 G_AD11 G_AD12 G_AD13 G_AD14 G_AD15 G_AD16 G_AD17 G_AD18 G_AD19 G_AD20 G_AD21 G_AD22 G_AD23 G_AD24 G_AD25 G_AD26 G_AD27 G_AD28 G_AD29 G_AD30 G_AD31 SCB0 SCB1 SCB2 SCB3 SCB4 SCB5 SCB6 SCB7 AGP G_FRAME# G_IRDY# G_TRDY# G_DEVSEL# G_STOP# G_PAR Tri-Stated during RSTIN# assertion G_REQ# G_GNT# SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 SB_STB SB_STB# ST0 ST1 ST2 AD_STB0 AD_STB0# AD_STB1 AD_STB1# PIPE# RBF# WBF# G_C/BE0# G_C/BE1# G_C/BE2# G_C/BE3# AGPREF G_RCOMP TESTIN# G22 E21 F21 G21 E20 G20 E19 F19 G19 G18 E17 E15 G12 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 H23 J23 G7 G8 J24 G24 H7 F7 G25 H25 G6 H6 MCS#0 MCS#1 MCS#2 MCS#3 MCS#4 MCS#5 MCS#6 MCS#7 C16 E16 C15 D14 B17 D16 B15 C14 MDP0 MDP1 MDP2 MDP3 MDP4 MDP5 MDP6 MDP7 G9 F4 G10 F5 G11 E5 MCKE0 MCKE1 MCKE2 MCKE3 MA[0 12] {14} MCH REFERENCE VOLTAGE VCC_DIMM R152 49.9RST MCS#0 MCS#1 MCS#2 MCS#3 MCS#4 MCS#5 MCS#6 MCS#7 {14} {14} {14} {14} {14} {14} {14} {14} MCKE0 MCKE1 MCKE2 MCKE3 R144 49.9RST 105P MCH MEMORY CLOCK RC CIRCUITS {14} {14} {14} {14} {14} {14} {14} {14} {14} {14} {14} {14} CN13 X_33P-8P4C 8 MCLK1 MCLK0 MCLK5 MCLK4 MCLK6 MCLK2 MCLK7 MCLK3 MCLK1 MCLK0 MCLK5 MCLK4 MCLK6 MCLK2 MCLK7 MCLK3 C MBS0 {14} MBS1 {14} MCLK0 MCLK1 MCLK2 MCLK3 MCLK4 MCLK5 MCLK6 MCLK7 MCH DECOUPLING CAPACITOR MRAS# {14} MCAS# {14} MWE# {14} R162 20.5RST VCC1_8 VCC_AGP VCC_DIMM VCCP Y24 W27 W24 W28 W23 W25 GREQ# {15} GGNT# {15} SBA0 SBA1 SBA2 SBA3 SBA4 SBA5 SBA6 SBA7 C101 SB_STB {15} SB_STB# {15} ST0 ST1 ST2 ST0 ST1 ST2 AF22 AE22 AE23 X_104P 40.2RST X_4.7K CB94 104P CB85 104P CB102 104P CB90 104P CB79 104P CB87 104P CB82 104P VCC5 104P B VCC1_8 104P VCCP CB198 VCC_DIMM X_105P 5020 CB203 X_105P 5020 CB201 X_105P 5020 C97 C96 104P 105P AGPREF A VCC_AGP PIPE# {15} RBF# {15} WBF# {15} AGPREF {15} CB107 104P CB109 104P CB116 104P CB108 104P CB135 104P BACK {15} {15} {15} GAD_STB0 {15} GAD_STB#0 {15} GAD_STB1 {15} GAD_STB#1 {15} CB207 5020 R161 R163 C41 VCC_DIMM R24 R23 AC27 AC28 AA21 AD25 H26 VCC_DIMM SBA[0 7] {15} AF27 AF26 AG25 AF24 AG26 CB97 104P CB101 106P/1206 CB99 106P/1206 GFRAME# {15} GIRDY# {15} GTRDY# {15} GDEVSEL# {15} GSTOP# {15} GPAR {15} AG24 AH25 AH28 AH27 AG28 AG27 AE28 AE27 AE24 AE25 CB111 105P CB110 104P SM_REF J9 J21 CB206 X_105P 5020 CB200 X_105P 5020 CB208 X_105P 5020 CB204 X_105P 5020 CB205 X_105P 5020 Micro Star Restricted Secret Title Width 10 mils and less than 500 mils VCC1_8 Rev Brookdale MCH Document Number 0A MS-6506 Last Revision Date: MICRO-STAR INT'L CO.,LTD Monday, June 04, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan Sheet http://www.msi.com.tw of 32 82845-A1 C90 CN9 X_33P-8P4C G23 J25 G27 J28 C88 104P MDP[0 7] {14} F17 G17 F13 G13 E2 C2 G15 G14 F3 E3 G16 F15 H5 G5 D SM_REF ICH2 PCI / HUB LINK / CPU / LAN / INTERRUPT SIGNALS ICH2 SMI# SIGNAL VCC3 VCC1_8 VCC1_8SB {16} {16} {16} {16} C_BE#0 C_BE#1 C_BE#2 C_BE#3 C_BE#0 C_BE#1 C_BE#2 C_BE#3 AA3 AB6 Y8 AA9 AB7 V3 W8 V4 W1 W2 AA7 W7 Y7 Y15 {16} DEVSEL# {16} FRAME# {16} IRDY# {16} TRDY# {16} STOP# {16} PAR {16} PLOCK# {16} SERR# {16} PERR# {15,16} PME# REQA# GNTA# M3 L2 {4} ICH_PCLK W11 {4} PCIRST# AA15 F4 G4 H3 H4 J1 K4 K3 J4 J3 {13} CS {13} DIN {13} DOUT {13} SHCLK A20M# CPUSLP# FERR# IGNNE# INIT# INTR NMI SMI# STPCLK# RCIN# A20GATE V14 V15 V16 H5 J5 E14 E15 E16 E17 E18 F18 G18 H18 J18 P18 R18 R5 T5 U5 V5 V6 V7 V8 HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 HL11 HL_STB HL_STB# HLCOMP HUBREF PIRQA# PIRQB# PIRQC# PIRQD# CBE#0 CBE#1 CBE#2 CBE#3 IRQ14 IRQ15 APICCLK APICD0 APICD1 SERIRQ DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PLOCK# SERR# PERR# PME# REQ0# REQ1# REQ2# REQ3# REQ4# GPIO1/REQB#/REQ5# GNT0# GNT1# GNT2# GNT3# GNT4# GPIO17/GNTB#/GNT5# GPIO0/REQA# GPIO16/GNTA# PCICLK PCIRST# NC12 NC13 NC14 NC15 NC16 EE_CS EE_DIN EE_DOUT EE_SHCLK LAN_CLK LAN_RSTSYNC LAN_RXD0 LAN_RXD1 LAN_RXD2 LAN_TXD0 LAN_TXD1 LAN_TXD2 GND67 GND66 VCC3 R239 C124 A22 B21 B22 D3 C1 D1 E1 E2 E3 E4 J2 GND68 GND69 GND70 GND71 NC5 NC6 NC8 NC9 NC10 NC11 NC17 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 VCCSUS1_8 VCCSUS1_8 VCCSUS1_8 VCCSUS1_8 VCCSUS1_8 AA4 AB4 Y4 W5 W4 Y5 AB3 AA5 AB5 Y3 W6 W3 Y6 Y2 AA6 Y1 V2 AA8 V1 AB8 U4 W9 U3 Y9 U2 AB9 U1 W10 T4 Y10 T3 AA10 A1 GND1 A2 GND2 A10 GND3 B1 GND4 B2 GND5 B3 GND6 B9 GND7 B10 GND8 C2 GND9 C3 GND10 C4 GND11 C9 GND12 D5 GND13 D6 GND14 D7 GND15 D8 GND16 D9 GND17 E6 GND18 E7 GND19 E8 GND20 E9 GND21 J9 GND22 J10 GND23 J11 GND24 J12 GND25 J13 GND26 J14 GND27 K9 GND28 K10 GND29 K11 GND30 K12 GND31 K13 GND32 K14 GND33 K1 GND58 AA1 GND59 AA2 GND60 AA21 GND61 AA22 GND62 AB1 GND63 AB2 GND64 AB21 GND65 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 {16} AD[0 31] VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 U15A VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 D10 D2 E5 K19 L19 P5 V9 SMI# D11 A12 R22 A11 C12 C11 B11 B12 C10 B13 C13 A20M# A4 B5 A5 B6 B7 A8 B8 A9 C8 C6 C7 C5 A6 A7 A3 HL0 HL1 HL2 HL3 HL4 HL5 HL6 HL7 HL8 HL9 HL10 B4 HUB_IREF A20M# {5} SLP# {5} FERR# {5} IGNNE# {5} HINIT# {5,13} INTR {5} NMI {5} FERR# SMI# R238 HL[0 10] from ICH use 15 mils trace R2 R3 T1 AB10 P4 L3 PREQ#0 PREQ#1 PREQ#2 PREQ#3 PREQ#4 PREQ#5 M2 M1 R4 T2 R1 L4 PGNT#0 PGNT#1 PGNT#2 PGNT#3 PGNT#4 PGNT#5 G3 H2 G2 G1 H1 F3 F2 F1 A21 AB22 FERR# R65 62 SERIRQ R255 8.2K PME# R246 10K KB_RST# A20GATE# R240 R227 10K 10K REQA# GNTA# R260 R266 2.7K 2.7K APIC_D0 APIC_D1 R258 R256 10K 10K VCCP VCC3 VCC3_SB VCC3 VCC5 VCC3 HL_STB {7} HL_STB# {7} VCC1_8 INTA# INTB# INTC# INTD# APIC_D0 APIC_D1 SERIRQ {5} ICH2 REFERENCE VOLTAGE P1 P2 P3 N4 F21 C16 N20 P22 N19 N21 {7} This resistor less than 0.5" 40.2RST HSMI# ICH2 STRAPPING RESISTORS STPCLK# {5} KB_RST# {11} A20GATE# {11} KB_RST# A20GATE# 33 100P {15,16} {15,16} {16} {16} VCC1_8 IRQ14 {4} IRQ15 {4} R225 150RST HUB_IREF RN16 8P4R-22 RN15 8P4R-22 SERIRQ {11} PREQ#0 PREQ#1 PREQ#2 PREQ#3 PREQ#4 PREQ#5 {16} {16} {16} {16} {16} {16} PGNT#0 PGNT#1 PGNT#2 PGNT#3 PGNT#4 PGNT#5 {16} {16} {16} {16} {16} {16} 7 8 C123 103P C122 104P C121 104P R226 150RST Place Cap as Close as possible to ICH2 Trace width use 15 mils and 15mils space CNR_CLK CNR_RST CNR_RXD0 CNR_RXD1 CNR_RXD2 CNR_TXD2 CNR_TXD1 CNR_TXD0 {13} {13} {13} {13} {13} {13} {13} {13} 82I801BA ICH2 DECOUPLING CAPACITORS VCC1_8 CB173 X_104P CB147 104P CB148 X_104P CB163 104P CB156 X_104P CB122 X_103P VCC1_8SB CB142 103P Micro Star Restricted Secret CB125 104P CB140 104P CB151 104P CB152 104P Place one 0.1U/0.01U pair in each corner and on opposite sides close to ICH2 if it fit Title Rev Brookdale ICH2 PCI Document Number 0A MS-6506 Distribute near the 1.8V power pin of the ICH2 Distribute near the VCC1_8SB Power pin of the ICH2 MICRO-STAR INT'L CO.,LTD Last Revision Date: Monday, June 04, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet of 32 ICH2 ASIC / RTC / AC'97 / GPIO / LPC / USB / IDE SIGNALS RTC BLOCK VCC5_SB VCC3 D9 D4 M19 P20 {4} ICH_66 {4} ICH_14 {4} ICH_48 {13} AC_RST# {12,13} AC_SYNC {12,13} AC_BCLK {12,13} AC_SDOUT {12,13} AC_SDIN0 {13} AC_SDIN1 {17} SPKR {17} EXTSMI# {11} SIO_PME# {13} GP21 {13} GP23 {11,13} {11,13} {11,13} {11,13} LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 R261 V22 P19 R19 P21 Y22 W22 N22 33 W14 AB15 L1 B14 A14 AB14 AA14 SIO_PME# GP21 GPIO22 GP23 R331 X_10K {11} LDRQ# {11,13} LFRAME#/FWH4 7 USB0+ USB0USB1USB1+ USB3USB3+ USB2USB2+ RN25 NEAR CHIPSET LESS THAN INCH USBP0+ 8P4R-15 USBP04 USBP1+ USBP1USBP18 USBP1+ USBP2+ USBP32 USBP24 USBP3+ USBP3+ USBP2USBP38 USBP2+ RN26 8P4R-15 {18} OC#0 {18} OC#1 15 15 W17 Y18 AB19 AA19 W18 Y19 AB20 AA20 W19 Y20 Y21 W20 CLK66 CLK14 CLK48 AC_RST# AC_SYNC AC_BITCLK AC_SDOUT AC_SDIN0 AC_SDIN1 SPKR GPIO12 GPIO13 GPIO21 GPIO22 GPIO23 GPIO27 GPIO28 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 LAD0/FWH0 LAD1/FWH1 LAD2/FWH2 LAD3/FWH3 FS0 LDRQ0# LDRQ1# LFRAME#/FWH4 USBP0+ USBP0USBP1+ USBP1USBP2+ USBP2USBP3+ USBP3OC0# OC1# OC2# OC3# TP0 GPIO2/PIRQE# GPIO3/PIRQF# GPIO4/PIRQG# GPIO5/PIRQH# GPIO6 GPIO7 GPIO8 GPIO18 GPIO19 GPIO20 GPIO24 GPIO25 R307 R306 H19 H22 J19 J22 K21 L20 M21 M22 L22 L21 K22 K20 J21 J20 H21 H20 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 D18 B19 D19 A20 C20 C21 D22 E20 D21 C22 D20 B20 C19 A19 C18 A18 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 U20 N3 N2 N1 M4 Y11 AA11 Y14 A15 D14 C14 V21 W15 BATLOW# GP6 GP7 GP8 PDD[0 7] {4} 10M R280 10M RTCX2 X3 R289 X_5.6M BAT1 YSKTBT-1 C161 15P 32.768KHZ +-30PPM 32pF C155 15P NEC-CI AOL2 Function +12V ICH2 STRAPPING RESISTORS PD_IORDY SD_IORDY PDD[8 15] {4} RTCX1 R288 K2 M20 VCC5REF1 VCC5REF2 V19 D12 D13 T18 U18 F5 G5 V17 V18 RTCX2 L9 L10 L11 L12 L13 L14 M9 M10 M11 M12 M13 M14 N9 N10 N11 N12 N13 N14 P9 P10 P11 P12 P13 P14 {18} {18} {18} {18} {18} {18} {18} {18} Y12 W12 AB13 AB12 AA12 Y13 W13 AB11 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15 RTCX1 R334 X_20M R130 R241 4.7K 4.7K VCC3 PD_DREQ SD_DREQ R132 R229 5.6K 5.6K INTRUDER# R270 22K RSMRST# R304 10K SPKR R257 X_10K PWR_GD R268 8.2K THRM# R316 10K VRM_GD R231 10K SIO_PME# R332 4.7K RING# R317 8.2K RSMRST# R303 1K PWRBTN# R295 X_10K SM_LNK0 SM_LNK1 BATLOW# EXTSMI# RN23 8P4R-4.7K SMB_ALERT SLP_S3# GP8 RN29 8P4R-10K GP23 GPIO22 GP6 GP7 RN24 8P4R-4.7K R263 1K SDD[0 7] {4} VBAT {17} SM_CTRL R262 4.7K B Q26 2N3904S SM_LNK0 G SM_LNK0 {16} Q27 NDS7002AS SMBCLK {4,11,13,14} SM_LNK1 SM_LNK1 {16} Q28 NDS7002AS G SMBDATA {4,11,13,14} VCC3 SDD[8 15] {4} INTE# {16} INTF# {16} INTG# {16} INTH# {16} GP6 {13} 82I801BA GP21 CNR_USB1- {13} CNR_USB1+ {13} R271 4.7K VCC3 VCC3 VCC3 R315 8.2K VCC3_SB R330 8.2K THRM# {11} C T22 R336 1K THMTR2 B Q34 2N3904S VCC3_SB R347 10K {5} THERMTRIP# THMTR1 Q35 2N3904S B E U22 RTCX2 VBIAS RTCRST# VBIAS C167 473P {4} {4} {4} {4} {4} {4} D RTCX1 RTCRST# PD_DREQ {4} SD_DREQ {4} PD_DACK# {4} SD_DACK# {4} PD_IOR# {4} SD_IOR# {4} PD_IOW# {4} SD_IOW# {4} PD_IORDY {4} SD_IORDY {4} YJUMPER-MG S T21 G22 B18 F22 B17 G19 D17 G21 C17 G20 A17 JBAT1(1-2) D T20 VBIAS PD_A0 PD_A1 PD_A2 SD_A0 SD_A1 SD_A2 R311 1K C176 473P VBAT D10 1N5817S C A S RTCRST# F20 F19 E22 A16 D16 B16 {4} {4} {4} {4} C INTRUDER# SMBDATA SMBCLK GPIO11/SMBALERT# SMLINK0 SMLINK1 INTRUDER# PD_CS#1 SD_CS#1 PD_CS#3 SD_CS#3 E SMB_ALERT E21 C15 E19 D15 JBAT1 D1x3-BK {16} SM_LNK0 {16} SM_LNK1 PDDREQ SDDREQ PDDACK# SDDACK# PDIOR# SDIOR# PDIOW# SDIOW# PIORDY SIORDY {4,11,13,14} SMBDATA {4,11,13,14} SMBCLK AA16 AB16 AB17 U19 V20 T19 PDA0 PDA1 PDA2 SDA0 SDA1 SDA2 R329 390K C 1N5817S {11} SUSCLK PDCS1# SDCS1# PDCS3# SDCS3# CB153 104P RING# RSMRST# VCC5REF_SUS VRM_GD VCPU_IO1 VCPU_IO2 PWR_GD THRM# SLP_S3# SLP_S5 PWROK CPUPWRGD VRMPWRGD PWRBTN# RI# RSMRST# RSM_PWROK SUSSTAT# SUSCLK CB154 104P GND34 GND35 GND36 GND37 GND38 GND39 GND40 GND41 GND42 GND43 GND44 GND45 GND46 GND47 GND48 GND49 GND50 GND51 GND52 GND53 GND54 GND55 GND56 GND57 {11} RSMRST# AA13 W16 AB18 R20 A13 B15 W21 AA17 R21 Y16 Y17 AA18 VCC3SUS1 VCC3SUS2 VCC3SUS4 VCC3SUS5 VCC3SUS6 VCC3SUS7 U15B THRM# VCCRTC U21 A {11} THRM# {11,19} SLP_S3# {19} SLP_S5# {17} PWR_GD {5} CPU_GD {20} VRM_GD {11} PWRBTN# JBAT1 Clear CMOS 1-2 Normal * 2-3 Clear CMOS R319 1K C VCCP VCC5_SB RTC_VCC R335 4.7K C RTC_VCC R338 1.5K R259 1K E VCC3_SB VCC5 A D5 1N5817S D8 1N4148S VCC3_SB VCC3 INTERUDER JCS1 YJ102-B INTRUDER# VRM_GD R228 SMB_ALERT ICH2 DECOUPLING CAPACITOR JP3(1-2) VCC3_SB VCC5_SB RTC_VCC VCC5 VCC5_SB {13} RECOVERY VCC3 CB170 104P Micro Star Restr icted Secret YJUMPER-MG VCCP CB182 104P CB141 104P CB185 104P CB159 103P Distribute near the VCC3_SB power pin of the ICH CB160 104P CB168 104P R312 1K AC_SDOUT Title JP3 D1x3-BK Rev Brookdale ICH2 Other Document Number 0A MS-6506 Last Revision Date: MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Monday, June 04, 2001 Sheet 10 of 32 E D C B BACK PANEL USB CONNECTOR FOR USB PORT 0,1 A POWER CIRCUIT FOR USB PORT 0,1 USB3 USB0USB0+ FB9 FB10 120S/0603 120S/0603 USB1USB1+ FB8 FB7 120S/0603 120S/0603 SVCC0 SBD0SBD0+ GNDA SVCC0 SBD1SBD1+ GNDA 10 UP DOWN RN28 8P4R-15K C26 33P C27 33P C25 33P C24 33P FS2 YFUSE1.1AS-P 11 12 FB6 VCC5_STR C18 470P {10} USB1{10} USB1+ YUSB-D1 60S/0805 R68 470K + {10} USB0{10} USB0+ C17 105P SVCC0 CT3 EL1000/6.3 R59 47K {10} OC#0 R293 560K C29 104P FB11 60S NEAR USB CONNECTOR GNDA C28 104P NEAR USB CONNECTOR POWER CIRCUIT FOR USB PORT 2, FRONT PANEL USB CONNECTOR FOR USB PORT 2,3 FB21 FB22 USB2USB2+ FB20 FB19 FS4 YFUSE1.1AS-P 120/0603 120/0603 USB2 SVCC1 SBD2+ SBD2- 10 120/0603 120/0603 {10} USB2{10} USB2+ USB3+ USB3- C172 C171 33P 33P C169 C170 33P 33P SBD3+ FB23 C178 470P SBD3- R350 470K 60S/0805 C175 105P SVCC1 CT39 EL1000/6.3 R324 47K {10} OC#1 R349 560K C179 104P {13} CNR_OC#1 YJ2050022 R344 RN27 8P4R-15K VCC5_STR + {10} USB3+ {10} USB3- NEAR USB CONNECTOR NEAR USB CONNECTOR NEAR CHIPSET LESS THAN INCH R58 27K VCC3 NEC-CI FAN CONTROL +12V C5 103P CPU FAN B CPU_TMPA {5,11} +12V OUT INPUTINPUT+ VCC INPUT+ INPUTOUT Ic=600mA U3 MC33204D R4 7.5K R26 OUT INPUTINPUT+ VEE INPUT+ INPUTOUT R5 470K C_FAN1 YJ103-BO-R NECCFAN2 +12V R18 200K C +12V R16 240K SYSTEM FAN R10 27K {11} SYS_FAN R11 10K S_FAN1 YJ103-BO R9 8.2K NECFAN CPU_FAN {11} +12V R35 1.8K 27K R7 240K E R12 4.7K B Q1 2N3904S 4.7K R41 R34 10K 10 11 12 13 14 R45 160K Q2 2N2222S B E R33 1.3K +12V C Q8 2N3904S E C R29 5.6K Title R22 33K R28 90.9KST Rev USB & FAN Connectors Document Number D 0A MS-6506 MICRO-STAR INT'L CO.,LTD No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw E Micro Star Restricted Secret C B Last Revision Date: Monday, June 04, 2001 Sheet 18 A of 32 G E G 3V3DLSB DRV2 N-MOS VSEN2 S S C19 475P/0805 U5 Power VCC3_SB VCC5_STR VCC_DIMM DIMMCTR 15 D 10 + Q14 SPD09N05 IRLR3303 N-MOS S DLA CT8 470U/10V CB17 104P CB6 104P CB16 104P NOTE3 - ICH2 Power 1.8V 1.8V_LAN VCC1_8SB VCC3 VCC3+562ET VCC3_SB VCC5 S0 300mA 36mA 45mA 410mA 230mA 25mA S1 100mA 28mA 30mA 5mA 210mA 0.6mA CPU PMCH ICH2 CY28324 AD1885 FWH -SST W83627HF HIP6301 HIP6602A HIP6601A SC1547 DIMM AGP PCI USB USB HUB FAN TTL AMPLIFIER OTHER S3/S4/S5 N/A N/A 7mA N/A N/A N/A VCC_VID / VID_GOOD VCC3 Q20 IRLR3303-S-TO252 P3055LD G D R249 200 VCCP 69.0A 2.4A 0 0 VCC_AGP NOTE1 0 0 0 0 0 0 0 0 0 0 8.0A 0 0 0 VCC3_DIMM 2.0A 0 0 0 0 NOTE2 0 0 0 0 VCC3 0 NOTE3 0 VCC5 0 0 0 0 0 6.0A 2.0A 0 0 0 0 VCC5_SB 0 NOTE3 0 0 0 +12V NOTE4 0 0 -12V 0 0 0 0 0 0 0 0 0 NOTE2 ? 1.0A 0 0 0 0 0 0 0 0 C VCC3 B C Q23 2N3904S U2A YLM358S-SOIC8 VCC1_8 IPD15N03L G VCC_VID {6} FDB6692 P3055LS U12B YLM358S-SOIC8 1.2V/0.1A REGULATORS OUTPUT DECOUPLING CAPACITORS CB4 106P/1206 R167 VCC5_SB VCC5 R168 1KST CT1 470U/10V CB11 104P CB38 105P + R36 1K CB1 104P VID_GD {20} R214 332RST CT30 EL1000/6.3 CB149 100P CB127 10P R8 1KST R3 + + D 1V G 10K VCC3 Q4 NDS7002AS U2B YLM358S-SOIC8 VCC_AGP CB103 104P CB62 105P S VCC1_8 + ADJ R17 1.5KST VCC1_8 CT29 EL1000/6.3 CB157 104P CB10 105P CB12 104P CB8 104P + 1N4148S D1 VOUT VCC3_SB +12V VCC_AGP VIN B Q21 + R211 470 210RST VR3 1050CP I31-010500B-U04 Q22 2N3906S Ic=200mA Vebo=5V Vceo=40V B R21 1KST B R217 200 Q3 NDS7002AS G S S C11 X_102P + 200 E 1KST D C95 X_102P R210 C VCC3 R27 1.05KST R154 1KST E +12V D R155 VR1 SC431 U12A YLM358S-SOIC8 CT26 470U/10V VCC1_8 0.2A NOTE3 0 0 0 0 0 0 0 0 - +12V A CT33 ELS47/16-C 1.8V/3.3V SEQUENCE CIRCUIT VREF2_5 R37 220/0805 S + VCC5 D C94 104P R160 1KST C140 104P +12V VCC3 C141 100P X_1KST R156 X_0 100 VR2 SC431L R253 432 POWER CONSUMPTION VCC3_SB = VCC1_8SB = VCC5_SB = VCC3_SB + VCC1_8SB VCC5 R159 VCC1_8SB NOTE1 - MCH VCC_AGP = VCC1_5 (1.5A) + VCC_AGP (0.37A) NOTE2 - DIMM S0 STATE - 2.0A * = 6.0A -> VCC3 S1/S3 STATE - 200mA * = 600mA -> VCC3_SB VCC3_SB > 600mA*3.3V/5V=396mA >VCC5_SB AGP 4X 1.5V POWER TRANSLATOR R158 VOUT C134 104P Q12 NDS352AP FDN338P P-MOS 12 HIP6501A G VREF2_5 VIN ADJ VCC5_STR S C 5VDL G 5VCTR G Q7 SPD09N05 IRLR3303 N-MOS VCC3 VR4 YLT1087S-0.8A C135 104P S C21 104P DLA GND S3 S5 EN5VDL EN3VDL SS 11 X_0 D R39 5VDLSB 13 (40mils trace / 20 mils space) CT5 EL1000/6.3 CB73 104P CB14 105P + D 10K R40 S5 Standby 0V 0V FAULT/SEL R47 VCC5_SB S3 Standby Standby Standby VCC_DIMM 16 VCC5_SB R50 4.7K R60 4.7K S0 Main Main Main 3V3DL VCC3_SB NZT651 VCC3_SB {10,11} SLP_S3# {10} SLP_S5# N-MOS Q13 IRLR3303-S-TO252 D 12V C C Q9 X_FDN337N-S-SOT23 VCC3 5VSB D D B 14 C31 105P VCC5_SB Q6 1.8V STANDBY POWER TRANSLATOR VCC5_SB +12V POWER TRANSLATOR + VCC5 CT27 EL1000/6.3 CB146 104P CB184 105P C10 105P A Micro Star Restricted Secret Title Rev Voltage Regulator Document Number R215 150RST 0A MS-6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Monday, June 04, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 19 of 32 CHOK4 +12VCP 1.1uH/25A CB70 33P C62 33P CT22 1800U/16V CT2 1800U/16V CT7 1800U/16V C58 475P/0805 C32 105P/0805 C63 475P/0805 D CB72 104P +12VCC U8A VCC U_G1 BOOT1 CB57 105P/0805 PHASE1 R90 12 11 13 0/0805 VCCP C52 104P CHOK3 GND R31 Q18 IPD12N03L G C57 103P R1 154K R2 VCC5 R23 R20 R96 PWM2 ISEN2 FS/DIS 0/0805 COMP PWM3 ISEN3 PWM4 ISEN4 C3 562P 14 13 R89 3K 11 12 R14 3K FB VSEN 18 17 S U8B VCC PVCC U_G2 BOOT2 CB58 105P/0805 PHASE2 10 R76 0/0805 C42 103P PWM2 HIP6602A L_G2 R78 0/0805 0 1 1 0 1.500 1.525 1 1 1.175 1.550 0 1 1.575 0 1 0 0 1.625 1.650 0 1 1.700 0 0 0 1 1.750 1.775 1 1 1 0 0 0 1 1 1 1.150 1.200 1.225 1.250 1.275 1.300 1 1.325 1 0 0 1 1.350 1.375 0 1 1 1 1.600 0 1.400 0 1.425 1.850 1.475 1 1 0 1 1 OFF 0 0 1.450 0 0 0 R13 10/0805 U1 VCC PVCC U_G BOOT CB3 105P/0805 PHASE R69 0/0805 SP150/2.5 5020 Under CPU Socket Solder C2 104P C22 103P PWM L_G Beside to CPU Socket Solder Side CHOK1 GND Q10 IPD12N03L G R24 0/0805 1.1uH/25A CT40 CT42 CT43 CT44 CT45 CT46 Q11 IPD07N03L G HIP6601A SP150/2.5 SP150/2.5 5020 SP150/2.5 5020 SP150/2.5 SP150/2.5 SP150/2.5 5020 5020 5020 5020 1.725 CT16 EL4700/6.3 C15 105P/0805 +12VCP 1.675 C CT41 D VID4 VID3 VID2 VID1 VID0 VDC(V) 1.100 1.125 Q16 IPD07N03L G VCCP 1.1uH/25A CT12 CT19 EL4700/6.3 EL4700/6.3 1 B 1 Under CPU Socket 4.67m Ohm CHOK2 S R43 1 Beside to CPU Socket Side D X_0 1 SP150/2.5 SP150/2.5 Q15 IPD12N03L G C54 104P PGND 10 R15 X_0 VID4 VID3 VID2 VID1 VID0 VDC(V) CT13 SP150/2.5 SP150/2.5 SP150/2.5 SP150/2.5 S {5} VCCPS+ CT11 C64 105P/0805 C4 X_562P R42 CT17 S R6 2K CT14 3K HIP6301 R19 X_15K CT10 Q17 IPD07N03L G HIP6602A PGOOD R38 15K X_0 15 16 L_G1 + {5} VCCPS- C 470K C13 105P/0805 PWM1 +12VCC C9 X_15pF PWM1 ISEN1 + DIS 19 VCC + X_100p GND 20 + R25 C7 VCC D 10K VID4 VID3 VID2 VID1 VID0 S R30 VCC3 {10} VRM_GD D VID4 VID3 VID2 VID1 VID0 1.1uH/25A CT4 U4 {5,11} VID[0 4] D S D 14 D +12VCC R93 10/0805 VCC5 +12VCP B 1.800 1.825 ATX12V POWER CONNECTOR PWM GOOD +12VCP DIS D HIP6301V DON'T NEED PULL HIGH HIP6301 NEED PULL HIGH {19} VID_GD Q5 NDS7002AS G R54 1K GND 12V GND C59 33P A S 12V D2x2 C70 103P A VID0 VID1 VID2 VID3 VID4 JPW1 VID PULL-UP RESISTORS VCC3 Micro Star Restricted Secret RN2 8P4R-1K Title Rev VRM 9.0 Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Monday, June 04, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 20 of 32 PS2 KEYBOARD & MOUSE CONNECTOR SERIAL PORT 60S/0805 FB1 DCDA DSRA RXDA CTSA RIA D U6 20 16 15 13 11 {11} DTRA# {11} RTSA# {11} SOUTA VCC RIN1 RIN2 RIN3 RIN4 RIN5 19 18 17 14 12 V+ ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 10 DIN1 DOUT1 DIN2 DOUT2 DIN3 DOUT3 VGND T I - G D75232-SSOP20 +12VCOM C37 +12V 104P DCDA# {11} DSRA# {11} SINA {11} CTSA# {11} RIA# {11} -12VCOM DTRA RTSA TXDA C36 D4 1N4148S DSRA DCDA RXDA RTSA CN3 8P4C-220P TXDA CTSA DTRA RIA CN2 8P4C-220P {11} {11} {11} 104P A CN5B C R32 47K RN1 8P4R-4.7K DCDA RXDA TXDA DTRA -12V 26 27 28 29 30 {11} DSRA RTSA CTSA RIA 31 32 33 34 C6 104P VCC5_STR FS1 YFUSE1.1AS-P POLY SWITCH D KBMS1 FB3 60S MS_DT MSCLK FB4 60S MS_CK KBDATA FB2 60S KB_DT KBCLK FB5 60S KB_CK MSDATA 11 12 10 MS KB YMD12P-1 CN1 X_22P-8P4C C14 180P C12 180P C16 180P C8 180P LPT-D25-BK-BI PSPWR C1 104P 104P A VCC5 C39 C VCC_MS D2 1N4148S SERIAL PORT +12VCOM C VCC5 C72 104P DCDB DSRB RXDB CTSB RIB U9 20 16 15 13 11 {11} DTRB# {11} RTSB# {11} SOUTB VCC RIN1 RIN2 RIN3 RIN4 RIN5 V+ ROUT1 ROUT2 ROUT3 ROUT4 ROUT5 DIN1 DOUT1 DIN2 DOUT2 DIN3 DOUT3 VGND T I - G D75232-SSOP20 19 18 17 14 12 C71 104P 10 DTRB RTSB TXDB C76 104P DCDB# {11} DSRB# {11} SINB {11} CTSB# {11} RIB# {11} DCDB DSRB RXDB DTRB CN11 8P4C-220P RTSB CTSB TXDB RIB CN12 8P4C-220P CN5C DCDB RXDB TXDB DTRB 35 36 37 38 39 -12VCOM FLOPPY CONNECTOR FDD1 DSRB RTSB CTSB RIB 40 41 42 43 LPT-D25-BK-BI 10 12 14 16 18 20 22 24 26 28 30 32 34 11 13 15 17 19 21 23 25 27 29 31 33 DRVDEN0 INDEX# TRACK0# WP# RDATA# DSKCHG# C {11} DRVDEN1 {11} INDEX# {11} MOT_A# {11} DRV_B# {11} DRV_A# {11} MOT_B# {11} DIR# {11} STEP# {11} WT_DT# {11} WT_EN# {11} TRACK0# {11} WP# {11} RDATA# {11} HEAD# {11} DSKCHG# {11} D2x17-1:31-BK B D3 VCC5 {11} {11} LP_PE {11} LP_BUSY {11} LP_ACK# {11} LP_ERR# {11} LP_AFD# {11} LP_STB# {11} LP_SLIN# {11} LP_INIT# A 1N4148S LP_D[0 7] {11} LP_SLCT LP_D6 LP_D5 LP_D4 LP_D3 LP_PE LP_BUSY LP_ACK# LP_D7 LP_ERR# LP_D0 LP_AFD# LP_STB# LP_D2 LP_D1 LP_SLIN# LP_INIT# LP_SLCT R79 9 5 RN3 10P8R-2.2K PARALLAL PORT LP_INIT# LP_SLIN# LP_D1 LP_D2 CN7 8P4C-220P LP_STB# LP_AFD# LP_D0 LP_ERR# CN8 8P4C-220P LP_D3 LP_D4 LP_D5 LP_D6 CN6 8P4C-220P LP_D7 LP_ACK# LP_BUSY LP_PE CN4 8P4C-220P LP_SLCT C46 33P 10 10 5 RN5 10P8R-2.2K 10 10 2.2K B CN5A LP_STB# LP_D0 LP_D1 LP_D2 LP_D3 LP_D4 LP_D5 LP_D6 LP_D7 LP_ACK# LP_BUSY LP_PE LP_SLCT 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 LP_AFD# LP_ERR# LP_INIT# LP_SLIN# LPT-D25-BK-BI A Micro Star Restricted Secret Title Rev IO Connector Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD L a s t R e v ision Date: M o n d a y , J u n e 04, 2001 N o , L i - D e S t , J u n g-He City, Taipei Hsien, Taiwan h t t p : / / www.msi.com.tw Sheet 21 of 32 SIMULATION TRACE PCB OTHER COMPONENT J8 J10 VCC5 X_PIN1*2 X_PIN1*2 CPU AGP PCB1 8 D D 9 9 5 5 P01-650600A P01-650600A U11-HS SST49LF002A M31-49002A8-S20 4 BS4 BS3 BS2 BS1 U19-BIOS E31-0400070 JCOM1 BS1_X1 BS2_X1 BS3_X1 BS4_X1 BS5_X1 JCOM2 10 YCN9M-1 10 BAT1-BAT YBA3V YCN9M-1 BS5 C C B B A A Micro Star Restricted Secret Title Rev Packaging Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Monday, June 04, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 22 of 32 Jumper Setting & Connector Setting D C Jumper Description J3 JP3 1-2 2-3 REMOVED AUDIO REAR PHONE JACK (LINE_IN, LINE_OUT, MIC_IN) BIOS function Normal (Default) Configuration Mode Recovery JBAT1 1-2 2-3 CLEAR CMOS NORMAL CLEAR CMOS JAUX1 JCD1 JPHN1 JP1 1-2 2-3 AUDIO AUX HEADER CDROM HEADER (ATAPI) TELEPHONY HEADER (ATAPI) CNR RISER CODEC SELECT HEADER ENABLE ONBOARD AC'97 (Default) DISBALE ONBARD AC'97 Connector U3 IDE1 IDE2 DIM1 DIM2 AGP1 PCI1 PCI2 COM1 COM2 LPT FDD1 JCS1 KBMS1 C_FAN1 S_FAN USB1 USB2 POWER F_P1 Pin1 Pin2 Pin3 Pin4 Pin5,8,12,13 Pin6 Pin7 Pin9 P_FAN1 JPW1 JSP1 (Default) B Description INTEL mPGA478-B CPU Primary Secondary SDRAM DIMM1 SDRAM DIMM2 AGP Slot PCI Slot1 PCI Slot2 Serial Port Serial Port Parallel Port Floopy Chassis Instruction PS/2 Keyboard and PS/2 mouse CPU FAN HEADER System FAN HEADER USB REAR CONNECTOR USB INTERNAL HEADER ATX Power Front Panel Power of Hard LED Power LED Hard LED Suspend LED GND Power Button Reset Button VCC ATX FAN HEADER ATX12V Power SPDIF Connector D C B A A Micro Star Restricted Secret Title Rev JUMPER SETTING Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Friday, June 01, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 23 of 32 Pentium Processor /Northwood mPGA 478 Source Synchronous Signal Group and the Associated Strobes D Signals REQ[4:0],A[16:3]# Associated Strobe ADSTB0# A[31:17]# ADSTB1# D[15:0]#,DBI0# D[31:16]#,DBI1# DSTBP0#,DSTBN0# DSTBP1#,DSTBN1# D[47:32]#,DBI2# DSTBP2#,DSTBN2# D[63:48]#,DBI3# DSTBP3#,DSTBN3# Length D Signals Data 2.0" to 10.0" Inaccuracy +/- 100 mil Address 2.0" to 10.0" +/- 200 mil Strobe 2.0" to 10.0" +/- 25 mil Clock 2.0" to 10.0" Don't need * Delta=(CPU_pkglen.net-CPUpkglen.strobe)+(CS_pkglen.net-CS_pkglen.strobe) Trace : mil width 13mil space Miscellaneous Signals C C USB HL_STB/HL_STB# HL[10 0] Taces 5mils HL[0:10] 20mils HL_STB 15mils HL_STB# 20mils HL[0:10] * Max Length : 8" * STB and STB# Length must be equal * USB Trace width : mils * USB Trace Spacing : 25 mils Others 20mils * Differential USB Signlas Trace Spacing : 18 mils * USB Power Trace must be 40mils width HL[0:10] 15mils HL[0:10] 20mils Others * Max Length : 8" * Length must be matched within +/- 0." of the Strobe Signals B B AGP 1X Timing group 2X/4X Timing group SET#1 GAD[15 0] GC_BE#[1 0] GAD_STB0 GAD_STB0# AGPCLK PIPE# RBF# WBF# ST[2 0] GFRAME# GIRDY# GTRDY# GSTOP# GDEVSEL# GREQ# GGNT# GPAR SET#2 GAD[31 16] GC_BE#[3 2] GAD_STB1 GAD_STB1# SET#3 SBA[7 0] SB_STB SB_STB# A SIGNALS Maximum Length Width Space Dismatch Length 1X Timing group 7.5" mil mil 2X/4X Timing group SET#1 7.25" mil 20 mil +/- 0.125" GAD_STB0 GAD_STB0# 2X/4X Timing group SET#2 7.25" mil 20 mil +/- 0.125" GAD_STB1 GAD_STB1# 2X/4X Timing group SET#3 7.25" mil 20 mil +/- 0.125" SB_STB SB_STB# 2X/4X Timing group SET#1 6" mil 15 mil +/- 0.25" GAD_STB0 GAD_STB0# 2X/4X Timing group SET#2 6" mil 15 mil +/- 0.25" GAD_STB1 GAD_STB1# 2X/4X Timing group SET#3 6" mil 15 mil +/- 0.25" SB_STB SB_STB# X Relative to X A Micro Star Restricted Secret Title Rev Revision History - Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Friday, June 01, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 24 of 32 CPUCLK 0.5" MAX MCHCLK CPUCLK# L1 MCHCLK# L1 0"~ 0.2" RS 2"~ 9" L2 L4 RS L2 L4 0"~ 0.2" DEVICE L1+L2 CPU MCH X X ITP X * Line Width : 7.0 mil * Differential pair spacing : 7.0mil * Spacing to other traces : 28 mil * BCLK0/BCLK1 LENGTH MATCH +/- 10 mil L3 L3 D D RT RT GND MCH_66 ICH_66 0"~ 0.5 " 4"~ 8.5" RS L1 AGP_66 L2 ICH_PCLK L1+L2 MCH ICH X X +/- 100 mils AGP X- 4" DEVICE FWH_PCLK 0"~ 0.5 " SIO_PCLK C 4"~ 8.5" RS L1 ISAPCLK L2 PCICLK[4 0] 0"~ 0.5 " ICH_14 4"~ 8.5" RS L1 OSC ICH_48 B DEVICE 0"~ 0.5 " SIO_48 L2 3"~12" RS L1 L2 L1+L2 ICH X FWH X SIO X PCI X-2.5" DEVICE ICH L1+L2 Y ISA BRIDGE DEVICE * Line Width : 5.0 mil * Spacing to other traces : 20 mil * L1/L2 TRACE SAME AS MCH_66 TRACE LENGTH C * Line Width : 5.0 mil * Spacing to other traces : 10 mil Y L1+L2 ICH * Line Width : 5.0 mil * Spacing to other traces : 20 mil * Line Width : 5.0 mil * Spacing to other traces : 20 mil B SIO CK 408 2.5" TO 9"- A 0.5" TO 6.5" RN CNR A LAN_PCLK RST A A RXD[2 0] ICH2 Micro Star Restricted Secret TXD[2 0] Title Rev CK-408 and LAN Design Guide Document Number AS SHORT AS POSSIBLE 0A MS-6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Friday, June 01, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 25 of 32 3.ICH,FWH,On board device and PCI slot 33MHz clock routing rule Clock Routing Guidelines Signal 1.CPU and MCH differential host bus clock routing rule Signal Length A Length B Length C 0.0" - 0.2" 0.0" - 0.2" Length D Width Spacing Max = 0.5" 2" - 9" mils mils (Note2) Length E ICH_PCLK FWH_PCLK DEV_PCLK (Note1) SLOT_PCLK (Note2) CPUCLK,CPUCLK# MCHCLK,MCHCLK# (Note1) CPU clock trace CPU clock length = A + B + D =X" length 4.0" - 8.5" = Y" 0.0" - 0.5" ICH or DEV PCI clock trace length Slot PCI clock trace length D Length F 0.0" - 0.5" Spacing mils 15 mils Y" - 2.6" ICH,FWH or DEV PCI clock length = E + F = Slot PCI clock length = E + F = MCH clock trace MCH clock length = A + B + D =(X"+0.4") to (X"+0.6") length Width Y" D Y" - 2.6" ICH,FWH,On board device and PCI slot CK-408 33MHz Clock Rs CK-408 Host Clock CPU or MCH F E Rs A A B D B D Note1:33MHz trace length must be match with 66MHz of all the on board device = +/- 100 mils Rs C C Note2: Slot PCI clock trace length less than ICH PCI clock trace length = 2.6" +/- 100 mils C C Rt 4.ICH and SIO 14MHz clock routing rule Rt Signal ICH_14CLK SIO_14CLK Length E Length F Width Spacing 0.0" - 0.5" 0" - 18" mils 10 mils Note1: * The clk and clk# length matching +/-10mil of a differential clock pair * A differential clock pair not split up,must be keep 7mils spacing and reference to GND 5.ICH and SIO 48MHz clock routing rule Note2: Signal * Differential pair spacing = mils ICH_48CLK SIO_48CLK Length E Length F Width Spacing 0.0" - 0.5" 3" - 12" mils 15 mils * Spacing to other trace = 28 - 35 mils 2.MCH,ICH and AGP 66MHz clock routing rule B Signal Length E Length F Width Spacing MCH_66CLK ICH_66CLK (Note1) 0.0" - 0.5" 4.0" - 8.5" = Y" mils 20 mils AGPCLK (Note2) 0.0" - 0.5" MCH or ICH clock trace length AGP clock trace length B Y" - 4" MCH or ICH clock length = E + F = Y" AGP clock length = E + F = Y" - 4" CK-408 MCH, ICH and AGP 66MHz Clock Rs E F A A Note1: MCH with ICH clock trace match = +/- 100 mils Micro Star Restricted Secret Title Note2: AGP clock trace length less than MCH or ICH clock trace length = 4" +/- 100 mils Rev CLOCK Layout Guigeline Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Friday, June 01, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 26 of 32 1.HVREF,HSWNG and HRCOMP signal layout 2DIMM Layout Guideline Signal Signal Max Length Width HVREF 3" 12 mil 10 mil 3" 12 mil 10 mil 10 mil mil SMA[12:0] SBS[1:0] SRAS# SCAS# SWE# D 0.5" Length E Length F Width Trace Spacing Group Spacing Clearance HSWNG HRCOMP 3.SMA[12:0],SBS[1:0],SRAS#,SCAS#,SWE# routing rule MCH Routing Guidelines 2.0" - 3.0" 0.4" - 0.6" mil 10 mil 12 mil D 2DIMM Breakout CHIP routing rule Width/spacing SDRAM Routing Guidelines 1.SDQ[63:0],SCB[7:0] routing rule Max Length mil / mil 0.5" mil / mil 1.5" MCH DIMM1 2DIMM Layout Guideline Signal SDQ[63:0] SCB[7:0] Length A 2.0" - Length B 4.0" 0.4" - Width 0.6" E Trace Spacing mil 12 mil C 12 mil 4.SCK[0:7] routing rule Max Length mil / mil 0.5" mil / mil 1.5" F Group Spacing Breakout CHIP routing rule Width/spacing DIMM2 2DIMM Layout Guideline Signal SCK[7:0] MCH DIMM1 DIMM2 Length G Length H See Table-3 0.0" - Length I 1.0" 0.0" - Length J 0.25" 4.0" - 5.0" Length K Width 0.0" - 1.5" mil Trace Spacing Group Spacing 15 mil C 15 mil Table - 2DIMM Total Length Limits SCK Signal Package Trace Length(") A MCH package length G + Length H + Length J = Total length B G + H + J = 5.3"+/- 50mils 2.SCS#[7:0],SCKE[3:0] routing rule 2DIMM Layout Guideline Signal Length C Width Trace Spacing Group Spacing SCS#[7:0] 3.0" - 4.0" mil 12 mil 12 mil SCKE[5:0] 3.0" - 4.0" 10 mil 12 mil 12 mil Breakout CHIP routing rule B Width/spacing Max Length Breakout CHIP routing rule Width/spacing Max Length mil / mil MCH DIMM1 DIMM2 mil / mil 0.5" mil / 10 mil 1.0" 0.5" DIMM C G H J SCK0 0.404 SCK1 0.353 SCK2 0.865 SCK3 0.893 SCK4 0.371 SCK5 0.349 SCK6 0.814 SCK7 0.821 SCK8 0.483 SCK9 0.432 SCK10 0.589 SCK11 0.689 B K C MCH I A A Micro Star Restricted Secret Title Rev S D R A M B u s L a y o ut Guigeline Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD L a s t R e vision Date: F r i d a y , June 01, 2001 N o , L i - D e S t , Jung-He City, T a i p ei Hsien, Taiwan h t t p : //www.msi.com.tw Sheet 27 of 32 3 CPU connect to MCH data layout guideline Norminal 4-layer Board Stackup Signal PCB length D[15:0]# DBI0# DSTBP0# DSTBN0# (Note1) 2" - D[31:16]# DBI1# DSTBP1# DSTBN1# (Note1) 2" - D[47:32]# DBI2# DSTBP2# DSTBN2# (Note1) 2" - D[63:48]# DBI3# DSTBP3# DSTBN3# (Note1) 2" - Total length Width Spacing Length match mils 13 mils +/- 100 mils 1.Board spec Description Target Value notes Micro-stripline Er 4.2 - 4.5 D Trace Thickness 1.3 - 1.42 mils Board Thickness 62 mils Material FR4 Fab Construction layer 2.Board each layer thickness Description Target Value Perpreg See Table -1 +/- 25 mils (Note2) (Note3) (Note4) 13 mils +/- 100 mils Note1 Note1: Thickness after plating (Layer 1) Top layer 10" Tolerance(+/- mils) 1.4 mil See notes 4.0 mil 0.3 1.4 mil 0.2 48 mil 1.4 mil 0.2 4.0 mil 0.3 1.4 mil See notes mils 10" See Table -1 +/- 25 mils D (Note2) mils 10" (Note3) (Note4) 13 mils +/- 100 mils See Table -1 +/- 25 mils (Note2) 10" mils (Note3) (Note4) 13 mils +/- 100 mils See Table -1 +/- 25 mils (Note2) (Note3) (Note4) Note1:This group all the signals keep same length (Layer 2) Power layer Note2:This trace length is pin to pin length Core Note3:Trace edge to edge spacing greater than 3:1 versus trace to reference plane height ratio (layer 3) Ground layer Perpreg Note4: * Each group DSTBPn/p# signals pad to pad length match = +/- 25 mils (layer 4) Bottom layer * This group other signal trace lengtn match = DSTBn/p# +/- 100 mils C Note1: Final plating thickness from 1.3 - 1.42 mils C Table - 3.Via Stack Description Target Value Via Pad 26 mil Via Anti-Pad 40 mil Via Finiched hole 14 mil Signal Pad(BGA) 20 mil CPU package lengt h + PCB trace length + MCH package length = Total length L1 + L2 + L3 = Total L4 7.Keep the voltage divider with in 1.5 inches of GTLREF pin.and not allow the GTLREF routing to splits or discontinuities power plane 4.CPU GTL+ bus impedance = 50 Ohm(7mil trace width) 8.CPU Asynchronous GTL+ bus connect to ICH2 trace length 5.CPU asynchronous GTL+,AGP,Memory and Hub-link bus impedance = 60 Ohm(5mil trace width) Signal Name Trace Length Pull-up Resistor FERR# MIL 1"-12" 62 Ohm +/- 5% PROCHHOT# MIL 1"-17" 62 Ohm +/- 5% THERMTRIP# MIL 1"-17" 62 Ohm +/- 5% A20M# MIL 1"-12" None ADSTB0# IGNNE# MIL 1"-12" None CPU Routing Guidelines 1.CPU data or address synchronous signal groups and the associate strobe B Signals Associated Strobe REQ[4:0]#,A[16:3]# Trace Spacing A[31:17]# ADSTB1# LINT[1:0] MIL 1"-12" None D[15:0]#,DBI0# DSTBP0#,DSTBN0# SLP# MIL 1"-12" None D[31:16]#,DBI1# DSTBP1#,DSTBN1# SMI# MIL 1"-12" None D[47:32]#,DBI2# DSTBP2#,DSTBN2# STPCLK# MIL 1"-12" None D[63:48]#,DBI3# DSTBP3#,DSTBN3# INIT# MIL 1"-17" PWRGOOD MIL 1"-12" B None 300 Ohm +/- 5% * A l l t h e s ystem bus signals must be referenced to GND 2.CPU connect to MCH address layout guideline A Signal PCB length REQ[4:0]# A[16:3]# ADSTB0# (Note1) A[31:17]# ADSTB1# (Note1) 2" - Total length 10" Width Spacing Length match mils 13 mils +/- 200 mils 9.CPU BCLK,BCLK# should be routed as a differential pair with mil trace and mil spacing between them,2.5" to 10" pin to pin common clock lengths, and 25 mil spacing away form all the signal or clock See Table -1 (Note2) 2" - 10" mils (Note3) (Note4) 13 mils +/- 200 mils (Note3) (Note4) 10.DBSY#,DRDY#,TRDY#,ADS#,LOCK#,BNR#,HIT#,HITM#,BPRI#,DEFER#,BR0#,RESET# and RS[2:0]# CPU signal trace length around 2.5" to 10" See Table -1 (Note2) A Micro Star Restricted Secret Note1:This group all the signals keep same length Note2:This trace length is pin to pin length Title Note3:Trace edge to edge spacing greater than 3:1 versus trace to reference plane height ratio CPU Bus Layout Guigeline Document Number 0A MS-6506 Note4:This group other signal trace lengtn match = ADSTB# +/- 200 mils Rev MICRO-STAR INT'L CO.,LTD Last Revision Date: Friday, June 01, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 28 of 32 Norminal 4-layer Board Stackup Target Value notes Micro-stripline Er 4.2 - 4.5 D Trace Thickness 1.3 - 1.42 mils Board Thickness 62 mils Material FR4 Fab Construction layer 5.2" - 10" from pin to pin and each address signal group should be routed to same length within +/-200 mils of the associated strobes.Additional CPU,MCH internal trcae length(see Table-1)must be included.The calculation trace length follow (Table-2) Note1 6.Internal adderss strobe trace length(See Table-1) of CPU,MCH must be inculded.The calculation trace length follow (Table-2) Note1: Thickness after plating CPU package lengt h + PCB trace length + MCH package length = Total length Target Value (Layer 1) Top layer Perpreg (Layer 2) Power layer Core (layer 3) Ground layer Perpreg Tolerance(+/- mils) 1.4 mil See notes 4.0 mil 0.3 1.4 mil 0.2 48 mil 1.4 mil 0.2 4.0 mil 0.3 1.4 mil See notes L1 C L2 + L3 = Total L4 8.CPU Asynchronous GTL+ bus connect to ICH2 trace length Note1: Final plating thickness from 1.3 - 1.42 mils 3.Via Stack Description + 7.Keep the voltage divider with in 1.5 inches of GTLREF pin.and not allow the GTLREF routing to splits or discontinuities power plane Signal Name (layer 4) Bottom layer D Table - 2.Board each layer thickness Description 4.A pair data strobe should be routed to the same length within +/- 25mils, if one strobe switch layers, and another switch layer in the same manner.Additional CPU,MCH internal trace length(See Table-1)must be inculded.The calculation trace length follow (Table-2) 1.Board spec Description Trace Length Pull-up Resistor FERR# Trace Spacing MIL 1"-12" 62 Ohm +/- 5% PROCHHOT# MIL 1"-17" 62 Ohm +/- 5% THERMTRIP# MIL 1"-17" 62 Ohm +/- 5% None A20M# MIL 1"-12" IGNNE# MIL 1"-12" None LINT[1:0] MIL 1"-12" None C Target Value Via Pad 26 mil Via Anti-Pad 40 mil Via Finiched hole 14 mil Signal Pad(BGA) 20 mil SLP# MIL 1"-12" None SMI# MIL 1"-12" None STPCLK# MIL 1"-12" None INIT# MIL 1"-17" None PWRGOOD MIL 1"-12" 4.CPU GTL+ bus impedance = 50 Ohm(7mil trace width) 300 Ohm +/- 5% 5.CPU asynchronous GTL+,AGP,Memory and Hub-link bus impedance = 60 Ohm(5mil trace width) 9.CPU BCLK,BCLK# should be routed as a differential pair with mil trace and mil spacing between them,2.5" to 10" pin to pin common clock lengths, and 25 mil spacing away form all the signal or clock B CPU Routing Guidelines B 10.DBSY#,DRDY#,TRDY#,ADS#,LOCK#,BNR#,HIT#,HITM#,BPRI#,DEFER#,BR0#,RESET# and RS[2:0]# CPU signal trace length around 2.5" to 10" 1.CPU data synchronous signal groups and the associate strobe Signals Associated Strobe REQ[4:0]#,A[16:3]# ADSTB0# A[31:17]# ADSTB1# D[15:0]#,DBI0# DSTBP0#,DSTBN0# D[31:16]#,DBI1# DSTBP1#,DSTBN1# D[47:32]#,DBI2# DSTBP2#,DSTBN2# D[63:48]#,DBI3# DSTBP3#,DSTBN3# * A l l t h e s ystem bus signals must be referenced to GND 2.Trace edge to edge spacing greater than 3:1(about 12 mils) versus trace to GND plane height ratio A 3.2" - 10" from pin to pin and each data signal group should be routed to same length within +/-100 mils of the associated strobes.Additional CPU,MCH internal trcae length(see Table-1)must be included.The calculation trace length follow (Table-2) A Micro Star Restricted Secret Title Rev CPU Bus Layout Guigeline Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Friday, June 01, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 29 of 32 Signal ADSTB#0 D C CPU ball CPU length(") MCH ball Address Group MCH length(") Signal CPU ball CPU length(") MCH ball Data Group MCH length(") Signal CPU ball CPU length(") MCH ball Data Group MCH length(") L5 0.210 R5 0.530 DSTBN#0 E22 0.338 AD4 0.759 DSTBN#2 K22 0.252 AE11 0.595 A#3 K2 0.368 T4 0.518 DSTBP#0 F21 0.326 AD3 0.801 DSTBP#2 J23 0.266 AD11 0.532 A#4 K4 0.265 T5 0.434 D#0 B21 0.414 AA2 0.649 D#32 M23 0.300 AC11 0.514 A#5 A#6 L6 K1 0.155 0.415 T3 U3 0.728 0.577 D#1 D#2 B22 A23 0.475 0.538 AB5 AA5 0.564 0.531 D#33 D#34 N22 P21 0.226 0.178 AC12 AE9 0.565 0.652 A#7 L3 0.304 R3 0.551 D#3 A25 0.608 AB3 0.678 D#35 M24 0.371 AC9 0.566 A#8 M6 0.144 P7 0.359 D#4 C21 0.386 AB4 0.628 D#36 N23 0.271 AE10 0.605 A#9 L2 0.372 R2 0.643 D#5 D22 0.386 AC5 0.635 D#37 M26 0.454 AD9 0.635 A#10 A#11 M3 M4 0.327 0.246 P4 R6 0.533 0.397 D#6 D#7 B24 C23 0.535 0.464 AA3 AA6 0.623 0.468 D#38 D#39 N26 N25 0.437 0.383 AG9 AC10 0.724 0.543 A#12 N1 0.394 P5 0.463 D#8 C24 0.515 AE3 0.802 D#40 R21 0.165 AE12 0.558 A#13 M1 0.408 P3 0.576 D#9 B25 0.590 AB7 0.495 D#41 P24 0.343 AF10 0.666 A#14 N2 0.349 N2 0.660 D#10 G22 0.274 AD7 0.609 D#42 R25 0.381 AG11 0.703 A#15 A#16 N4 N5 0.241 0.198 N7 N3 0.407 0.570 D#11 D#12 H21 C26 0.203 0.589 AC7 AC6 0.548 0.579 D#43 D#44 R24 T26 0.329 0.420 AG10 AH11 0.705 0.754 REQ#0 J1 0.427 U6 0.402 D#13 D23 0.462 AC3 0.709 D#45 T25 0.380 AG12 0.669 REQ#1 K5 0.207 T7 0.350 D#14 J21 0.183 AC8 0.590 D#46 T22 0.221 AE13 0.563 REQ#2 J4 0.270 R7 0.393 D#15 D25 0.550 AE2 0.856 D#47 T23 0.279 AF12 0.596 REQ#3 0.337 0.356 U5 U3 0.475 0.599 DBI#0 E21 AD5 0.309 Data Group 0.637 DBI#2 P26 AH9 0.441 Data Group 0.775 REQ#4 J3 H3 DSTBN#1 K22 0.301 AE6 0.693 DSTBN#3 W22 0.298 AC15 0.443 ADSTB#1 R5 0.214 N6 0.438 DSTBP#1 J23 0.306 AE7 0.638 DSTBP#3 W23 0.300 AC16 0.395 A#17 T1 0.470 K4 0.550 D#16 H22 0.272 AG5 0.845 D#48 U26 0.419 AG13 0.668 A#18 A#19 R2 P3 0.404 0.303 M4 M3 0.580 0.648 D#17 D#18 E24 G23 0.480 0.358 AG2 AE8 0.904 0.663 D#49 D#40 U24 U23 0.324 0.270 AH13 AC14 0.712 0.412 A#20 P4 0.246 L3 0.604 D#19 F23 0.418 AF6 0.759 D#51 V25 0.384 AF14 0.548 A#21 R3 0.334 L5 0.521 D#20 F24 0.443 AH2 0.965 D#52 U21 0.167 AG14 0.621 A#22 T2 0.388 K3 0.624 D#21 E25 0.508 AF3 0.798 D#53 V22 0.252 AE14 0.520 A#23 A#24 U1 P6 0.458 0.156 J2 M5 0.685 0.509 D#22 D#23 F26 D26 0.513 0.597 AG3 AE5 0.898 0.709 D#54 D#55 V24 W26 0.341 0.447 AG15 AG16 0.612 0.610 A#25 U3 0.379 J3 0.636 D#24 L21 0.176 AH7 0.863 D#56 Y26 0.454 AG17 0.619 A#26 T4 0.281 L2 0.648 D#25 G26 0.524 AH3 0.904 D#57 W25 0.426 AH15 0.703 A#27 V2 0.417 H4 0.634 D#26 H24 0.412 AF4 0.794 D#58 Y23 0.336 AC17 0.339 A#28 A#29 R6 W1 0.166 0.493 N5 G2 0.472 0.792 D#27 D#28 M21 L22 0.171 0.245 AG8 AG7 0.789 0.785 D#59 D#60 Y24 Y21 0.386 0.222 AF16 AE15 0.580 0.534 A#30 T5 0.217 M6 0.449 D#29 J24 0.401 AG6 0.785 D#61 AA25 0.426 AH17 0.672 A#31 U4 0.285 L7 0.365 D#30 K23 0.313 AF8 0.711 D#62 AA22 0.268 AD17 0.419 D#31 H25 0.473 AH5 0.892 D#63 AA24 0.394 AE16 0.503 DBI#1 G25 0.458 AG4 0.888 DBI#3 V21 0.202 AD15 0.431 Address Group B D C B A A Micro Star Restricted Secret Title Rev CPU/845 Package Length Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Friday, June 01, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 30 of 32 Power Delivery Map ATX 12V POWER Supply D D 3.3V 5V 5VSB 12V 1A VRM9.2 Processor Core Processor Vtt Power Translator ACPI IC MCH Core 1.5V 1.5V VREG MCH Vtt MCH AGP OP 1.8V VREG MCH HUB Interface 1.8V MCH Memory sdr 3.3V C C 3.3V DUAL FET PC-133 System Memory 3.3V 3.3V VREG ICH2 Core 1.8V ICH2 I/O 3.3V ICH2 Resume 1.8V 1.8V VREG ICH2 Resume I/O 1.8V 5V TO 3.3V RESISTOR ICH2 RTC 3.3V ICH2 5V FWH 3.3V B B LPC Super I/O 3.3V CLOCK GEN 3.3V HARDWARE AUDIO 3.3V PCI LAN 3.3V/2.5V 5VDual For USB and K/B A A Micro Star Restricted Secret Title Rev Power Delivery Map Document Number 0A MS-6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Friday, June 01, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www.msi.com.tw Sheet 31 of 32 0A Revision History Change Date D C Sheet Desciption 05/22 05 GTLREF[0:3] just reference to one Reference Voltage GTLREF1 05/22 10 Remove Processor Hot Block Add GPIO21 for Flash Vpp Programing Voltage Control 05/22 13 Change U10 Vpp Circuit for 12V Programming 05/23 04 Remove ITPCLK/ITPCLK# 05/23 05 Restore GTLREF[0,2] reference to GTLREF2 and GTLREF[1,3] to GTLREF1 For Layout Consideration 05/29 13 Add Q92 for Vpp Programing Control Logic 05/31 12 Reserved C109 & R190 for SPDIF Noise Considerarion 06/01 X Rename Schematics file D C B B A A Title Size B Date: Document Number F r i d a y , J une 01, 2001 Rev Sheet 32 of 32 ... Slot Imax VCC_AGP 8 .0A VCC3 6 .0A VCC12 1 .0A VCC5 2 .0A A A Micro Star Restricted Secret Title INTA# INTB# Rev AGP SLOT Document Number 0A MS- 6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Monday,... Title Rev Revision History - Document Number 0A MS- 6506 MICRO-STAR INT'L CO.,LTD Last Revision Date: Friday, June 01, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan http://www .msi. com.tw... VCC1_8 Rev Brookdale MCH Document Number 0A MS- 6506 Last Revision Date: MICRO-STAR INT'L CO.,LTD Monday, June 04, 2001 No 69, Li-De St, Jung-He City, Taipei Hsien, Taiwan Sheet http://www .msi. com.tw