Tài liệu Logic Design with VHDL doc

A B C A B C A B CA C AND: C = A B OR: C = A + B NOT: C = A' Figure 1-1 Basic Gates EXCLUSIVE OR: C = A + B X Y Cin Cout Sum FULL ADDER X Y Cin CoutSum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 1 1 1 1 Figure 1-2 Full Adder (a) Full adder module (b) Truth Table Cout = X'YCin + XY'Cin + XYCin' + XYCin = XY + XCin + YCin Sum = X'Y'Cin + X'YCin' + XY'Cin' + XYCin = X + Y + Cin 1 1 1 1 1 1 0100 11 10 01 00 11 10 AB CD 1 X 1 X 1 four corner terms combine to give B' D' C A'BD F =∑m(0,2,3,5,6,7,8,10,11) + ∑d(14,15) = C + B' D' + A' BD = (B' + C + D) (B + C + D') (A'+B') 0 0 0 0 0 4 6 7 5 13 15 14 10 12 1 3 8 9 11 2 0100 11 10 01 00 11 10 AB CD 0 Figure 1-3 Four-Variable Karnaugh Maps X 1 1 1 1 1 0100 11 10 01 00 11 10 AB CD 1 1 A'C' ACD A'B'D' 0 1 3 2 6 14 10 7 15 11 4 12 8 5 13 9 X Figure 1-4 Selection of Prime Implicants F = A'C' + A'B'D' + ACD + A'BD or F = A'C' + A'B'D' + ACD + BCD 1 X 1 X X 1 1 1 0100 11 10 01 00 11 10 AB CD E = F = 0 MS 0 = A'B' + ACD X X X X X X 1 X X 0100 11 10 01 00 11 10 AB CD E = 0, F = 1 MS 2 = AD X 1 1 X X X X X X X 0100 11 10 01 00 11 10 AB CD E = 1, F = 0 MS 1 = A'D 1 E E X 1 X X 1 F 1 1 0100 11 10 01 00 11 10 AB CD G Figure 1-5 Simplification Using Map-Entered Variables G = MS + EMS + FMS = A'B' + ACD + EA'D + FAD 0 2 1 NAND: NOR: C = (AB)' = A' + B' C = (A+B)' = A'B' C C C C A B A B A B A B Figure 1-6 NAND and NOR Gates D C A B' G E F Z A G' D C' B' E F Z Double inversion cancels Complemented input cancels inversion Figure 1-7 Conversion to NOR Gates (a) AND-OR network (b) Equivalent NOR-gate network A B C D E F A B' C D' E' F Added inverter Added inverter A B C D E F Bubbles cancel Figure 1-8 Conversion of AND-OR Network to NAND Gates (a) AND_OR network (b) First step in NAND conversion (c) Completed conversion Figure 1-9 Elimination of 1-Hazard 0 1 0 1 10 1 0 10 01 00 11 10 A BC C B A F A F = AB' + BC + AC (c) Network with hazard removed C E B A D F 0 1 0 1 10 1 0 10 01 00 11 10 A BC F = AB' + BC 1 - Hazard (a) Network with 1-hazard B D E F 0 ns 10 ns 20 ns 30 ns 40 ns 50 ns 60 ns (b) Timing Chart B' DFF CLK D QQ' D Q Q + 0 0 0 0 1 0 1 0 1 1 1 1 Figure 1-10 Clocked D Flip-flop with Rising-edge Trigger Q = D + [...]... Devices State Change Initiated Here Clock Switching Transients Control Signal (CS) CLK1 = Clock · CS (a) (b) CS CLK2 = Clock + CS Figure 1-35 Incorrect Design Figure 1-36 Correct Design (a) with gated clock Clock CS CLK1 "Rising Edge" Device CK Clock CS (b) With enble CS Enable Clock CK CK CLK2 ... DATA SECTION Condition Signals Data Out Figure 1-32 Timing Chart for System with Falling-Edge Devicves State Change Initiated Here Clock Uncertain Switching Transients Control Signal Clock·CS Figure 1-33 Gated Control Signal Clock CS CK Clock CS CK CLK (a) Faling-edge device (b) Rising-edge device Figure 1-34 Timing Chart with Rising-Edge Devices State Change Initiated Here Clock Switching Transients . + BC + AC (c) Network with hazard removed C E B A D F 0 1 0 1 10 1 0 10 01 00 11 10 A BC F = AB' + BC 1 - Hazard (a) Network with 1-hazard B D E F. D QQ' D Q Q + 0 0 0 0 1 0 1 0 1 1 1 1 Figure 1-10 Clocked D Flip-flop with Rising-edge Trigger Q = D + CK FF Q' Q JK J K Q Q + 0 0 0 0 0 0 1