BENQ r55 quanta TW3A

1 PCB STACK UP TW3A- DESIGN LAYER : TOP DC/DC +3VSUS +5VSUS LAYER : SGND1 A LAYER : IN1 LAYER : IN2 LAYER : VCC LAYER : IN3 RUN POWER SW PG 43 AC/BATT CONNECTOR PG 40 CLOCKS ICS954206 BATT CHARGER PG 40 PG 37 DDRII 667mhz LVDS(2 Channel) Panel Connector TVOUT S-Video PG 35 VGA PG 29 PATA - HDD USB2.0 (P5) Bluetooth PG 33 USB2.0 (P0~P1,P4) USB2.0 I/O Ports PG 26 PCI-E, 1X LAN ICH7-M PATA 100 PG 29 88E8038/88E8055 PG 24 652 BGA PCI-E, 1X Internal ODD CD-ROM PG 18~21 Magnetics PG 25 RJ45 PG 25 Mini PCI-E Card PCI Express Mini Card PCI-E, 1X PG 29 C B PG 23 USB2.0 (P0~P7) SATA0 PG42 VGA,DVI PG 6,7,8,9,10,11 DMI interface SATA - HDD DDRII 16M*16(128MB) 32M*16(256MB) (Bank*4) PG 22 1466 BGA PG 16,17 DC/DC VGA CORE NV72M/MV (64 Bit B/W) Integraded VGA Function DDRII 667mhz nVIDIA PCI-Express 16X Calistoga PM 945PM PG 16,17 DDRII-SODIMM2 PG (478 Micro-FCPGA) PG 4,5 DDRII-SODIMM1 PG37 CPU VR FSB 133MHZ PG 39 DC/DC +1.05V +1.5V PG38 PG43 Yonah/Merom 31W/35W LAYER : BOT B DC/DC +3VPCU +5VPCU A LAYER : SGND2 DDRII VR Azalia PG 33 PCI Bus 33MHz Express Card x1 NEW CARD PG 12,13,14,15 C Power Input PG 33 RQ6 LPT PORT Conexant Audio CX20549-12 COM PORT TI PC7402 LPC PG 30 LAN PG 27 Replicator Daughter Board VGA Headphone MDC DAA CX20548-A PG 32 AUDIO Amplifier PG 31 KBC TPM1.2 PC87541V PG 36 PG 44 USB 1394 IEEE1394 CONN in Card reader PG28 USB X X-Bus PG 35 D D Jack to Speaker PG 31 Audio Jacks PG 30 MODEM RJ 11 PG 32 Key Matrix PG 34 Touch Pad PG 34 Flash PG 36 PCI ROUTING TABLE REQ2# / GNT2# IDSEL AD17 INTERUPT DEVICE INTC#,INTD# TI 7402 PROJECT : TW3 Quanta Computer Inc Size Document Number Rev B1A Block Diagram Date: Thursday, March 09, 2006 Sheet of 47 Board Stack up Description PCB Layers Voltage Rails A A Layer Layer Layer Layer Layer Layer Layer Layer TOP(Component,Other) Voltage Rails Ground Plane VCC_CORE Core voltage for Processor VCCP Core voltage for CPU / NB SMDDR_VTERM 0.9V for DDR2 Termination voltage X X X RVCC1.5 RVCC3 X X VCC1.5 VCC2.5 VCC3 VCC5 X X X X 1.8VSUS 3VSUS 5VSUS X X X X X X 3VPCU 5VPCU 9VPCU X X X X X X IN1 ON S3 ON S4 ON S5 Control signal VR_ON 0.726V~0.94V VR_ON MAINON IN2 Power Plane X X X X RVCC_ON RVCCD IN3 Ground Plane BOTTOM Power On Sequencing Timing Diagram VID Tsft_star_vcc VR_ON Vboot Vid MAIND MAINON MAIND MAIND SUSON SUSD SUSD Tboot Vcc-core Tboot-vid-tr Tcpu_up CPU_UP B ON S0~S2 Vccp X X X X X X VL VL 5VPCU B Tvccp_up Vccp_UP Vccgmch Tgmch_pwrgd GMCHPWRGD ACIN CLK_ENABLE# POWER ON TIMING ACIN Tcpu_pwrgd IMVP4_PWRGD Voltage Rails ON S0~S1 ON S3 ON S4 ON S5 Control signal 5VPCU/3VPCU VCC_CORE Core voltage for Processor X VRON GMCH_VTT Core voltage for GMCH 1.05V X MAINON SMDDR_VTERM SMDDR_VREF 0.9V for DDR II Termination voltage 0.9V for DDR II Reference Voltage X X MAINON MAINON NBSWON# Dothan Power-up Timing Specifications PWRBTN# To ICH7 X GMCH_1.5V From 87541 Td S5_ON 1.8VSUS 1.8V for DDR II voltage MAINON X X SUSON To ICH7 RESET# +2.5V X 3VPCU 3VSUS +3V X X X X X X X VL SUSON MAINON MAINON 5VPCU 5VSUS +5V X X X X X X X VL SUSON MAINON X X X X RSMRST# From ICH7 SUSB#,SUSC# BCLK From 87541 SUSON Tc From 87541 MAINON Te From 87541 VSUS,VCC PWRGOOD From 87541 C C VR_ON Ta VCC Tb Tf VIN POWER SOURCE VCCP/1.05V VCORE_CPU Vcc,boot VID[5:0] CLK_EN# PCI DEVICE IDSEL# PCI7402 AD17 REQ# / GNT# Interrupts REQ2# / GNT2# PIRQ C/D To clock generator 99ms < t 214 PWROK To GMCH/other PCI device PLTRST#\PCIRST# VCCP From ICH7 to CPU H_PWRGD Ta=VCC and VCCP asseration to VID[5:0] vaild Tb=VID[5:0] stable to VCC vaild Tc=BCLK stable to PWRGOOD assertion Td=PWRGOOD to RESET# de-assertion time Te=Vcc,boot vaild to PWRGOOD assertion time 2ms Form GMCH to CPU H_CPURST# D D PROJECT : TW3 Quanta Computer Inc Size Document Number Date: Thursday, March 09, 2006 Rev B1A System Information Sheet of 47 0 133 100 33 1 166 100 33 200 100 33 0 266 100 33 0 333 100 33 1 400 100 33 1 RSVD 100 33 C419 33p/50V VDDA_CR XIN Y1 C434 33p/50V CLK_EN# PM_STPPCI# PM_STPCPU# TI_CLK48M R181 CLKUSB_48 R180