5 SYSTEM PAGE REF Content PAGE D C B 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 40 43 44 45 46 47 48 50 51 52 53 56 57 58 60 61 64 65 66 67 70 Block Diagram System Setting CPU(1)_DMI,PEG,FDI,CLK,MISC CPU(2)_DDR3 CPU(3)_CFG,RSVD,GND CPU(4)_PWR CPU(5)_XDP DDR3 SO-DIMM_0 DDR3 SO-DIMM_1 DDR3 CA_DQ VOLTAGE VID CONTROLLER PCH_IBEX(1)SATA,IHDA,RTC,LPC PCH_IBEX(2)_PCIE,CLK,SMB,PEG PCH_IBEX(3)_FDI,DMI,SYS PWR PCH_IBEX(4)_DP,LVDS,CRT PCH_IBEX(5)_PCI,NVRAM,USB PCH_IBEX(6)CPU,GPIO,MISC PCH_IBEX(7)_POWER,GND PCH_IBEX(8)_POWER,GND PCH_SPI ROM,OTH CLK_ICS9LRS3197 EC_IT8502(1/2) EC_IT8502(2/2)KB, TP,FP RST_Reset Circuit HANKSVILLE LAN-AR8131 AUD-ALC269 AUD-HEADPHONE & SPEAKER CB_R5U230 CB_NewCard BUG_Debug CRT_LCD Panel CRT_D-Sub Display Port TV_HDMI FAN_Fan & Sensor XDD_HDD & ODD USB_USB Port *2 MINICARD(WLAN) LED_Indicator DSG_Discharge PW_PROTECT DC_DC & BAT Conn BT_Bluetooth TUN_TV Tuner ME_Conn & Skew Hole ESA_ESATA PCH_XDP, ONFI VGA_MXM M60J SCHEMATIC Revision 2.00 Page 80 BLOCK DIAGRAM System 1.5VS & 1.05VS DP Display Port Page 82 DDR & VTT Page 47 R1.2, CHANGED HDMI HDMI Page 48 CRT Page 83 +2.5VS DDR3 SO-DIMM DDR3 1066/1333MHz CLARKFIELD nVIDIA NB10P-GS LVDS DDR3 CPU PCIE x16 MXM (R2.1a) CRT Page 84 Page 16~18 Charger Page 70 Page 3~6 Page 46 eDP ONFI Braidwood NV_DQ DMI x4 LCD Panel R1.3,removed Page 86 Detect Page 67 Page 90 Page 45 Load Switch MiniCard Page 91 WLAN Shirley Peak/ Echo Peak C Power Protect Page 53 Page 92 Debug Conn PCIE x1 MiniCard Page 44 Touchpad Page 31 Keyboard Page 31 EC ITE IT8502E R1.32,changed Page 30 ITE IT8301E R1.3,removed USB R1.1,added AR8131 Array Mic.DSP SMBus Audio Amp Page 37 Fortemedia FM2010 Page 40 Cardreader Page 43 Page 38 Azalia Azalia MDC Azalia Codec R1.2, CHANGED CardReader+1394 R1.2, CHANGED Page 64 12 USB Port(3) HDD(2) Bluetooth 1.1 Page 61 13 USB Port(4) Page 51 Page 40 TV Tuner Page 52 PCIE x1 MiniCard Page 65 HDD(1) Page 51 USB Port(2) Page 51 Page 36 Finger Print 1.1 Page 52 eSATA 10 Page 66 NC Page 31 NC 3G Page 40 OLED Page 68 Page 53 11 VID controller Page 19 Clock Generator ICS9LRS3197 PWM Fan R1.3,changed Page 29 Page 57 USB Port(5) Page 45 Page 60 Reset Circuit Page 50 NC DC & BATT Conn Discharge Circuit B USB Port(1) Page 65 ODD CMOS Camera Page 45 Ricoh R5U230 PW_VCORE(MAX17034) PW_SYSTEM(MAX17020) PW_I/O_VTT_CPU&+1.1VM PW_I/O_DDR & VTT& +1.8VS PW_I/O_3VM & ME_+VM_PWEGD PW_+VGFX_CORE(MAX17028) PW_CHARGER(MAX17015) PW_DETECT PW_LOAD SWITCH PW_SIGNAL PW_FLOWCHART ExpressCard SATA Realtek ALC269 Jack Page 34 Page 28 Page 35 R1.2, REMOVED R1.3,changed Page 20~28 SPI BIOS ROM INT MIC Page 45 Page 66 RJ45 Page 33 Page 30 Page 45 PRE-ES1 SATA solution Remove when fixed GigaLAN R1.32 R1.32 Array Mic ESATA controller Page 64 SPI EC ROM R1.1,removed R1.1,removed R1.1,removed TV Tuner PCH Ibex Peak-M PM55 LPC Page 31 1394 Skew Holes Page 32 Page 65 Title : Block Diagram Engineer: ASUSTeK COMPUTER INC NB4 Size Date: James1_Wu Project Name Rev M60J C D Page 81 A Power VCORE Page 65 80 81 82 83 84 86 88 90 91 93 94 2.00 Sheet Thursday, July 09, 2009 1 of 99 A PCH_IBEX GPIO D C B A PCH_IBEX GPIO GPIO 00 GPIO 01 GPIO [2:5] GPIO 06 GPIO 07 GPIO 08 GPIO 09 GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 GPIO 16 GPIO 17 GPIO 18 GPIO 19 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 31 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 GPIO 42 GPIO 43 GPIO 44 GPIO 45 GPIO 46 GPIO 47 GPIO 48 GPIO 49 GPIO 50 GPIO 51 GPIO 52 GPIO 53 GPIO 54 GPIO 55 GPIO 56 GPIO 57 GPIO 58 GPIO 59 GPIO 60 GPIO 61 GPIO 62 GPIO 63 GPIO 64 GPIO 65 GPIO 66 GPIO 67 GPIO 72 GPIO 73 GPIO 74 GPIO 75 Use As Internal & External Pull-up/down Signal Name GPO GPO GPI GPO GPO GPI Native Native GPI Native GPO GPO GPO GPI GPI GPI GPI Native GPI GPO Native GPO GPI GPI GPO GPO Native GPO Native GPIO GPI Native GPO GPI GPI GPI GPI Native Native Native Native Native Native Native GPI GPO GPIO Native Native NC_TP NC_TP PCI_INT[E:H]# NC_TP NC_TP EXT_SMI# NC_PU NC_PU EXT_SCI# NC_TP NC_TP NC_PU BT_LED DGPU_HOLD_RST# DGPU_PWROK CLKREQ1#_TV SATA1GP CLKREQ2#_WLAN SATA0GP WLAN_LED NC_TP NC_TP CLKREQ3#_NEWCARD CLK_REQ4#_CB NC_TP WLAN_ON# NC_TP ME_SusPwrDnAck ME_AC_PRESENT PM_CLKRUN# HDA_DOCK_EN# NC_TP SATA_CLK_REQ# DGPU_PWR_EN# DGPU_PRSNT# PCB_ID0 PCB_ID1 NC_PU NC_PU NC_PU NC_PU CLK_REQ5# NC_TP NC_TP CLKREQ_PEG# NC_TP PCH_TEMP_ALERT# PCI_REQ1# PCI_GNT1# DGPU_SELECT#_R NC_TP PCI_REQ3# PCI_GNT3# CLKREQ_GLAN# BT_ON SML1_CLK NC_PU SML0ALERT# NC_TP NC_TP NC_TP NC_TP NC_TP NC_TP NC_TP PM_BATLOW# CLK_REQ0# SML1ALERT# SML1_DATA Native GPO Native Native GPI GPO GPIO Native Native Native Native Native Native Native Native Native Native Native Native GPIO Power - +3VS INT TBD +3VS EXT PU +5VS INT TBD +3VS INT TBD +3VS EXT PU & INT PU +3VSUS EXT PU +3VSUS EXT PU +3VSUS EXT PU +3VSUS +3VSUS +3VSUS EXT PU +3VSUS INT PD +3VSUS EXT PU +3VS EXT PD & INT TBD +3VS EXT PD +3VS EXT PU +3VS EXT PD +3VS EXT PU +3VS EXT PD +3VS INT PU +3VS +3VSUS EXT PD +3VSUS EXT PD +3VSUS INT WEAK PU +3VSUS EXT PD +3VSUS EXT PU(DNI)/PD(DNI) +3VSUS EXT PU +3VSUS EXT PU +3VSUS EXT PU +3VS +3VS +3VS +3VS EXT PD +3VS EXT PU EXT PU +3VS EXT PD +3VS EXT PD +3VS EXT PU +3VSUS EXT PU +3VSUS EXT PU +3VSUS EXT PU +3VSUS EXT PU +3VSUS EXT PU +3VSUS EXT PU +3VSUS EXT PU +3VSUS +3VS EXT PU +3VS EXT PU +5VS INT PU +3VS EXT PU +5VS INT PU +3VS EXT PU +5VS INT PU +3VS EXT PD +3VSUS EXT PU(DIODE) +3VSUS EXT PU +3VSUS EXT PU +3VSUS EXT PU +3VSUS +3VSUS +3VSUS +3VSUS INT TBD +3VS INT TBD +3VS INT TBD +3VS INT TBD +3VS EXT PU +3VSUS EXT PU +3VSUS EXT PU +3VSUS EXT PU +3VSUS EC IT8541 EC GPIO GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 GPC0 GPC1 GPC2 GPC3 GPC4 GPC5 GPC6 GPC7 GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 GPD6 GPD7 GPE0 GPE1 GPE2 GPE3 GPE4 GPE5 GPE6 GPE7 GPF0 GPF1 GPF2 GPF3 GPF4 GPF5 GPF6 GPF7 GPG0 GPG1 GPG2 GPG6 GPH0 GPH1 GPH2 GPH3 GPH4 GPH5 GPH6 GPI0 GPI1 GPI2 GPI3 GPI4 GPI5 GPI6 GPI7 GPJ0 GPJ1 GPJ2 GPJ3 GPJ4 GPJ5 Use As O O O O O O O IO IO O O O IO IO O I O I I I I I O O O I O O O O I I O I I IO O O I I IO O O O O O O I I I I I I I O O O O O Signal Name PWR_LED# CHG_LED# LCD_BL_PWM FAN0_PWM BATSEL_0 BATSEL_1 ME_AC_PRESENT_EC SMB0_CLK SMB0_DAT A20GATE RCIN# PM_RSMRST# SMB1_CLK SMB1_DAT PM_PWRBTN# AC_IN_OC# OP_SD# BAT1_IN_OC# RFON_SW# PWRLIMIT# PM_SUSC# BUF_PLT_RST# EXT_SCI# EXT_SMI# LCD_BACKOFF# FAN0_TACH VSUS_ON EGAD (IT8301 Address/Data connect) EGCS (IT8301 Cycle Start connect) EGCLK (IT8301 Clock connect) PWR_SW# LID_SW# EXP_GATE# TP_CLK TP_DAT THRO_CPU PCH_SPI_OV ME_SusPwrDnAck_EC PM_SUSB# PM_CLKRUN# GFX_VR_ON CHG_EN SUSC_EC# SUSB_EC# NUM_LED# CAP_LED# SUS_PWRGD ALL_SYSTEM_PWRGD VRM_PWRGD PCH_TEMP_ALERT# ALS_AD CAP_ACK_A# CAP_ACK_B# CPU_VRON PM_PWROK VSET_EC ISET_EC TP_LED - EC IT8301 EC GPIO GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 R1.3 removed Use As I I I I O O O Signal Name ME_PM_SLP_M# ME_SusPwrDnAck ME_+VM_PWRGD ME_PM_SLP_LAN# ME_AC_PRESENT ME_PWROK ME_SLP_M_EC# - PCIE Minicard TV Tuner PCIE Minicard WLAN PCIE Newcard PCIE PCIE Card reader PCIE GLAN PCIE PCIE D SATA SATA HDD (1) SATA1 SATA ODD SATA4 SATA HDD (2) SATA5 ESATA USB USB Port (1) USB USB Port (2) USB USB Port (3) USB USB Port (4) USB Minicard TV Tuner USB NewCard USB USB USB WLAN USB CMOS Camera USB 10 USB 11 Bluetooth USB 13 Finger Printer SM_BUS ADDRESS : PCH Master SM-Bus Device SM-Bus Address Clock Generator(ICS9LRS3197) 1101001x ( D2 ) SO-DIMM 1010000x ( A0 ) SO-DIMM 1010001x ( A2 ) VID Controller(ASM8272) 0011011x ( 36 ) WiFi/WiMax N/A B EC Master (SMB1) SM-Bus Device SM-Bus Address CPU Thermal Sensor - VGA Thermal IC(G781-1) 1001101x ( 9A ) Device Identification CPU Thermal Sensor P/N: component name Clock Gen P/N: component name 1st S S S 1st 06G011604010 ICS9LRS3197 S S A VGA Thermal Sensor 1st component name 06G023048020 G781-1 S S Title : System Setting Engineer: ASUSTeK COMPUTER INC NB4 Size James1_Wu Project Name Rev M60J C Date: C USB 12 2.00 Sheet Thursday, July 09, 2009 of 99 U0301A DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 D24 G24 F23 H23 22 22 22 22 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 D25 F24 E23 G23 R1.2,item L2 F17 E17 FDI_INT C17 FDI_LSYNC0 FDI_LSYNC1 F18 D17 FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] FDI_FSYNC[0] FDI_FSYNC[1] FDI_INT FDI_LSYNC[0] FDI_LSYNC[1] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] 750Ohm K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 PCIENB_RXN0 PCIENB_RXN1 PCIENB_RXN2 PCIENB_RXN3 PCIENB_RXN4 PCIENB_RXN5 PCIENB_RXN6 PCIENB_RXN7 PCIENB_RXN8 PCIENB_RXN9 PCIENB_RXN10 PCIENB_RXN11 PCIENB_RXN12 PCIENB_RXN13 PCIENB_RXN14 PCIENB_RXN15 J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PCIENB_RXP0 PCIENB_RXP1 PCIENB_RXP2 PCIENB_RXP3 PCIENB_RXP4 PCIENB_RXP5 PCIENB_RXP6 PCIENB_RXP7 PCIENB_RXP8 PCIENB_RXP9 PCIENB_RXP10 PCIENB_RXP11 PCIENB_RXP12 PCIENB_RXP13 PCIENB_RXP14 PCIENB_RXP15 PCIENB_RXN[15:0] R1.1,item L11 Main Board R0366 R0367 CLKDREF CLKDREF# 70 1KOhm 1KOhm Place near R0328,R0329 SKTOCC#:pulled to ground on processor may use to determine if CPU is present U0301B PCIENB_RXP[15:0] 70 20Ohm 1% R0303 H_COMP3 AT23 20Ohm 1% R0304 H_COMP2 AT24 49.9Ohm 1% R0305 H_COMP1 G16 49.9Ohm 1% R0306 H_COMP0 AT26 T0301 1TP_SKTOCC# +VTT_CPU 49.9Ohm H_CATERR# For EC request, to read PECI via EC Connection: R0317.2 >Q0301.1 >U3001.118 1% COMP2 COMP1 COMP0 SKTOCC# R0307 AK14 0Ohm THRO_CPU AH24 COMP3 CATERR# @ R0317 +VTT_CPU 25 SL0310 H_PECI R0310 don't remove L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PCIENB_TXN0 PCIENB_TXN1 PCIENB_TXN2 PCIENB_TXN3 PCIENB_TXN4 PCIENB_TXN5 PCIENB_TXN6 PCIENB_TXN7 PCIENB_TXN8 PCIENB_TXN9 PCIENB_TXN10 PCIENB_TXN11 PCIENB_TXN12 PCIENB_TXN13 PCIENB_TXN14 PCIENB_TXN15 CX0301 CX0302 CX0303 CX0304 CX0305 CX0306 CX0307 CX0308 CX0309 CX0310 CX0311 CX0312 CX0313 CX0314 CX0315 CX0316 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V PCIEG_RXN0 PCIEG_RXN1 PCIEG_RXN2 PCIEG_RXN3 PCIEG_RXN4 PCIEG_RXN5 PCIEG_RXN6 PCIEG_RXN7 PCIEG_RXN8 PCIEG_RXN9 PCIEG_RXN10 PCIEG_RXN11 PCIEG_RXN12 PCIEG_RXN13 PCIEG_RXN14 PCIEG_RXN15 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 PCIENB_TXP0 PCIENB_TXP1 PCIENB_TXP2 PCIENB_TXP3 PCIENB_TXP4 PCIENB_TXP5 PCIENB_TXP6 PCIENB_TXP7 PCIENB_TXP8 PCIENB_TXP9 PCIENB_TXP10 PCIENB_TXP11 PCIENB_TXP12 PCIENB_TXP13 PCIENB_TXP14 PCIENB_TXP15 CX0317 CX0318 CX0319 CX0320 CX0321 CX0322 CX0323 CX0324 CX0325 CX0326 CX0327 CX0328 CX0329 CX0330 CX0331 CX0332 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V PCIEG_RXP0 PCIEG_RXP1 PCIEG_RXP2 PCIEG_RXP3 PCIEG_RXP4 PCIEG_RXP5 PCIEG_RXP6 PCIEG_RXP7 PCIEG_RXP8 PCIEG_RXP9 PCIEG_RXP10 PCIEG_RXP11 PCIEG_RXP12 PCIEG_RXP13 PCIEG_RXP14 PCIEG_RXP15 PCIEG_RXN[15:0] H_PROCHOT_S# H_PECI_ISO 0402 R0322 AT15 H_PROCHOT_S#_R AN26 0402 SL0312 25 H_THRMTRIP# PECI 68OHM SL0311 70 H_THRMTRIP#_R 0402 AK15 PROCHOT# THERMTRIP# R2.00,item L5 T0302 H_CPURST# 22 PM_SYNC# 70 PM_SYNC#_R 0402 7,25 H_CPUPWRGD AN14 SL0315 1VCCPWRGOOD_0_R AN27 SL0316 1VDDPWRGOOD_R 0402 AK13 AM15 58 H_VTTPWRGD AM26 H_PWRGD_XDP 7,24,30,32,33,40,43,45,53,64,67,70 AL15 SL0314 1VCCPWRGOOD_1_R 0402 22 H_DRAM_PWRGD BUF_PLT_RST# 1% R0318 1.5KOhm PEG_CLK PEG_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK# SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] PM_EXT_TS#[0] PM_EXT_TS#[1] PLT_RST#_R AL14 RESET_OBS# PM_SYNC VCCPWRGOOD_1 VCCPWRGOOD_0 SM_DRAMPWROK VTTPWRGOOD TAPPWRGOOD A16 B16 D CLK_CPU_BCLK CLK_CPU_BCLK# CLK selection AR30 CLK_ITP_BCLK_R AT30 CLK_ITP_BCLK#_R TCK TMS TRST# TDI TDO TDI_M TDO_M DBR# BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] SL0317 0402 SL0318 CLK_ITP_BCLK CLK_ITP_BCLK# 0402 E16 CLK_EXP_P D16 CLK_EXP_N A18 A17 CLKDREF CLKDREF# R1.2,item L2 F6 M_DRAMRST# AL1 SM_RCOMP0 R0331 AM1 SM_RCOMP1 R0332 AN1 SM_RCOMP2 R0333 AN15 AP15 1% 1% 1% 16,17 100Ohm 24.9Ohm 130OHM PM_EXTTS#0 16,17 PM_EXTTS#1 +VTT_CPU RN0301A 10KOHM RN0301B 10KOHM PRDY# PREQ# AP26 SL0313 BCLK_ITP BCLK_ITP# SM_DRAMRST# 0402 PCIEG_RXP[15:0] BCLK BCLK# AT28 AP27 XDP_PRDY# XDP_PREQ# AN28 AP28 AT27 XDP_TCLK XDP_TMS XDP_TRST# AT29 AR27 AR29 AP29 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M AN25 H_DBR#_R 7 C AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 XDP_OBS0_R XDP_OBS1_R XDP_OBS2_R XDP_OBS3_R XDP_OBS4_R XDP_OBS5_R XDP_OBS6_R XDP_OBS7_R R0336 0Ohm RX03371 RX03381 RX03391 RX03401 RX03411 RX03421 RX03431 RX03441 2 2 2 2 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm 0Ohm XDP_DBRESET# 7,22,67 XDP_OBS[7:0] XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 R0319 750Ohm 1% RSTIN# SOCKET989 For Intel GFX display PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] 49.9Ohm 1% PWR MANAGEMENT C FDI_FSYNC0 FDI_FSYNC1 FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] 1% THERMAL D22 C21 D20 C18 G22 E20 F20 G19 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] Intel(R) FDI E22 D21 D19 D18 G21 E19 F21 G18 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] R0302 CLOCKS 22 22 22 22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] R0301 EXP_RBIAS DDR3 MISC B24 D23 B23 A22 PEG_IRCOMP_R JTAG & BPM DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 B26 A26 B27 A25 22 22 22 22 PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] PCI EXPRESS GRAPHICS A24 C23 B22 A21 MISC DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI D 22 22 22 22 SOCKET989 DG R1.11 P.09: R1.2,item B1 SL0301 SL0302 0402 0402 CLK_CPU_BCLK H_CPURST# R0313 @ 68OHM CLK_CPU_BCLK# XDP_TMS R0345 @ 51Ohm XDP_TDI_R R0346 @ 51Ohm 21 CLK_DMI_PCH XDP_PREQ# R0347 @ 51Ohm SL0304 0402 0402 XDP_TCLK R0348 @ 51Ohm CLK_EXP_P CLK_EXP_N B R0320 1.1KOhm 1% VDDPWRGOOD_R 21 CLK_DMI#_PCH SL0303 +1.5V *On Clarksfield rPGA only designs, VCCPWRGOOD_1 on the Clarksfield processor can be left as No Connect 25 BCLK_CPU_N_PCH B DG R1.1 P.109: 25 BCLK_CPU_P_PCH DRAMPWROK: (DGU R1.52) +VTT_CPU R1.1,item L8 R0321 3.01KOHM 1% R1.3,item B5 FDI disable: (For discrete graphic) NC: FDI_TX#[0:7],FDI_TX[0:7],FDI_RX#[0:7],FDI_RX[0:7] VCC_AXGSENSE,VSS_AXGSENSE JTAG MAPPING XDP_TDI_R Pull-down to GND via 1KΩ ± 5% resistor: XDP_TDO_M FDI_FSYNC[0:1],FDI_LSYNC[0:1],FDI_INT,GFX_IMON 0402 R0350 SL0308 XDP_TDI 0Ohm XDP_TDO @ XDP_TRST# 1 ~15mW power saving.(DG R0.8 P.70) R0351 Connected to GND: VCCAXG, R0354 51Ohm XDP_TDI_M DPLL_REF_CLK,DPLL_REF_CLK# R0352 XDP_TDO_R Connect to +V1.05S rail: 0402 0Ohm SL0309 VCCFDIPLL DG R1.1 P.83: A 1KOhm 1 0402 0402 0402 R0364 SL0305 SL0306 SL0307 H_PROCHOT_S# @ 1KOhm R0363 R1.2,item L2 *FDI_FSYNC[0],FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1] can be ganged together with one resistor *On the other hand,FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on PCH side can be left as no connect without any power or functional impact 30,88 PWRLIMIT# D0301 RB751V-40 R1.31,item B2 FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1 FDI_INT R1.1,item L10 D Q0301 2N7002ET1G 11 S G THRO_CPU Title : 30 2 A @ 2 0Ohm Can be connected to GND directly: Size CPU(1)_DMI,PEG,FDI,CLK,MISC James1_Wu Project Name Rev M60J C Date: Engineer: ASUSTeK COMPUTER INC NB1 2.00 Sheet Friday, July 10, 2009 of 99 Main Board U0301C U0301D 16 M_A_DQ[63:0] C B A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14 16 16 16 M_A_BS0 M_A_BS1 M_A_BS2 AC3 AB2 U7 16 16 16 M_A_CAS# M_A_RAS# M_A_WE# AE1 AB3 AE9 SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] SA_BS[0] SA_BS[1] SA_BS[2] SA_CAS# SA_RAS# SA_WE# AA6 AA7 P7 M_CLK_DDR0 16 M_CLK_DDR#0 16 M_CKE0 16 D 17 M_B_DQ[63:0] SA_CK[1] SA_CK#[1] SA_CKE[1] SA_CS#[0] SA_CS#[1] SA_ODT[0] SA_ODT[1] SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] Y6 Y5 P6 M_CLK_DDR1 16 M_CLK_DDR#1 16 M_CKE1 16 AE2 AE8 M_CS#0 M_CS#1 16 16 AD8 AF9 M_ODT0 M_ODT1 16 16 B9 D7 H7 M7 AG6 AM7 AN10 AN13 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 C9 F8 J9 N9 AH7 AK9 AP11 AT13 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 C8 F9 H9 M9 AH8 AK10 AN11 AR13 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 M_A_DM[7:0] 16 M_A_DQS#[7:0] M_A_DQS[7:0] M_A_A[15:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 16 16 16 B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 17 17 17 M_B_BS0 M_B_BS1 M_B_BS2 AB1 W5 R7 17 17 17 M_B_CAS# M_B_RAS# M_B_WE# AC5 Y7 AC6 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_BS[0] SB_BS[1] SB_BS[2] SB_CAS# SB_RAS# SB_WE# SB_CK[0] SB_CK#[0] SB_CKE[0] SB_CK[1] SB_CK#[1] SB_CKE[1] SB_CS#[0] SB_CS#[1] SB_ODT[0] SB_ODT[1] SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] DDR SYSTEM MEMORY - B M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 DDR SYSTEM MEMORY A D SA_CK[0] SA_CK#[0] SA_CKE[0] SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] W8 W9 M3 M_CLK_DDR2 17 M_CLK_DDR#2 17 M_CKE2 17 V7 V6 M2 M_CLK_DDR3 17 M_CLK_DDR#3 17 M_CKE3 17 AB8 AD6 M_CS#2 M_CS#3 17 17 AC7 AD1 M_ODT2 M_ODT3 17 17 D4 E1 H3 K1 AH1 AL2 AR4 AT8 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 D5 F4 J4 L4 AH2 AL4 AR5 AR8 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 C5 E3 H4 M5 AG2 AL5 AP5 AR7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 M_B_DM[7:0] 17 M_B_DQS#[7:0] M_B_DQS[7:0] M_B_A[15:0] 17 C 17 17 B SOCKET989 SOCKET989 A A Title : CPU(2)_DDR3 Engineer: ASUSTeK COMPUTER INC NB1 Size Rev M60J C Date: James1_Wu Project Name 2.00 Sheet Friday, July 10, 2009 of 99 Main Board D D U0301H U0301I RSVD32 RSVD33 18 DIMM0_VREF_DQ 18 DIMM1_VREF_DQ AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 10mil trace J17 10mil trace H17 G25 G17 E31 E30 RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREFDQ SB_DIMM_VREFDQ RSVD11 RSVD12 RSVD13 RSVD14 RSVD34 RSVD35 RSVD36 RSVD_NCTF_37 RSVD38 RSVD39 RSVD_NCTF_40 RSVD_NCTF_41 C T0578 T0567 T0566 T0565 T0569 T0568 T0571 T0572 T0574 T0570 T0575 T0573 T0576 T0577 T0592 T0581 T0580 T0579 T0583 1 1 1 1 1 1 1 1 1 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 B19 A19 0Ohm R0501 0Ohm R0502 H_RSVD17_R H_RSVD18_R A20 B20 U9 T9 AC9 AB9 T0513 T0510 1 C1 A3 J29 J28 B T0511 T0512 1 A34 A33 T0514 T0515 1 C35 B35 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 RESERVED RSVD_NCTF_42 RSVD_NCTF_43 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 AJ13 AJ12 AH25 AK26 AL26 AR2 T0504 AP1 AT2 1 T0501 T0506 AT3 AR1 1 T0507 T0503 1 1 T0508 T0509 T0502 T0505 AJ26 AJ27 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 E15 F15 A2 D15 C15 AJ15 RSVD64_R AH15 RSVD65_R R0505 R0506 0Ohm 0Ohm RSVD15 RSVD16 RSVD17 RSVD18 RSVD19 RSVD20 RSVD21 RSVD22 RSVD_NCTF_23 RSVD_NCTF_24 RSVD26 RSVD27 RSVD_NCTF_28 RSVD_NCTF_29 RSVD_NCTF_30 RSVD_NCTF_31 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 VSS AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 AP34 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 C VSS NCTF U0301E VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 AT1 AR34 B34 B2 B1 A35 TP_MCP_VSS_NCTF1 TP_MCP_VSS_NCTF2 1 T0564 T0561 TP_MCP_VSS_NCTF6 TP_MCP_VSS_NCTF7 1 T0563 T0562 B SOCKET989 SOCKET989 SOCKET989 CFG strapping information: CFG[1:0]: PCI Express Port Bifurcation:(Clarksfield Only) - 11 = x 16 PEG (Default) - 10 = x PEG CFG[3]: PCIE Static Numbering Lane Reversal.(Auburndale Only) - 1:Normal Operation (Default) - 0:Lane Numbers Reversed 15 -> 0, 14 -> 1, CFG[4]: Embedded DisplayPort Detection.(Auburndale Only) - 1:Disabled - No Physical Display Port attached to Embedded DisplayPort - 0:Enabled - An external Display Port device is connected to the Embedded Display Port CFG[7]: Fixed for PCI Express 2.0 jitter specifications.(Clarksfield) Clarksfield (only for early samples pre-ES1) - Connect to GND with 3.01K Ohm/5% resistor For a common motherboard design (for AUB and CFD), the pull-down resistor should be used Does not impact AUB functionality Unmount if Intel has fixed this issue Intel sighting #: 402607(3393727) To drive a value of zero on CFG[0] pin use a 250 Ohm pull down resistor to Vss CFG0 @ 3.01KOHM 1% @ CFG3 R0536 3.01KOHM 1% @ CFG4 R0537 3.01KOHM eDP=3.3K PD 1% CFG7 A R0535 R0538 @ 3.01KOHM A 1% Note: (Auburndale)Hardware Straps are sampled on the asserting edge of VCCPWRGOOD_0 and VCCPWRGOOD_1 and latched inside the processor R1.1,item B1 Title : CPU(3)_CFG,RSVD,GND Note: (Clarksfield)Hardware Straps are sampled after RSTIN# de-assertion Engineer: ASUSTeK COMPUTER INC NB1 Size Rev M60J C Date: James1_Wu Project Name Friday, July 10, 2009 2.00 Sheet of 99 R2.00,item L5 2 @ 330UF/2V CE0604 PANASONIC/EEFSX0D331XE ESR=6mOhm/Ir=3A C0685 C0686 22UF/6.3V 22UF/6.3V C0625 1UF/10V C0624 1 C0622 C0621 C0623 1UF/10V 1UF/10V 1UF/10V R1.2,item B1 + P10 N10 L10 K10 C0626 C0627 SENSE LINES 10UF/6.3V 10UF/6.3V C 0Ohm PM_DPRSLPVR C0664 C0666 C0668 C0667 2 22UF/6.3V 22UF/6.3V +1.8VS 4.7UF/6.3V SOCKET989 R0601 C0665 19 1 80 C0629 C0659 22UF/6.3V L26 L27 M26 C0628 C0658 22UF/6.3V VCCPLL1 VCCPLL2 VCCPLL3 2.2UF/10V CPU_VID[0:6] 22UF/6.3V 1.1V C0657 22UF/6.3V J22 J20 J18 H21 H20 H19 PM_PSI# VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 Intel use 22u 1.8V C0656 22UF/6.3V VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 1UF/10V 0Ohm H_VTTVID1 D 4.7KOhm DG R1.1,P41 1xbuck Stuffing option G15 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 PM_DPRSLPVR_R 1UF/10V AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 1UF/10V POWER CPU VIDS VTT_SELECT AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 R0606 +VTT_CPU K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 PEG & DMI VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR 1KOhm C0655 C0654 AR25 GFX_VRON_EN AT25 GFXVR_DPRSLPVR AM24 GVR_PWR_MON R0613 4.7KOhm +VTT_CPU Intel use 22u R0616 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 VTT0_59 VTT0_60 VTT0_61 VTT0_62 22UF/6.3V 22UF/6.3V C0618 22UF/6.3V VTT1_45 VTT1_46 VTT1_47 Intel use 22u R1.2,item L4 AN33 GVR_PWR_MON R0605 +VTT_CPU Intel use 22u PSI# GFX_VR_EN GFX_DPRSLPVR GFX_IMON AM22 AP22 AN22 AP23 AM23 AP24 AN24 C0689 10UF/6.3V C0688 C0687 10UF/6.3V C0617 AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 22UF/6.3V VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] AR22 AT22 +1.5V +VTT_CPU J24 J23 H25 VAXG_SENSE VSSAXG_SENSE GRAPHICS VIDs C0616 C0615 C0613 C0611 C0608 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V 10UF/6.3V C0606 1 C0602 C0601 C0604 10UF/6.3V 10UF/6.3V 2 10UF/6.3V 10UF/6.3V @ +VTT_CPU 10UF/6.3V 1.1V RAIL POWER R1.2,item L2 FDI Intel 1.8V CAP 1u: 2/2 2.2u: 1/1 4.7u: 1/1 330u:1/1 80 Processor Decoupling 82 VTT_TEST TBD Decoupling guide from Intel +VCORE Schematic Checklist R0.7: B Schematic R0.9: ISENSE AN35 I_MON R0602 100Ohm 1% 80 VCORE 22uF * 16pcs VCORE 22uF * 12pcs 10uF * 16pcs 10uF * 16pcs R2.00,item B5 AJ34 AJ35 VCCSENSE VSSSENSE 80 80 470uF* 6pcs(2 no stuff) 470uF* 6pcs(2 no stuff) +VCORE 22UF/6.3V 22UF/6.3V 22UF/6.3V 1 C0638 22UF/6.3V C0637 C0644 2 1 22UF/6.3V C0643 C0636 C0645 22UF/6.3V 22UF/6.3V 22UF/6.3V C0642 C0635 22UF/6.3V 22UF/6.3V C0641 C0634 22UF/6.3V 22UF/6.3V C0640 C0633 22UF/6.3V 1 C0632 R0603 100Ohm 1% T0632 T0631 1 VTT_SENSE TP_VSS_SENSE_VTT B15 A15 VTT_SENSE VSS_SENSE_VTT 1 VCC_SENSE VSS_SENSE SENSE LINES B @ 0Ohm +VTT_CPU +VTT_CPU CPU CORE SUPPLY C AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 GRAPHICS D VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 - 1.5V RAILS AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 R0607 R2.00,item B5 VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 R1.2,item L2 U0301F AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 Main Board U0301G T0633 +VCORE +VGFX_CORE DDR3 Add Jumper to measure power? POWER C0639 22UF/6.3V C0647 22UF/6.3V SOCKET989 10UF/6.3V C0675 10UF/6.3V C0674 10UF/6.3V C0673 10UF/6.3V C0672 10UF/6.3V C0671 10UF/6.3V C0670 10UF/6.3V C0669 2 8/5 delete C0646 (22UF,6.3V) for layout placement (+1.8VS,VCCPLL) C0676 10UF/6.3V 10UF/6.3V C0683 10UF/6.3V C0682 10UF/6.3V C0681 10UF/6.3V C0680 10UF/6.3V C0679 10UF/6.3V C0678 10UF/6.3V 2 C0677 A A C0684 10UF/6.3V Title : CPU(4)_PWR Engineer: ASUSTeK COMPUTER INC NB1 Size Rev M60J C Date: James1_Wu Project Name 2.00 Sheet Friday, July 10, 2009 of 99 Main Board D D CPU XDP connector +VTT_CPU J0701 31 C R1.3,item L21 32 SIDE1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SIDE2 30 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 T0720 T0721 0Ohm 1 C R0709 CPUPWRGD_XDP 1KOhm R0708 HBPM3# HBPM2# HBPM1# HBPM0# 51Ohm R0711 XDP_RST#_R T0716 T0717 T0718 T0719 1KOhm R0707 H_PWRGD_XDP XDP_TRST# H_CPUPWRGD 3,25 (54) (39) ( 3) ( 5) XDP_TDO XDP_TDI (52) (56) XDP_TMS XDP_TCLK (58) (57) XDP_DBRESET# H_CPURST# 3,22,67 (48) (46) SMB_DAT_S 16,17,28,29,44,53,67 SMB_CLK_S 16,17,28,29,44,53,67 CLK_ITP_BCLK# CLK_ITP_BCLK (42) (40) (44) +VTT_CPU XDP_RST#_R R0715 0Ohm T0722 T0723 T0724 T0725 T0726 T0727 T0728 T0729 1 1 1 1 XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 T0730 PM_PWRBTN#_R J0701 (45) XDP_PREQ# XDP_PRDY# FPC_CON_30P B @ BUF_PLT_RST# 3,24,30,32,33,40,43,45,53,64,67,70 B 3 3 3 3 22 FFC path Put these test point near J0701 Put it away from the FFC path A A Title : CPU(5)_XDP Engineer: ASUSTeK COMPUTER INC NB1 Size Rev M60J C Date: James1_Wu Project Name 2.00 Sheet Friday, July 10, 2009 of 99 D D C C B B A A Title : ASUSTeK COMPUTER INC NB1 Size NB_**** James1_Wu Project Name Custom Date: Engineer: Rev M60J 2.00 Thursday, July 02, 2009 Sheet of 99 Main Board D D C C B B A A Title : NB_**** ASUSTeK COMPUTER INC NB1 Size James1_Wu Project Name Custom Date: Engineer: Rev M60J 2.00 Thursday, July 02, 2009 Sheet of 99 Main Board D D C C B B A A Title : NB_**** ASUSTeK COMPUTER INC NB1 Size James1_Wu Project Name Custom Date: Engineer: Rev M60J 2.00 Thursday, July 02, 2009 Sheet 10 of 99 AC_BAT_SYS R8101 1 2 R1.2 1 +3VA 2 SL8101 1MM_OPEN_5MIL 0402 0Ohm @ GND_17020 17020_DL1 20mil C8118 C8122 4.7UF/6.3V 2 2 1 C8113 10UF/6.3V CE8102 150UF/6.3V ESR=19mOhm/Ir=2780mA 2 1 2 +12VSUS 1MM_OPEN_5MIL C8123 1UF/25V 2 CPU_VRON_PWR SUSB_EC# 70,82,83,91 +5VAO T8104 TPC28T +3VA T8105 TPC28T +5VA T8106 TPC28T 2 SUSC_EC# 30,57 +3VAO T8107 TPC28T +12VSUS SUSC#_PWR 83,91 1KOhm @ VSUS_ON 30 T8108 TPC28T T8109 TPC28T VSUS_ON_PWR VSUS_ON_PWR 82 R1.1 T8110 TPC28T SUSB_EC# T8111 TPC28T SUSC_EC# T8112 TPC28T CPU_VRON T8113 TPC28T SUS_PWRGD ENBL SGL_JUMP +12VSUS R1.2 R8126 1KOhm Imax=100mA J8108 B 32,58 FORCE_OFF# C8126 1UF/25V @ R1.2 ENBL SHORTPIN 2 1 C8125 @ 1UF/25V +5VSUS T8103 TPC28T 2 +3VSUS 1KOhm @ R8127 80 30,43,57,58 SUSB#_PWR R8124 JP8113 2 SGL_JUMP 1KOhm 30 T8102 TPC28T VSUS_ON_PWR D8107 BAT54CW R8128 @ 95.3KOhm FB=1.24V R8123 CPU_VRON T8101 TPC28T R1.3,item L17 R8125 @ 845KOHM GND EN LEAA ADJ G922T11U @ @ 1 JP8108 1MM_OPEN_5MIL 1KOhm Imax=10mA OUT 3MM_OPEN_5MIL @ SGL_JUMP JP8109 1 IN JP8112 BAT54SW R1.2 C8119 1UF/25V 0.1UF/25V c0603 1 SGL_JUMP JP8111 @ D8105 R8121 100KOhm +3VAO +0.95VSUS BAT54SW 2 R8120 174KOhm AC_BAT_SYS R1.1 +5VO 2008.10.16 OCP>7A +12VSUS JP8110 1 +12VSUS 6A R1.2 +3VAO U8103 R1.2 R8116 39KOHM 1% 1 R1.1 C8124 @ 0.1UF/25V C 0.1UF/25V Vref=1.2V B +3VSUS R1.3 PWR B1 R8122 C8121 100PF/50V @ P M U J N E P O R1.2 RT9043-GB +5VAO D8103 C8117 FOR POWER TEST +3VAO VIN VOUT GND EN FB 3MM_OPEN_5MIL JP8105 R1.2 R1.2 U8102 2 1 C8128 1000PF/50V GND_17020 GND_17020 240mil JP8104 R8111 2.2Ohm 2 40mil GND_17020 +5VA 2 C8114 10UF/25V 240mil R8115 1% 200KOhm GND_17020 C8120 1UF/10V C8107 10UF/25V R8113 C8116 1UF/10V D JP8107 +3VAO GND6 GND5 GND4 GND3 + R1.2 0Ohm 37 36 35 34 1MM_OPEN_5MIL +5VAO R1.2 R8108 1% 200KOhm GND_17020 17020_DL2 +5VA 2 0402 SL8104 17020_DL1 17020_BST2 1 +5VAO GND_17020 U8101B RT8206AGQW JP8106 C 17020_SECFB 40mil Q8104 IRF8707PBF 2 0Ohm R1.2 40mil R8110 217020_BST1 + C8108 0.1UF/25V @ @ +3VO L8102 3.8UH Irat=6A GND_17020 C8112 0.1UF/25V R8109 AC_BAT_SYS @ CE8106 27UF/25V SL8102 0402 1 NC2 LDO VIN NC1 ENLDO VCC TON REF C8111 0.1UF/25V 17 18 19 20 21 22 23 24 2 BOOT1 LGATE1 PVCC SECFB GND1 PGND LGATE2 BOOT2 G S D R8107 1% 200KOhm @ S R1.2 R1.3 PWR L R1.1 40mil GND_17020 GND_17020 17020_REFIN2 17020_ILIM2 17020_OUT2 17020_REF SUS_PWRGD ENBL 17020_DH2 17020_LX2 33 32 31 30 29 28 27 26 25 GND2 BYP FB2 VOUT1 ILIM2 U8101A FB1 RT8206AGQW VOUT2 ILIM1 SKIP# PGOOD1 PGOOD2 EN1 EN2 UGATE1 UGATE2 PHASE1 PHASE2 G Q8102 IRF8707PBF G 1 C8110 10UF/6.3V 17020_FB1 17020_ILIM1 SUS_PWRGD ENBL 17020_DH1 17020_LX1 Q8103 IRF8707PBF C8109 0.1UF/16V D @ 10 11 12 13 14 15 16 40mil S 1 3MM_OPEN_5MIL OCP>7A R1.2 2 + +5VSUS 240mil JP8103 GND_17020 GND_17020 R1.2 +5VO L8101 3.8UH Irat=6A CE8101 150UF/6.3V ESR=19mOhm/Ir=2780mA R1.1 240mil GND_17020 GND_17020 40mil +5VO 120mil S Q8101 IRF8707PBF G 17020_IN 17020_RTC 17020_ONLDO 17020_VCC 17020_TON 17020_REF 1 C8106 4.7UF/6.3V 2 R8106 150KOhm 1% C8115 10UF/25V C8104 10UF/25V C8105 0.1UF/25V D 2 C8103 0.1UF/25V @ CE8103 27UF/25V @ + 22,30,58 D CE8104 27UF/25V @ + SL8103 +5VAO D 6A SUS_PWRGD AC_BAT_SYS CE8105 27UF/25V GND_17020 120mil J8102 SHORT_PIN GND_17020 R1.1 +5VAO 0402 R1.3 PWR L C8101 1UF/10V 1 0402 SL8105 R8103 390KOhm 10Ohm C8102 1UF/10V + R1.2 ENBL C8127 1000PF/50V @ R1.2 R1.1 GND_17020 A A Title : POWER_SYSTEM Engineer: ASUSTeK COMPUTER INC NB Size Date: Kenny Chu Project Name Rev M52J C Sheet Friday, July 10, 2009 2.00 81 of 99 AC_BAT_SYS 1 CE8209 27UF/25V CE8208 27UF/25V C8206 10UF/25V 2 +3VSUS JP8201 51117_OUT_SENSOR + VTTVID1 = Low , 1.10V VTTVID1 = High , 1.05V @ Iocp=(Rtrip*10uA)/Rds Vout=0.75*(1+Ra/Rb) 2N7002ET1G S C Q8209R1.31 PMBS3904 B PWR B E 2 H_VTTVID1 40mil + (18A) (+1.05V) OCP>20A R1.1 C G +VTT_CPU Rtrip=R8202 D 11 VTTVID1 = Low , 1.10V VTTVID1 = High , 1.05V Q8210 C R8227 10KOhm 51117_DRVL 2 Ra R8206 30KOHM 1% R8221 100KOhm R8226 180KOhm R8229 100KOhm @ 1 Rb C8207 10UF/6.3V c0805_h57 ESR=15mOhm/Ir=2.7A 220UF/2V CE8204 2008.10.17 ESR=15mOhm/Ir=2.7A 220UF/2V CE8207 Q8203 RJK0349DPA-01 1 2008.07.22 3MM_OPEN_5MIL VFB=0.75V R8208 1% 12KOhm 240mil SHORT_PIN G 51117_PGOOD JP8202 1.0UH @ S 0402 G R1.31 PWR B S 58 +VTT_CPU_PWRGD 51117_VFB R1.2 1 3MM_OPEN_5MIL R8202 7.5KOHM TPS51117RGYR SL8201 D R1.2 40mil 40mil 51117_DRVH 51117_LL 51117_TRIP +5VSUS C8201 1UF/10V JP8203 +VTT_CPU_VO L8201 D D R1.4 PWR L +5VSUS +VTT_CPU_VO 51117_V5FILT R8203 300Ohm 15 14 13 12 11 10 GND2 EN_PSV VBST TON DRVH VOUT LL V5FILT TRIP VFB V5DRV PGOOD DRVL GND1 PGND @ @ + 2 U8201 Q8204B UM6K1N 70,81,83,91 SUSB#_PWR R8207 0Ohm C8203 r0603_h24 0.1UF/25V 51117_VBST 2CP S 51117_LL D R8209 100KOhm G Q8204A UM6K1N +3VO 51117_TON C8204 0.1UF/25V Q8201 IRF8707PBF 51117_EN R8201 39KOhm 0Ohm Q8202 RJK0349DPA-01 R8212 @ + 2 0Ohm @ 1 R8211 R8204 249KOhm D 0Ohm 51117_EN_R C8205 10UF/25V Freq=300KHZ C8202 1UF/10V R8210 R1.3 PWR L R1.1 120mil D8201 BAT54CW 58,70 SYSTEM_PWRGD R1.31 PWR B R1.2 R1.1 R8228 100KOhm @ R1.2 120mil D8252 BAT54CW AC_BAT_SYS VFB=0.75V R8256 30KOHM 1% Rb C8256 10UF/25V 40mil R1.3 PWR B2 R8258 1% 12KOhm 2 +1.05VS (2.44A) B 1 2 OCP>9A +VTT_PCH (5.7A) (+1.05V) R1.4 PWR L C8257 10UF/6.3V @ + + 3MM_OPEN_5MIL CE8251 100UF/2.5V 1 51117_DRVL_1 2 51117_PGOOD_1 JP8253 1.5UH CE8252 560UF/2.5V ESR=10mOhm/Ir=3900mA 2 0402 C8252 1UF/10V 58 +1.05VS_PWRGD 51117_VFB_1 S SL8202 +5VSUS G TPS51117RGYR 3MM_OPEN_5MIL 240mil 1 R8251 7.5KOhm +1.05VSO L8251 D R1.2 2008.10.17 40mil 40mil 51117_DRVH_1 51117_LL_1 51117_TRIP_1 2 C8251 1UF/10V 15 14 13 12 11 10 2 GND2 EN_PSV VBST TON DRVH VOUT LL V5FILT TRIP VFB V5DRV PGOOD DRVL GND1 PGND SHORT_PIN 1 +5VSUS +1.05VSO 51117_V5FILT_1 R1.3 PWR L R8253 300Ohm JP8252 JP8251 Q8253B UM6K1N U8251 JP8254 3MM_OPEN_5MIL R1.31 PWR B @ R8261 2.2Ohm Q8253A UM6K1N R8257 0Ohm C8253 r0603_h24 0.1UF/25V 51117_VBST_1 2CP_1 Q8251 IRF8707PBF 51117_LL_1 C8254 0.1UF/25V R8264 100KOhm R1.3 PWR L 0Ohm 0Ohm 51117_TON_1 R8263 @ 1 R8262 51117_EN_1 R8252 330KOHM Q8252 IRF8707PBF S SUSB#_PWR G 81 VSUS_ON_PWR R8259 @ 0Ohm +3VO R1.3 PWR L D B R8254 249KOhm 0Ohm 51117_EN1_R R8260 51117_EN1_R_ON C8255 10UF/25V Freq=300KHZ C8258 1000PF/50V R1.1 T8202 TPC28T SYSTEM_PWRGD SUSB#_PWR T8203 TPC28T +VTT_CPU_PWRGD T8204 TPC28T H_VTTVID1 T8205 TPC28T +VTT_CPU T8206 TPC28T +VTT_PCH T8207 TPC28T T8208 TPC28T @ R1.1 R1.2 51117_OUT_SENSOR_1 T8201 TPC28T Ra +1.05VS +1.05VS_PWRGD Rtrip=R8206 Iocp=(Rtrip*10uA)/Rds Vout=0.75*(1+Ra/Rb) A A PW_I/O_VTT_CPU&VTT_PCH Title : Engineer: Kenny Chu ASUSTeK COMPUTER INC NB Size Project Name Rev M52J C Date: 2.00 Sheet Friday, July 10, 2009 82 of 99 M_VREF DDR3 60mil * VREF = 0.75V+-1% R2.00,item L17 +1.5VO = VREF * ( R8230 + R8201) / R8301 =1.5V JP8303 1 2 C8312 10UF/25V C8311 10UF/25V 240mil L8300 1 Q8302 IRF8707PBF R1.2 R1.3 PWR L + 2.5UH 1 2 240mil +1.5V (5A) OCP>7A C8304 10UF/6.3V 51116_LL 51116_DRVL 2 JP8301 3MM_OPEN_5MIL CE8305 560UF/2.5V ESR=10mOhm/Ir=3900mA 1 DEM VTTREF MODE GND1 VTTSNS VTTGND C8310 10UF/6.3V C8306 10UF/6.3V +5VSUS C8305 10UF/6.3V Fsw=400KHz 1 JP8302 3MM_OPEN_5MIL @ R1.1 +5VSUS R8304 11.8KOHM GND_51116 58 DDR_PWRGD 26 27 28 29 GND3 GND4 GND5 GND6 C8300 4.7UF/6.3V R1.2 U8301B 1 R1.3 PWR L +5VSUS R8303 5.1OHM R1.31 PWR B C8309 0.1UF/16V R8306 100KOhm D +1.5VO S @ AC_BAT_SYS @ + C8302 0.1UF/25V G GND_51116 AC_BAT_SYS R8307 750KOhm R8301 30KOHM GND_51116 81,91 SUSC#_PWR D8302 BAT54CW R1.2 51116_VDDQSET R1.3 PWR L D R1.31 PWR B C8307 0.1UF/16V R8305 100KOhm2 70,81,82,91 SUSB#_PWR 51116_DRVH R8302 0Ohm 51116_VBST 25 24 23 22 21 20 19 PGOOD VDD VDDP CS NC2 PGND 51116_S3 51116_S5 GND2 VTT VLDOIN U8301A RT8207GQW BOOT UGATE PHASE LGATE NC1 VDDQ FB S3 S5 TON 13 14 15 151116_CS16 17 18 R8330 30KOHM C8308 0.1UF/16V 10 11 12 1A S G FB:0.75V Q8301 IRF8707PBF D D8303 BAT54CW R1.2 +0.75VS 120mil @ GND_51116 GND_51116 51116_VDDQSNS D 60mil JP8300 SHORT_PIN 1MM_OPEN_5MIL CE8308 27UF/25V 60mil +0.75VO +1.05VO: ROCSET = R8304 ;R8304=11.8KOhm ; OCP>7A C8303 2.2UF/10V JS8303 RT8207GQW GND_51116 SHORT_PIN GND_51116 GND_51116 C C R1.3 PWR L Vout=0.8*(1+Ra/Rb) Rb R8366 3 RT8015APQW 100mil R1.31 PWR B R8364 1% C8362 30KOHM 1000PF/50V 8015_COMP1 2CM 8015_FB 8015_VDD 60mil 1 C8364 47PF/50V 2 11 10 GND2 COMP FB VDD PVDD2 PVDD1 SHDN/RT GND1 LX1 LX2 PGND 15KOhm 1% +1.8VO_SENSE 2 60mil +3VSUS JP8361 C8365 3MM_OPEN_5MIL 10UF/6.3V c0603 R1.4 PWR L 1V8_EN 11 Q8361 2N7002ET1G L8361 2.2UH Irat=8.3A 100mil T8301 TPC28T +1.8VS T8302 TPC28T +1.5V Imax=2A T8303 TPC28T M_VREF T8304 TPC28T +0.75VS T8305 TPC28T T8306 TPC28T JP8362 100mil 2 B +1.8VO C8363 10UF/6.3V c0603 1 C8361 0.047UF/16V c0603 S 2 G R8361 330KOHM 8015_LX D 1 D8361 BAT54CW SUSB#_PWR 8015_SHDN 31V8_EN# U8361 R1.31 PWR B Freq=1MHZ R8362 330KOHM Ra R8365 12KOhm 1% 8015_VDD SHORT_PIN J8361 R8363 1MOhm 1 2 3MM_OPEN_5MIL C8366 10UF/6.3V c0603 100mil +1.8VS B DDR_PWRGD 8015_VDD A A Title : POWER_I/O_DDR & VTT Engineer: Kenny Chu ASUSTeK COMPUTER INC NB Size Project Name Rev M52J C Date: 2.00 Sheet Friday, July 10, 2009 83 of 99 +3VM R1.3,item L17 R1.3,item L17 D D C C B B A A Title+3VM : & +3VS_TVDAC Engineer: ASUSTeK COMPUTER INC NB3 Size C Date: Kenny Chu Project Name Rev M52J 2.00 Sheet Wednesday, July 08, 2009 84 of 99 D D C C B B A A Title : Engineer: Kenny Chu ASUSTeK COMPUTER INC NB Size Project Name Rev M52J C Date: 2.00 Sheet Tuesday, July 07, 2009 86 of 99 R1.2 1 R2.0 PWR L EMI CHG_-INE3_C 2 BATSEL_1 T8807 TPC28T CHG_VREF T8811 TPC28T T8812 TPC28T T8810 TPC28T 1 T8809 TPC28T CHG_EN T8813 TPC28T T8815 TPC28T T8816 TPC28T T8817 TPC28T 1 40mil JP8808 1 40mil AC_BAT_SYS T8814 TPC28T AC_BAT_SYS_INV BAT B SHORT_PIN Q8808A UM6K1N BATSEL_0 30 BATSEL_1 30 T8821 TPC28T T8820 TPC28T T8822 TPC28T AC_BAT_SYS T8825 TPC28T SGND_CHG CLOSE TO VIN(PIN 24) T8823 TPC28T T8827 TPC28T T8824 TPC28T T8826 TPC28T Fsw=515KHz T8818 TPC28T SGND_CHG Q8808B UM6K1N T8819 TPC28T CELLS_SEL AC_BAT_SYS_INV to Inverter connect, Power trace =60mil(min) C8811 0.1UF/25V c0603 30 CHG_EN C8813 0.1UF/10V c0402 2 R8811 33KOhm 1% 2 C8812 0.1UF/10V c0402 A/D_DOCK_IN 1 R8812 10KOhm 0.1% BATSEL_0 T8806 TPC28T CHG_CELLS RN8802D 100KOHM JP8805 @ SHORT_PIN 1 ER_change GND3 GND4 GND5 GND6 T8805 TPC28T T8808 TPC28T CHG_ADJ3 R8813 20KOhm 0.1% T8804 TPC28T CHG_CSIN CHG_BATT 0.1% U8801B AC_IN_OC# T8802 TPC28T 1 C8808 10UF/25V c1206_h75 C8805 10UF/25V c1206_h75 2 CHG_CSIP 1 JP8802 SHORT_PIN C8827 1500PF/50V R2.0 PWR L 0402 JP8807 SHORT_PIN 2 2 RN8802C 100KOHM C8809 10UF/25V c1206_h75 2 S SL8802 SGND_CHG CHG_ENBLE# C8804 10UF/25V c1206_h75 G BAT 1 40mil CHG_VREF C8818 1UF/10V c0402 R8828 2.2Ohm D 20m OHM 1% 1 VSET_EC Q8813 IRF8707PBF 160mil R8802 BAT_RSENS 1 R8814 13.7KOhm Charge Voltage ADJ L8802 6.8UH 1 C JP8806 SHORT_PIN R8815 20KOhm 1% R1.3 PWR B3 CHG_BATT C8814 1000PF/16V c0402 CHG_COMP3_C @ S 40mil CHG_COMP3 C8815 0.01UF/16V c0402 SGND_CHG G 40mil @ AC_BAT_SYS R8805 @ 0Ohm JP8801 SHORT_PIN 2 CHG_OUTC3 R1.3 PWR L D CHG_CB CHG_HG CHG_LX CHG_VB CHG_LG 2 33 32 31 30 29 28 27 26 25 GND2 CTL2 CB OUT1 LX VB OUT2 PGND CELLS BATT ADJ3 CS RT VREF GND1 CTL1 VIN R8824 1% 10KOhm U8801A MB39A132 Q8803 IRF8707PBF R8829 0Ohm 17 18 19 20 21 22 23 24 C8817 2200PF/50V c0402 C8820 0.1UF/25V c0402 -INE1 OUTC1 OUTC2 +INC2 -INC2 ADJ2 COMP2 COMP3 C8802 0.1UF/25V c0603 70Ohm /100Mhz R8804 @ 0Ohm CHG_ISET 10 11 12 13 14 15 16 D8801 BAT54CW CHG_CSIP CHG_CSIN 1 SGND_CHG CHG_CS CHG_RT SGND_CHG SGND_CHG T8801 TPC28T C8825 0.1UF/25V CHG_-INE3_R CP_BAT COMP1 ADJ1 -INE3 ACOK ACIN +INC1 -INC1 VCC C8819 0.01UF/16V c0402 CHG_COMP2 MB39A132 2 C8816 120PF/50V c0402 CHG_COMP1 R8820 1KOhm 1% 2 R8818 10KOhm 1% C8807 10UF/25V c1206_h75 JP8804 2 2 CHG_CSSP CHG_CSSN R8816 1KOhm 1% L8803 1 R8826 20KOhm 1% R8819 16.9KOhm 1% 34 35 36 37 C8821 @ 0.01UF/16V c0402 SGND_CHG CHG_-INE3 1CHG_-INE1 B SHORT_PIN 0402 4 C8822 @ 0.01UF/16V c0402 160mil CHG_COMP1_R 65W:R8822=42.2Kohm 90W:R8822=24.9Kohm 30 1 SGND_CHG ADP>=17.5V R8823 10KOhm 1% SGND_CHG CHG_TOTALPWR R8822 24.9KOhm 1% ISET_EC D C8810 0.1UF/25V c0603 CHG_ACIN SGND_CHG 30 360mil R8837 100KOhm CHG_ACIN_OK# Charge Current ADJ AC_BAT_SYS R8827 130KOhm 1% Q8812B UM6K1N RN8801B 100KOHM C 0402 SL8803 5CHG_ACIN_OK# CHG_VREF SEL_EN 2 RN8801A 100KOHM A/D_DOCK_IN Q8802 FDS4435BZ SL8801 Q8809B UM6K1N Total Power ADJ R1.3 PWR B3 CHG_VCC 2CHG_GATE_B 2ACIN_OK_EN RN8801C 100KOHM Q8812A UM6K1N D RN8801D 100KOHM Q8809A UM6K1N AC_BAT_SYS 2 R8803 200KOhm 1% RN8802A 100KOHM CHG_GATE_A 30,47 AC_IN_OC# JP8803 A/D_DOCK_IN D RN8802B 100KOHM SHORT_PIN R1.4 PWR L EMI 360mil G CHG_SW_GATE C8806 0.1UF/25V c0402 D G +3VAO S S A/D_DOCK_IN R8801 20m OHM 1% 200mil CHG_PATH_19V C8824 0.1UF/25V Q8801 FDS4435BZ C8823 0.1UF/25V R1.3 PWR B3 200mil SGND_CHG T8832 TPC28T T8830 TPC28T T8831 TPC28T T8828 TPC28T 1 T8829 TPC28T Battery Cells R1.3 PWR L Power Limit 2008.10.17 BATSEL_1 TPC28T T8803 +5VSUS PWRLIMIT# CELLS L H CELLS H L C8829 0.1UF/25V CELLS L L CELLS C8831 S Charger IC and EC Code correlation sheet： ： Charger MAX8725 => EC CODE： ： 200 Charger MAX17015 => EC CODE： ： 201 Charger MB39A132 => EC CODE： ： 202 Q8819 2N7002ET1G Title : POWER_CHARGER_202 ASUSTeK COMPUTER INC NB3 Size Date: Engineer: Kenny Chu Project Nam e Rev M52J Cus tom A R1.31 PWR B C8830 TOTAL COUNT:66 PCS 11 G R8858 100KOhm D 47UF/6.3V VLMV321IDBVR 3,30 1 R8857 24.9KOhm 1% CHG_PWRLIMIT - 2 U8802 V+ + CHG_REFIN 2.37V C8828 0.1UF/25V 0.1UF/25V CHG_-INE1 1SS355 D8808 1 R8856 10KOhm 1% A CELLS H +3VSUS BATSEL_0 H Friday, July 10, 2009 2.00 Sheet 88 of 99 R1.2 D D C C B B A A Title : POWER_DETECT Engineer: ASUSTeK COMPUTER INC NB3 Size C Date: Kenny Chu Project Name Rev M52J 2.00 Sheet Tuesday, July 07, 2009 90 of 99 SUSB#_PWR POWER SUSC#_PWR POWER Q9106 IRF8707PBF D S G 80mil +3V R9106 240KOhm 1% C9108 @ 0.1UF/16V R1.2 R1.31 B C9109 0.033UF/16V D 80mil +3VSUS D R1.3 PWR L 200KOhm 1% C +12V E 47K B +3VS R9108 100KOhm B R1.2 C9105 @ 0.1UF/16V 10K R1.2 47K 81,83 SUSC#_PWR D9102 @ BAT54CW C G R1.2 20mil 200mil 47K 1% 20mil +12VSUS Q9103 IRF8707PBF S D 1 +3VSUS 200KOhm C9110 @ 0.1UF/16V R1.2 200mil 2 C9103 @ 0.1UF/16V C9104 0.033UF/16V E G R9102 +5V R9107 C9111 0.033UF/16V +1.5VS G 80mil +1.5V 160mil 160mil Q9102 IRF8707PBF D S Q9107 IRF8707PBF D S 80mil +5VSUS Q9108 UMC4N C C R9103 1% 270KOhm 200mil R1.31 B C9112 0.033UF/16V Q9104 IRF8707PBF D S +5VS 240KOhm 1% C9106 @ 0.1UF/16V R1.3 PWR L R1.2 C9107 0.033UF/16V R9104 1 G R1.3 B 200mil +5VSUS B B UMC4N +12VS B 47K E 20mil C 20mil +12VSUS 10K B R9105 100KOhm 47K E C SUSB#_PWR 47K 70,81,82,83 Q9105 R1.4 PWR L T9101 TPC28T +1.5VS T9102 TPC28T +3VS T9103 TPC28T +5VS T9104 TPC28T +12VS T9105 TPC28T +3V T9106 TPC28T +5V T9107 TPC28T +12V 1 1 T9108 T9109 T9110 T9111 T9112 TPC28T TPC28T TPC28T TPC28T TPC28T A A 1 1 T9113 T9114 T9115 T9116 T9117 TPC28T TPC28T TPC28T TPC28T TPC28T Title : POWER_LOAD SWITCH Engineer: Kenny Chu ASUSTeK COMPUTER INC NB Size Project Name Rev M52J C Date: 2.00 Sheet Friday, July 10, 2009 91 of 99 POWER_SIGNAL A/D_DOCK_IN A/D_DOCK_IN 60,88 R1.2 AC_BAT_SYS AC_BAT_SYS 70,80,81,82,83,88 BAT_CON 60 BAT BAT 60,88 +5VA +5VA 28,31,56,81 +5VAO +5VAO 81 +5VO +5VO 81 +5VSUS +5VSUS 27,56,81,82,83,88,91 BAT_CON D D +5V +5V 31,44,45,52,56,57,65,91 +5VS +5VS 27,30,31,36,46,47,48,50,51,56,57,70,80,91 +3VA +3VA 20,30,56,57,60,81 +3VO +3VO 58,81,82 +3VSUS +3VSUS 27,30,33,53,58,81,82,83,88,91 +3V 24,31,33,43,45,53,57,61,64,91 +3V +3VS +3VS 16,17,20,21,22,23,24,25,26,27,28,29,30,31,32,36,40,43,44,45,46,47,48,50,51,53,56,57,58,64,65,66,67,70,80,91 +3VM +3VM 26,27,28 +12VSUS +12V +12VS C +12VSUS 28,81,91 +12V 91 +12VS 28,45,46,91 +1.8VO +1.8VO 83 +1.8VS +1.8VS 6,26,57,70,83 +1.5VO +1.5VO 83 +1.5V +1.5V 3,6,16,17,57,83,91 +1.5VS +1.5VS 26,29,36,43,53,57,64,91 +0.75VS +0.75VS 16,17,57,83 +1.05VSO +1.05VS +VTT_PCH +VTT_CPU_VO +VTT_CPU +VCORE C 2008-08-27,Chester modify +1.05VSO 82 +1.05VS 27,82 R1.3 PWR L +VTT_PCH 26,57,80,82 +VTT_CPU_VO 82 +VTT_CPU 3,6,7,25,26,27,57,82 +VCORE 6,57,80 R1.2 2008-10-21,Chester modify B B A A Title : POWER_SIGNAL Engineer: ASUSTeK COMPUTER INC NB3 Size C Date: Kenny Chu Project Name Rev M52J 2.00 Sheet Friday, July 10, 2009 93 of 99 M52J SUSC#_PWR IRF8707 +3V (1.5A) (1.5A) IRF8707 +3VS (5A) IRF8707 +3VM (1.3A) (1.3A) APL5913 +1.8VS (1.0A) (1.0A) IRF8707 +5V (1.5A) (1.5A) IRF8707 +5VS (4.5A) (4.5A) +3VA (0.05A) (0.05A) AC_BAT_SYS +3VO SUSB#_PWR (5A) SLP_M_PWR D D SUSB#_PWR RT8206A +5VO SUSC#_PWR VSUS_ON SUSB#_PWR FORCE_OFF# +5VAO +5VA SIP21108DT +3VAO SUS_PWRGD SUSB#_PWR C TPS51117 +5VSUS +VTT_CPU_VO (18A) (18A) C +VTT_CPU_PWRGD +1.05VO SLP_LAN#_PWR +VTT_CPU +1.05VM_LAN SUSB#_PWR SI4634 +VTT_PCH TPS51117 SLP_M#_PWR +5VSUS IRF8707 +1.05VM (2.5A) +1.05VM_LAN_PWRGD +1.5VO SUSC#_PWR SUSB#_PWR TPS5116 +5VSUS IRF8707 +0.75VO B SUSB#_PWR (5A) (5A) (2.5A) +1.5V (8A) (8A) +1.5VS (2.6A) (2.6A) +0.75VS (1A) (1A) B DDR_PWRGD +5VS (54A) +VCORE MAX17034 (54A) CPU_VRON_PWR VR_VID0~VR_VID6, H_DPRSTP#, PM_DPRSLPVR,PM_PSI#, VCCSENSE,VSSSENSE, VRM_PWRGD, CLK_EN#, I_MON A A Title : Engineer: ASUSTeK COMPUTER INC NB3 Size Cus tom Rev M52J 2.00 Date: Tues day, July 07, 2009 Chester Project Nam e Sheet 94 of 99 [M52J] R1.0 [ BOM modify - EE ] (Release on 2008/09/23) B1: P05: DNI R0538 for MoW41 Intel's recommand SR1 Gerber out revision B2: P20: DNI R2029 to disable Flash descriptor override B3: P31: Change R3101 from 10K ohm to ohm, DNI C3105 for EGCLK signal quality [M52J] R1.0 => R1.1 (Release on 2008/10/16) B4: P42: Change R3101 from 10K ohm to 100L ohm for +12VSUS low rating [ Layout Changed - EE ] D L1 For 1-1 1-2 1-3 1-4 ME request: Change J6401 from 12G030000522 to Change J4201 from 12G340003601 to Change H6401, H6402, H6403, H6404 Change H5303, H5304, H7003, H7004 12G030000525 12G340003605 from 13GNHC10M020-1 to 13G021043011 from 13GNHC10M020-1 to 13G021036001 B5: P60: According to "EOS of Battery SMBus" report: P60: Change R6001,R6002,R6003 from ohm to 330 ohm P60: Change C6006,C6007,C6008 from 47PF to 33PF B6: P32: DNI R3205 for test purpose D B7: P32: DNI SW3201,R3202 for not support L2 P18: Change M2 circuit for Intel requet B8: P66,51,21: DNI JMB360 circuit for ES1 sample SATA OK L3 Re-define J4501 circuit for cost down 3-1 P45: Re-define J4501 pin6,pin30~40,delete J4502 3-2 P36: Delete C3639 (MONO_OUT) Modify circuit for Internal MIC 3-3 P38: Delete all items in this page for spec change L4 For SPI 4-1.P28: P20: 4-2.P30: flash circuit: Change circuit for PCH SPI flash Change R2015 pull-up from +3VM to +3VM_SPI Change circuit for EC SPI flash L5 To prevent device damage if power not ready: 5-1.P20,P30: Add J2001,J3001 to isolate +3VA 5-2.P20,P21,P22,P24,P25,P27: Modify +3VSUS to +3VSUS_ORG P27: Add J2703,J3001 to isolate +3VSUS 5-3.P27: Modify +5VSUS to +5VSUS_ORG,add J2704 to isolate L6 For 6-1: 6-2: 6-3: decoupling: Change C2903 from net +3VS_VDDPCIEX to +VDDIO_42 Change C2904 from net +3VS_VDDPCIEX to +VDDIO_28 Add C2927 to +VTT_CPU L7 P29: Reserve net +VTT_CPU and add +3VS for frequency 133MHz L8 P03,P29: Delete colay net for PCH buffer mode clock is workable Net: CLK_CPU_BCLK_ICS,CLK_CPU_BCLK_ICS# B9: P33: Mount D3301,D3302 for ESD protect as default setting [ BOM modify - PWR ] PB1: P80: Adjust loadline change R8021 from 3.92KOhm to 3.65KOhm PB2: P80: Reduce transient undershoot change R8037,R8060 from 2KOhm to 2.49KOhm change R8035,R8054 from 1.5KOhm to 2.21KOhm PB3: P81: +3VO from FB mode to fix mode Mount R8133 ,un-mount R8134,change R8111 from 20K Ohm to Ohm PB4: P82: Change L8201 from 2.2UF to 1.5UF ,un-mount CE8204 for add FB voltage Change L8251 from 2.5UF to 1.5UF ,change CE8252 from 100UF to 220UF for reduce transient pulse for reduce transient pulse PB5: P91: Change C9102 from 0.033UF to 0.1UF PB6: P91: Change R9109 from 200K to 100K,adjust +1.05VM rising L9 For test: 9-1 P22: Add R2265,R2266@,R2267 for test 9-1 P22: Add R2265,R2266@,R2267 for test PB7: P92: Change R9205 from 100K to 10K,adjust SYSTEM_PWRGD rising PB8: P80,P81,P82,P83,P86: Change C8001,C8003,C8006,C8009,C8110,C8113,C from 100K to 10K,adjust SYSTEM_PWRGD rising L10 P03,P30: Add power limit circuit for power request L11 P91: Add D9101,D9102 for MOS close quickly C C L12 P03: Add R0366,R0367 to disable FDI for discrete GFX L13 P30,P31: Reserved circuit for testing U3101 removed L14 P31: Exchange D3105 pin 4,5 net for EMI request L15 P22: For S0-to-G3,S5-to-G3 solution L16 P48: Modify circuit for design IP change L17 P30: Delete BAT_LEARN function for power request cost down [ Layout Changed - PWR ] L1 For reduce noise add inupt CAP CE8006,CE8007,CE8800 L2 P80 change pull high power Follow intel common schematic from +VTT_CPU_VO to +VTT_PCH L3 For +12VSUS test 3-1 P80: bump power from +5VSUS to +5VO 3-2 P80: Add JP8108 JP8109 L4 To enhance charger bump energy add C8129,D8108,D8109 L5 Change +1.05VM_LAN enable from SLP_LAN#_PWR to VSUS_ON_PWR for EE request L6 For enable frequency test Add R8210,R8211,R8212,R8259,R8260,R8264,R8262,R8263,Q8253A,Q8253B,R8405 L7 For test add JP860,JP8606 L8 P88 Change D8807 PIN2 connect D8805 PIN2 to D8805 PIN1 for solve MAX17015 IC bug B L9 P88: Add power limit circuit B L10 P91: Add D9101,D9102,R9117 for EE request L11 P92 Change protect circuit to original un-cost down version A A Title : Size C Date: System History Engineer: ASUSTeK COMPUTER INC NB Project Name Rev M60J Sheet Thursday, July 02, 2009 95 of 99 D [M52J] R1.1=> R1.2 [M52J] R1.21=> R1.3 [M52J] R1.3=> R1.31 (Release on 2009/01/12) (Release on 2009/04/20) [ Layout Changed - EE ] L1 P29,25: Change clock GEN: ICS9LPR362 >ICS9LRS3197 for corechip (Release on 2009/06/03) B1 Change connector for ME request J4501:12G170010409 >12G170010408 J4801:12G241101928 >12G24110193V L1 P66,51,21: Del JMB360 cirsuit for PCH SATA workable P21,24,40,41,42: Change CB_ from R5C833 to R5U230 L2 P33,34,21,25: Change LAN:HANKSVILLE >AR8131 for corechip L3 P18: Delete M2 solution and modify description B2 Change MOS 2N7002 P/N to 07G005000313 for RD pool Q0301,Q2001,Q2901,Q3302@,Q4301@,Q4402,Q4503,Q4802,Q6102@ L2 For no support AUB,delete or modify related circuit: P03,P06,P21,P22,P23,P26,P45,P46,P47,P48,,P57,P70,P71, L4 P19: Delete VID controller B3 Change U2801,U2802 for vendor EOL 05G00160F010 >05G00160G010 L3 Change audio circuit from ALC663 to ALC269 L5 P30: Fix error: TP_DAT,TP_CLK pull up +3VA_EC >+5VS L4 For one phase bug fix:R8047: >10K, R8041.2 >R8047.1, R0616: 10K >0ohm L6 P24,53,P64: For PCH SKU compatible: TV_Turner: port >port4 WLAN: port >port8 L5 Layout modify for DG,Mow,EDS: P20,P21,P:25,P27,P32 B4 Change EC from 8541 to 8512 DNI C2804,R2848,R2855,R2856,U2803,R2857,R2858,R2859,R2860,R2861,R3002,R3003,R3004,R3005 Mount R2846,R2853,R2854,R2827,R2828,U3003,R3053,R3043,C3019 Change U3003: 05G001405010 >05G00120A010 Change U3001: 06G042025010 >06G042005012 D L7 P20,21,24,25,67 delete PCH XDP L6 Layout modify for new EC 8541 colay: P28,P30 B5 WW22 MOW,Implement M1 & M3 method: mount R1801,R1804 L8 P25 for PCH GPIO define change: L7 Modify EC pin assignment for charger change:P30 B6 WW20 MOW,change R2029 from 100K@ to 1K@ P25 GPIO15,GPIO28 exchange L8 P45: Add BUF_PLT_RST# to BL_EN circuit [M52J] R1.31=> R1.32 L9 P45: reserverd for RF request (Release on 2009/06/05) L9 P53: Fix error for WLAN_ON# L10 P52: Add CE5202 to avoid voltage droop L10 R6741,R6742 move to R2621,R2622 for some project without BRAIDWOOD B1 P28 DNI U2802 for costdown B2 P30 Change EC from 8512 to 8502 for costdown L11 P32: Delete SW3201,R3202 for no support force-off switch L11 P61: D6101 change from RB751V to BAT54C L12 P30,P56: for touch sensor board rev 1.2 Move CAP_ACK#(GPE7) >CAP_ACK_A#(GPI6),add CAP_ACK_B#, delete R5624,delete Q5602@,Q5604@,R5626@,add SL3005,SL3006 [ Layout Changed - PWR ] PL1 P81: SYSTEM PWM change from MAX17020 to pin to pin RT8206A (for IC bug) PL2 P88: Charger IC change from MAX17015 to MB39A132 (for IC bug & EMI) L13 For N10P-GS VGA card: (Layout impedance change) P48:Move D4802 from net HDMI_HPD_CON to HDMI_HPD P48:Add R4809~R4816,Q4802 for HDMI termination PL3 PL4 PL5 PL6 PL7 P88,P60: Change BAT in jump & bead from P88 to P60 P.86: Delete P86 +VGA_CORE P.80: PM_PSI# pull low follow intel schematic P90 Delete battery detect circuit P80 VID0~6, PM_DPRSLPVR, PM_PSI# pull high power from +VTT_PWR Change to +VTT_PCH PL8 P81 System +3VS,+5V voltage change from resister adjust to fix mode PL9 P90 Delete battery detect circuit L14 P24,P30: For PCI_CLK layout guide update L15 P21,P27:Disable Intel LAN P27 Delete R2723,net +1.05VM_LAN L16 Change ESD diode to IP4223 for cost down D3106,D4301,D4503,D4605,D4701,D4702,D4703,D5201,D6501,D6601 L17 For iAMT disable [ EMI request ] ITEM E: C P30,P31,P92 Delete net ME_+VM_PWRGD,D9202,R3070@,R3105,R3108@ P31.Delete U3101(IT8301E) block P30.Delete R3066,R3067,R3068,R3072,net EGAD,EGCS,EGCLK,EGCLK_EC P57 Delete Q5708,R5709,R5716,R5717,Q5710,R5718,R5719,no connect Q5707B P81.Delete net ME_PM_SLP_LAN#,SLP_LAN#_PWR,R8131,JP8117 P81.Delete net ME_SLP_M_EC#,SLP_M#_PWR,R8129,JP8116 P84.Delete +3VM load switch block,ME_+VM_PWRGD block P22.Delete ME_PM_SLP_M# to PM_SUSB#,delete R2254,R2238,Add T2208 P22.Delete net ME_PM_SLP_LAN#,R2254,R2257,add T2207 Connect ME_PWROK_PCH to PM_PWROK_PCH Delete R2272@,R2268,D2204@,R2271 P27 Delete net +1.05VM_ORG_R[1 4],delete R2736,R2727,R2738,R2739 Connect +1.05VS to +1.05VM_ORG Connect +3VS to +3VM via JP2705 1.P88 BAT : L8801, L8803 要要 for EMI >L6001,L6002 2.P29 CLK Gen : R2935 , R2936 改 Bead 120 ohm for EMI >L2901,L2902 3.P36 SPDIF1,2_OUT : R6502 , SL3652 改 Bead 120 ohm for EMI >L6501,L3622 4.USB power : R6501 , R4505 , R5201 改 Bead 120 ohm for EMI >L6502,L4504,L5203 5.C4508 要要 for EMI >Mount C4508 6.USB I/O port & CMOS 同同 Run 會會 EMI issue,建建建 USB EHCI define 同時時時時時時時時 >已已已,port4=WiFi/WiMax,port9=Camera 7.LAN : R3306 , R3338 , R3332 , R3337 改改 Bead ; +1.05VM_LAN 要 0.1uF 靠靠 R3341 >L3301, L3303,L3302,L3304,C3314 Note: 1.請請請請請bead是是是是要R3341就就 C3313,C3314是是是是是要是是,要上是是? 8.LVDS : C4506 要要 0.1uF ; LCD_PWM要要 0.1uF >Mount C4506, LCD_PWM預預10PF不要C4514 P36 GND 到 GND_Audio 的 short line 增增增是 (或是或或或或改 short line ) >SL3651,SL3652,SL3653 L18 For EC8541: P28: Delete R2848,R2856,net PM_RSMRST# Add Q2804,Q2805,R2830,R2835,R2836,R2838 P28: Others: please see the description [M52J] R2.00=> R2.01 B1 BOM modify for DG,Mow,EDS: P03,P21,P24,P25 L25 P28 Fix SPI circuit for EC8541 B2 P80 +Vcore output CAP from Panasonic 470Uf/2V 4.5m Ohm change to Panasonic 330/2V 6m Ohm B3 P80 Change Q8007,Q8001,Q8005,Q8000 from SI4686BDY to SI7170DP Change Q8002,Q8004 from SI4634BDY to SI7686DP P28 ChangeJ2801.1 power for dediprog flash P47 ChangeR4701 10K >100K,add R4709 to fix DP hot-plug issue P20 Fix error that HDA_DOCK_EN# can't pull to GND directly P36,P20 Remove PC beep circuit for design IP change P03,06,20,27,30,32,56,60,65:Add test point for factory request P45: Change C4501 0.1uF(0402) >0.22uF(0603) for LCD power timing P37: Change J3701 12G171000049 >12G17100004F to fix ME bug P53: Change J5302 12G030000524 >12G03011052X for EOL Change H5303、H5304 13G021036001 >13GP2360M110-1 to match 12G03011052X L9 P43: Change U4301 06G030053010 >06G030091110 for design IP L10 For EMI request: Add C2617,C2618,C2736,C2748,C2749,C4509,C4510,C4519@,C5101,mount C3406 USB_PN0, USB_PN1 建J6501 預預 choke USB_PN2,3,5 預預 ohm L11 For EC request pin assignment: GPB.2 (ME_AC_PRESENT );GPG.0 (ME_SusPwrDnAck);GPI.4 (PCH_TEMP_ALERT#) Change GPF.0 (PCH_SPI_OV) to GPF.7 L12 For Touch seneor default state: Del RN3007,change CAP_ACK_A#,CAP_ACK_B# pull up to +3VS(RN3008) L13 Change C2101@(27pF) to ohm to meet Calpella DG R1.6,Page 369 L14 P29: Colay clock GEN 9LRS3197/9LVS3162 L15 Fix thermal policy: P25 Move & mount R2501,add R2505 P32 Follow designip P50 Use GMT G709 as thermal protection L16 P45 Reserve soft-start circuit to prevent LCD inrush current L17 P65 Add C6514,C6515 for EMI request(prevent TV noise) L17 P45,P83: change JP4599 for lead part L21 P7,P37 change XDP from 60pin to 24pin SFF L24 P45 Delete F4502 for costdown B1 P80 Change CE8806,CE8807 from mount to un-mount L1 L2 L3 L4 L5 L6 L7 L8 L22 P56: prevent touch sensor board leakage Change J5601 net SMB1_CLK >SMB1_CLK_S,SMB1_DAT >SMB1_DAT_S [ BOM modify - EE ] [ BOM modify - PWR ] (Release on 2009/07/02) B1 B2 B3 B4 B5 B6 B7 B8 B9 L19 net connection change.(for possible costdown) PM_PWROK_PCH:D2202.2 >D2202.1 PM_RSMRST#_PCH:D2203.1 >D2202.2 R2275:0ohm >10Kohm L20 P20,30.connect HDA_DOCK_EN# to EC for BIOS request L23 For component kinds down:F5201< F6501,F4801< F4502 B [M52J] R1.32=> R2.00 C P46 Change C4601~C4601 10PF >5PF for CRT signal quality P45 Change J4501:12G170010409 >12G170010408 for footprint not compatible P23 ChangeR2321 from 1Kohm,0.5% >1Kohm,5% for DAC_IREF not used P58 Move page 92 to page 58, rename components P06 Delete unused nets P20,28: Change R2032,R2033,R2837,R2840,R2841 to 33ohm to fix dediprog checksum error issue P52: Change L5203 09G012080023 > for common part P52: Change C6508,C6509 100pF >1000pF for EMI request(prevent TV noise) P24: DNI R2414 for no braidwood (Release on 2009/07/02) B10 P20,P28: For only one SPI ROM: DNI R2834,R2832,C2803,R2828,R2827,R2852,R2850,R2846,R2851,R2823,R2854,R2849,R2853,R2033 B11 P20,P67:remove support of PCH JTAG P20: R2034,R2035,R2036,R2037,R2038,R2039,R2040,R2041 P67: R6702,J6701,R6721,R6722,R6723,R6724 B1 P36 Change ALC269 From A5 to VA6(P/N: 02G611005006) B2 P30 Change U3001 from IT8512E to IT8541E B3 P18 Change Vref solution from M1 to M3 DNI R1801,R1804,Mount R1805,R1806 B4 P67 For no support Braidwood: DNI J6704,R6740, B5 Intel DG update: P03 change R0320 & R0321 B B6.P70 correct name to match page rule: C7709 >C7009 ,C7010,C7011,C7012,C7013,C7014,C7705 T7006,T7007,T7008 B4 P81 Change CE8101,CE8102 from CHEMICON 220UF/6.3V 10m Ohm to CHEMICON 150UF/6.3V 19m Ohm B7.P70 DNI R7022, mount R7023 for VGA timing B5 P82 Change CE8204,CE8207 from Panasonic 330/2V 6m Ohm to Panasonic 220/2V 15m Ohm B8.P50 Change U5002 from G781-1 to G781 for SMBUS addr B6 P82 Change CE8252 from CHEMICON 330UF/4V 10m Ohm to CHEMICON 560UF/2.5V 10m Ohm B9.P21 DNI X2101,C2101,C2102,R2151 for PCH only support BTM mode currently B7 P83 Change CE8305 from CHEMICON 330UF/4V 10m Ohm to CHEMICON 560UF/2.5V 10m Ohm B10 Improve clock ppm: P29: C2907,C2908: 24pF >27pF P40: C4040,C4066: 22pF >27pF B8 P91 Change Q9101 from SI4634DY Rdson=6.7mOhm to IRF8707PBF Rdson=17.5mOhm B9 P91 Change C9101, C9103, C9105, C9106, C9108, C9110, C9122 from mount to un-mount B11 Add R3205 support thermal protection [M52J] R1.2=> R1.21 (Release on 2009/03/12) B1 For EA team signal quality test: P21 Change RX2103,RX2104 from 0ohm to 22ohm P24 Change R2404,R2406 from 22ohm to 33ohm B2 P47 R4708:100K >1K for bug fix(0.3V >3V) A A Title : Size C Date: System History Engineer: ASUSTeK COMPUTER INC NB Project Name Rev M60J Sheet Friday, July 10, 2009 96 of 99 AC-IN Mode M52J Power On Sequence Diagram Rev 0.31 Reset Logic (RC) P.32 19 GFX_VR_ON 15 SUSB_EC# +VGFX_CORE 22 +0.75VS +1.5VS +1.8VS +3VS +5VS +12VS GFX_PWRGD PWROK Logic1 P.92 PWROK Logic2 P.92 CPU_VRON VRM_PWRGD ME_+VM_PWRGD 14 SUSC_EC# ALL_SYSTEM_PWRGD C 23 26 16 24 EC power EC EC PLT_RST# 29 30 28 CPU_PWRGD PCH 15 14 13 19 GFX_VR_ON PWROK Logic3 P.92 H_VTTPWRGD 21 to to to to H_DRAM_PWRGD P.81 10 12 11 12 DRAMPWRGD PCH_PWROK SYS_PWROK SUS_PWRGD +1.5V +3V +5V +12V ME_PWROK LAN_RST# SUSB_EC# SUSC_EC# ME_SLP_M_EC# +3VSUS +5VSUS +12VSUS PM_SUSC# SLP_S4# PM_SUSB# SLP_S3# DRAMPWROK VSUS_ON ME_PM_SLP_M# ME_PM_SLP_LAN# BUF_PLT_RST# P.81 17 27 RSTIN# +3VA_EC MAX17020 ME_AC_PRESENT ME_SusPwrDnAck PM_PWRBTN# PM_RSMRST# ME_PWROK PM_PWROK EC IT8512E (+IT8301E) D H_CPUPWRGD +3VA +5VA AC_BAT_SYS Power On Button VCCPWRGOOD_0 VCCPWRGOOD_1 PWR_SW# EC_RST# D C CPU VTTPWRGOOD 18 SYSTEM_PWRGD +VTT_CPU 20 +VTT_CPU_PWRGD B B 12 ME_PM_SLP_LAN# +1.05VM_LAN 15 SUSB_EC# Delay Logic 13 ME_SLP_M_EC# +1.05VM +VM_OK Logic P.84 +VTT_PCH +3VSUS 12 ME_PM_SLP_LAN# Power On Sequence +3VM IMVP6.5 +VCORE A 25 CLK_PWRGD CLK Gen CK505 30 A Title : POWER SEQUENCE Engineer: James1_ Wu ASUSTeK COMPUTER INC Size C Date: Project Name Rev M60J 2.00 Sheet Thursday, July 02, 2009 98 of 99 AC-IN Mode M52J Power-On Sequence Timing Diagram Rev.0.31 +3VA/+5VA/+3VA_EC (to EC) EC_RST# (EC to power) VSUS_ON +3VSUS/+5VSUS D (pull up to +3VSUS) (PCH to EC) ME_SusPwrDnAck (power to EC) SUS_PWRGD T0=20ms(spec.>=10ms) D T1=1ms) (EC to PCH) 17 ME_PWROK 18 SYSTEM_PWRGD +VTT_CPU B B (CPU to power) 19 GFX_VR_ON T4=1.25ms 20 +VTT_CPU_PWRGD/ 21 H_VTTPWRGD (power to CPU) GFX_VID +VGFX_CORE T5=60us(typ.) 22 GFX_PWRGD (power to EC) 23 ALL_SYSTEM_PWRGD T6=110ms (spec.>=99ms) (EC to power) 24 CPU_VRON T7=10~100us +VCORE 25 CLK_PWRGD (inversion of CLK_EN#) A T8=3~20ms A (power to EC) 26 VRM_PWRGD (EC to PCH) 27 PM_PWROK T9=10ms (PCH to CPU) 28 H_DRAM_PWRGD Title : Power On Timing (PCH to CPU) 29 H_CPUPWRGD Size (PCH to CPU) 30 BUF_PLT_RST# Engineer: C Date: Wenbin Jian Project Name Rev M60J 2.00 Sheet Thursday, July 02, 2009 99 of 99 DC-IN Mode M52J Power-On Sequence Timing Diagram Rev.0.31 +3VA/+5VA/+3VA_EC (to EC) EC_RST# (to EC) PWR_SW# D (falling edge) (EC to power) VSUS_ON +3VSUS/+5VSUS D (pull up to +3VSUS) (PCH to EC) ME_SusPwrDnAck (power to EC) SUS_PWRGD T0=20ms (spec.>=10ms) T1=1ms) (EC to PCH) 17 ME_PWROK 18 SYSTEM_PWRGD +VTT_CPU B B (CPU to power) 19 GFX_VR_ON T4=1.25ms 20 +VTT_CPU_PWRGD/ 21 H_VTTPWRGD (power to CPU) GFX_VID +VGFX_CORE T5=60us(typ.) 22 GFX_PWRGD (power to EC) 23 ALL_SYSTEM_PWRGD T6=110ms (spec.>=99ms) (EC to power) 24 CPU_VRON T7=10~100us +VCORE 25 CLK_PWRGD (inversion of CLK_EN#) A T8=3~20ms A (power to EC) 26 VRM_PWRGD (EC to PCH) 27 PM_PWROK T9=10ms (PCH to CPU) 28 H_DRAM_PWRGD Title : Power On Timing (PCH to CPU) 29 H_CPUPWRGD Size C (PCH to CPU) 30 BUF_PLT_RST# Engineer: Date: Wenbin Jian Project Name Rev M60J 2.00 Thursday, July 02, 2009 Sheet 99 of 99