5 F80S SCHEMATIC Revision R1.1 BLOCK DIAGRAM D Page17 ATI M82-M PCIE 16X Page43~49 RGB Page16 HDMI TMDS Page18 TPM North Bridge SiS 671DX 533/667 Mhz DDR2 SO-DIMM2 Page13 MuTIOL 1G Page40 South Bridge SiS 968 LPC Debug CON Page19 EC ITE8752 ODD SATA HDD Page17 New Card Page29 Page34 KB/TOUCH PAD Page31,38 Mini Card W-LAN Page19 Audio Codec ALC660D Page35 Page27 A Page26 MIC IN Page28 Blue Tooth Page38 B Finger Printer Page38 USB2.0 *3 RealTek RLT8201CL-10/100 Page26 Amp CCD PCIE AZALIA LED Page30 C Page32 Page32 USB PHY SPI ROM PATA Page20~24 Page30 SPK OUT DDR2 SO-DIMM1 Page12 Page6~11 C B D Clock GEN Page6 FSB 800 LVDS CRT ThermalPage5 CPU MEROMPage2,3 LCD MDC Page33 Card Reader AU-6371 4in1 Card Reader Page27 Page27 Page36 A RJ45/RJ11 JACK Page36 Title : Block Diagram ASUSTeK Computer INC Size B WM Chen Rev F80S Date: Friday, February 15, 2008 Engineer: Project Name 1.1 Sheet 1 of 94 6 +VCCP_AGTL+ H_A#[16 3] H_REQ#[4 0] H_A#[35 17] +VCCP H_ADSTB#0 H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_ADSTB#0 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 C H_ADSTB#1 21 21 21 H_A20M# H_FERR# H_IGNNE# 21 21 21 21 H_STPCLK# H_INTR H_NMI H_SMI# +VCCP +VCCP_AGTL+ H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 H_A#32 H_A#33 H_A#34 H_A#35 H_ADSTB#1 H_A20M# H_FERR# H_IGNNE# J4 L5 L4 K5 M3 N2 J1 N3 P5 P2 L2 P4 P1 R1 M1 K3 H2 K2 J3 L1 Y2 U5 R3 W6 U4 Y5 U1 R4 T5 T3 W2 W5 Y4 U2 V4 W3 AA4 AB2 AA3 V1 A6 A5 C4 H_STPCLK# D5 H_INTR C6 H_NMI B4 H_SMI# A3 T215 TPC28T @ 1 T216 TPC28T @ M4 N5 T2 V3 B2 C3 D2 D22 D3 F6 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# A[32]# A[33]# A[34]# A[35]# ADSTB[1]# A20M# FERR# IGNNE# STPCLK# LINT0 LINT1 SMI# RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 RSVD9 RSVD10 SHORT_PIN @ H_D#[0 63] D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# Y22 AB24 V24 V26 V23 T22 U25 U23 Y25 W22 Y23 W24 W25 AA23 AA24 AB25 Y26 AA26 U22 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_DSTBN#2 H_DSTBP#2 H_DINV#2 AE24 AD24 AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21 AC22 AD23 AF22 AC23 AE25 AF24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 AA1 Y1 H_COMP0 R213 H_COMP1 R207 H_COMP2 R216 H_COMP3 R206 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 H_DPRSTP# H_DPSLP# H_DPWR# H_PWRGD H_CPUSLP# +VCCP 4,5,6,10,21,23,37,43,84 +VCCP_AGTL+ 2.5A U201A JP201 T203 D ADS# BNR# BPRI# DEFER# DRDY# DBSY# BR0# H1 E2 G5 H_ADS# H_BNR# H_BPRI# H5 F21 E1 H_DEFER# H_DRDY# H_DBSY# F1 H_BR0# IERR# INIT# D20 B3 H_IERR# H_INIT# LOCK# H4 H_LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# C1 F3 F4 G3 G2 H_CPURST# H_RS#0 H_RS#1 H_RS#2 H_TRDY# HIT# HITM# G6 E4 H_HIT# H_HITM# BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 HBPM1# H_PREQ# H_TCK H_TDI H_TDO H_TMS H_TRST# CPU_DBR# H_ADS# H_BNR# H_BPRI# 6 U201B H_BR0# H_INIT# 21 R203 56Ohm +VCCP_AGTL+ R208 H_LOCK# @ 56Ohm H_CPURST# H_RS#0 H_RS#1 H_RS#2 H_TRDY# H_HIT# H_HITM# T207 1 T208 T209 T214 C202 0.1UF/10V X7R @ 6 6 THERMTRIP# D21 A24 B25 C7 R215 1KOhm 1% H_PROCHOT_S# 31 CPU_THRM_DA CPU_THRM_DC PM_THRMTRIP# BCLK[0] BCLK[1] PM_THRMTRIP# 5,21 CLK_CPU_BCLK CLK_CPU_BCLK# CLK_CPU_BCLK CLK_CPU_BCLK# 2KOhm 1% CLK_CPU_BCLK CLK_CPU_BCLK# 1 H_DSTBN#1 H_DSTBP#1 H_DINV#1 R220 R221 T211 R205 @ A22 A21 6 GND T212 T213 GND T205 T206 GND 4 1KOhm @ 51.1Ohm @ 2 C203 0.1UF/10V @ 1 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 CPU_BSEL0 CPU_BSEL1 CPU_BSEL2 E22 F24 E26 G22 F23 G25 E25 E23 K24 G24 J24 J23 H22 F26 K22 H23 J26 H26 H25 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# N22 K25 P26 R23 L23 M24 L22 M23 P25 P23 P22 T24 R24 L25 T25 N25 L26 M26 N24 GTL_REF C201 0.1UF/10V H CLK H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 +VCCP_AGTL+ T202 TPC28T H_PROCHOT_S# CPU_THRM_DA CPU_THRM_DC H_DSTBN#0 H_DSTBP#0 H_DINV#0 GND THERMAL PROCHOT# THRMDA THRMDC H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 H_DEFER# H_DRDY# H_DBSY# D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# AD26 C23 D25 C24 AF26 AF1 A26 GTLREF TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 B22 B23 C21 BSEL[0] BSEL[1] BSEL[2] D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# MISC BCLK 133 SOCKET478B 533 L L H 166 667 L H H 800 Layout Note: Comp0,2 connect with Z0=27.4 ohm, make trace length shorter than 0.5" Comp1,3 connect with Z0=54.9 ohm, make trace length shorter than 0.5" Comp[3:0] at least 25 mils away from any other toggling signal 27.4 ohm connects with an ~18mil wide trace to comp0 54.9 ohm connect with 5mil-wide to comp1 H_DSTBN#3 H_DSTBP#3 H_DINV#3 C 27.4Ohm 1% 54.9Ohm 1% 27.4Ohm 1% 54.9Ohm 1% GND H_DPRSTP# 21,80 H_DPSLP# 21 H_DPWR# H_CPUSLP# 21 PM_PSI# R219 10OHM 80 T210 TPC28T FSB BSEL2 BSEL1 BSEL0 200 H_DSTBN#2 H_DSTBP#2 H_DINV#2 PM_PSI# SOCKET478B