5 A6F Block DiagramCPU D FAN + SENSOR PAGE CLOCK GEN ICS954310 PAGE D DISCHARGER CIRCUIT YONAH-2M PAGE 36 PAGE 2,3 Power On Sequence FSB 667MHz PAGE 39 DEBUG PORT MCH-M Calistoga 945GM LVDS & INV PAGE 12 CRT & TV OUT PAGE 41 DDR2-667 Dual Channel DDR2 PAGE 6,7,8,9,10,11 C PAGE 14,15,16 SYSTEM PWR C DMI interface PAGE 51 PCIE *1 PAGE 44 SUPER I/O SMSC LN47N217 ICH7-M PCI 33MHz B0:02G010008811 EC IT8510E PAGE 33,34 IDE PAGE 28,29 PAGE 37 PCMCIA PAGE 31 CardBus R5C841 PAGE 17,18,19,20 INSTANT KEY B PAGE 57 10/100/1000LAN RTL8110SBL Azalia PAGE 25 BAT & CHARGER MINI CARD WLAN PAGE 26 LPC 33MHz KEYPAD MATRIX PAGE 37 PAGE 50 B0:02G010009121 PAGE 13 PRINT PORT CPU VCORE SO-DIMM X USB 1394 PAGE 32 PAGE 30 B CARD READER PAGE 32 LED Control PAGE 37 Mini PCI HDD USB 2.0 CON X4 PAGE 27 ISA ROM PAGE 38 PAGE 35 ODD Azalia Codec ALC660 PAGE 27 PAGE 24 Bluetooth PAGE 21,22,23 PAGE 26 MDC Connector A Camera PAGE 34 A PAGE 12 Title : BLOCK DIAGRAM ASUSTeK COMPUTER INC Size Project Name A3 Engineer: Jack WANG Rev A6F 1.1 Date: Monday, March 06, 2006 Sheet 1 of 63 H_A#[16 3] H_REQ#[4 0] H_A#[31 17] T200 STPCLK# LINT0 LINT1 SMI# AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 RSVD[1] RSVD[2] RSVD[3] RSVD[4] RSVD[5] RSVD[6] RSVD[7] RSVD[8] RSVD[9] RSVD[10] B25 B1 F3 F4 G3 G2 H_CPURST# H_RS#0 H_RS#1 H_RS#2 H_TRDY# HIT# HITM# G6 E4 H_HIT# H_HITM# +VCCP_AGTL+ H_LOCK# H_CPURST# H_RS#0 H_RS#1 H_RS#2 H_TRDY# H_HIT# H_HITM# AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 PRDY# PREQ# TCK TDI TDO TMS TRST# CPU_DBR# PROCHOT# THERMDA THERMDC D21 A24 A25 H_PROCHOT_S# CPU_THRM_DA CPU_THRM_DC THERMTRIP# C7 PM_THRMTRIP# BCLK[0] BCLK[1] A22 A21 CLK_CPU_BCLK CLK_CPU_BCLK# RSVD[12] RSVD[A2] T22 A2 CONTROL 17 +VCCP_AGTL+ R202 54.9Ohm / T201 6 H_DSTBN#0 H_DSTBP#0 H_DINV#0 6 +VCCP_AGTL+ R203 R204 R205 R217 R206 R207 T202 56Ohm 56Ohm 56Ohm 56Ohm 56Ohm 56Ohm / / GND +VCCP_AGTL+ T204 TPC28T CPU_THRM_DA CPU_THRM_DC R200 1KOhm 1% PM_THRMTRIP# 4,7,17 6 H_DSTBN#1 H_DSTBP#1 H_DINV#1 RSVD[11] RSVD[13] RSVD[14] RSVD[15] RSVD[16] RSVD[17] RSVD[18] RSVD[19] RSVD[20] CLK_CPU_BCLK CLK_CPU_BCLK# C200 0.1UF/10V N/A R211 2KOhm 1% D2 F6 D3 C1 AF1 D22 C23 C24 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 M24 N25 M26 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# GTL_REF pin17,pin18=LCDCLK(96MHz) or 27M/27M_SS GND1 GND2 GND3 GND4 GND5 GND6 GND7 internal pull high PEREQ3# 32 PEREQ4# 33 Vtt_PwrGd#/PD GND REF1/FSLC/TEST_SEL REF0 GND STP_CPU# 19,50 49.9Ohm r0402 49.9Ohm r0402 C 49.9Ohm r0402 49.9Ohm r0402 49.9Ohm r0402 49.9Ohm r0402 49.9Ohm r0402 49.9Ohm r0402 10KOhm 10KOhm GND GND 56Ohm 56Ohm PREQ#2 0=PCIEX 8/1 Not Controlled B 1=PCIEX 8/1 Controlled CLK_PCIE_ICH 18 CLK_PCIE_ICH# 18 PREQ#3 0=PCIEX 4/2 Not Controlled 2/23/06 1=PCIEX 4/2 Controlled DOT96 R551 DOT96# R552 33Ohm 33Ohm 10KOhm / CLK_UMA_96M CLK_UMA_96M# +3VS_CLK REF1 REF0 PREQ#4 +3VS MCH_CLK_REQ# PEREQ4# R556 0Ohm CLKREQ# 26 R557 10KOhm / R558 2.2KOhm CPU_BSEL2 R559 R560 33Ohm 33Ohm CLK_14_SIO 25 CLK_ICH14 19 10 61 60 0=PCIEX 6/0 Not Controlled 1=PCIEX 6/0 Controlled GND Realtek:Mount R519,Remove R550 R534 0.1UF/10V STP_PCI# 19 R554 R561 49.9Ohm r0402 49.9Ohm r0402 PREQ#1 R553 475Ohm 2 2 2 C523 C522 C521 C517 C519 C520 CLK_MINIPCI_D 38 C518 C512 PCIE7 R531 PCIE#7 R532 49.9Ohm r0402 49.9Ohm r0402 STP_PCI# 62 CLK_LCD_SSCG 33 CLK_LAN_PCI 63 CPU_STOP# VDDA 16 PCI/PCIEX_STOP# 46 PCICLK5 +3VS_VDDREF 30 CLK_CBPCI 56 45 GND 19 CLK_USB48 CPU_BSEL0 CPU_BSEL1 CLK_MINIPCI VDDREF VDD GND B +3VS_VDD48 VDDCPU GND 27PF/50V GND 11 50 +3VS_VDDA 27PF/50V R513 1Ohm VDD48 VDDPCIEX1 VDDPCIEX2 VDDPCIEX3 34 C516 10UF/6.3V 0=PCIEX 7/5/3 Not Controlled 2.2Ohm C514 0.1UF/10V C511 GND VDDPCI2 21 28 42 C510 0.1UF/10V +3VS C515 2 C513 10UF/10V 1 X500 14.318Mhz 1 C VDDPCI1 U500 +3VS_CLK R516 R512 2.2Ohm 2 2 C507 C508 C509 0.1UF/10V 0.1UF/10V 10UF/10V Pin34 is PWRSAVE# 1 1 +3VS_VDDPCI R555 10KOhm / 1=PCIEX 7/5/3 Controlled CLK_EN# 50 A A SELLCD_27#/PCICLK_F1: >pin17,pin18=LCDCLK(96MHz) Internal Pull-Up Resistor PCICLK2/REQ_SEL: >pin40,pin41=PREQ1#,PREQ2# Title : CLOCK GEN Internal Pull-Down Resistor ASUSTeK COMPUTER INC Size ITP_EN/PCICLK_F0: >CPU_ITP pair Custom Engineer: Jack Wang Project Name Rev A6F 1.1 Date: Monday, March 06, 2006 Sheet of 63 H_D#[0 63] H_A#[31 3] +VCCP CLK_MCH_BCLK CLK_MCH_BCLK# H_HIT# H_HITM# H_LOCK# Y1 U1 W1 H_YRCOMP H_YSCOMP H_YSWING H_CLKIN H_CLKIN# A C +VCCP H_BNR# H_BPRI# H_BR0# H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# R606 200Ohm 1% C601 0.1UF/10V R607 221Ohm 1% GND GND H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 2 2 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 D8 G8 B8 F8 A8 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#_0 H_RS#_1 H_RS#_2 B4 E6 D6 H_RS#0 H_RS#1 H_RS#2 H_SLPCPU# H_TRDY# E3 E7 N_CPUSLP# H_TRDY# 0.1UF/10V 10/20mils 2 2 R608 100Ohm 1% GND GND B Signal voltage level = 0.3125*VCCP Trace should be 10 mil wide with 20 mil spacing +VCCP H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 Layout Note: 0.1uF should be placed 100mils or less from GMCH pin C602 2 2 2 H_XSWING H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 R609 221Ohm 1% H_YSWING H_HIT# H_HITM# H_LOCK# 2 H_YRCOMP H_YSCOMP H_YSWING GND R610 100Ohm 1% H_RS#[0 2] C600 0.1UF/10V H_XRCOMP H_XSCOMP H_XSWING GND E1 E2 E4 D3 D4 B3 H_HIT# H_HITM# H_LOCK# H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 K3 T6 AA5 AC5 Charger Disable AC_BAT_SYS C5705 MAX8725_LDO T5712 TPC28T D 11 0.1UF/25V A/D_DOCK_IN Mode pin : Vmode > 2.8V (trie to LDO pin) > Cells 0.8 > Vmode (trie to GND) > Learning mode B 2N7002 G S BATSEL_2P# 0.1UF/25V PC5704 CHG_PDL A/D_DOCK_IN 28 0.1UF/25V C5703 CHG_PDS Vbatt = Cell * { Vref +[ (VCTL- 1.8V) / 9.52 ] } VCTL= 1.588V => Vbatt = 4.2V G C TPC28T T5711 Charge Current Ichg = [0.075V/Rsense(CHG)]*[VICTL/3.6V] Rsense(CHG)=0.025 ohm VICTL= 3V => Ichg = 2.5A VICTL= 1.68V => Ichg = 1.4A C5702 0.1UF/25V Adapter Iin(max) = [0.075V/Rsense(ADin)]*[VCLS/VREF] Rsense(ADin)=0.02 ohm VCLS= 3.685V => Iin(max)=3.27A => Constant Power = 19 * 3.27 = 62.13W =>R5708=20K,R5714=137K PKPRES# R5727 CHG_SRC AC_IN Threshold 2.048Vmax A/D_DOCK_IN > 17.44V active 100KOhm CSSN PKPRES# +5VLCM R5724 100KOhm V- - 1% @ D5705 A/D_SD# @ C5719 @ 0.1UF/25V @ 1SS355 G Q5713 2N7002 D R5720 Q5709 2N7002 11 BAT_LEARN 90.9KOhm @ A S 28 A D R5726 @ Ilimit=3.31A Plimit=62.8W 60 88.7KOhm @ V+ R5721 G C5718 15KOhm 2 S 2 28,59 AC_APR_UC 11 Q5711 2N7002 @ MAX8725_LDO R5723 U5701 LMV321IDBVR @ AD_IINP + 4.7KOhm 3 D R5718 100KOhm 2 +5VCHG S 47UF/6.3V 2 C5720 0.1UF/25V 2N7002 G R5722 C5717 0.1UF/25V @ 1SS355 D5706 @2 11 CHG_EN# +2.5VREF PWRLMT# Q5707 D 28 3 2 S 28 Power Limit C5715 1UF/16V 340KOhm Q5712 2N7002 G R5725 D 11 PRECHG 28 1MOhm G 11 S Title : Size C Project Name Rev A6F 1.0 Date: Monday, March 06, 2006 POWER_CHARGER Engineer: Johnson Zhang Sheet 57 of 63 D D C C B B A A Title : Dummy Engineer: Johnson Zhang ASUSTeK COMPUTER INC Size Project Name C Rev A6F 1.0 Date: Monday, March 06, 2006 Sheet 58 of 63 BATTERY IN DETECT ADAPTER IN DETECT +3VA TPC28T T5900 R5900 Q5900B UM6K1N Q5900A UM6K1N TS# ACIN_OC# 28 Q5901 2N7002 G S C5900 1000PF/16V D 11 28,57 AC_APR_UC 40,57 D R5901 T5901 TPC28T D 100KOhm 100KOhm 1 BAT_IN_OC# 28 C C +5VLCM, +5VCHG & +2.5VREF B B +5VCHG A/D_DOCK_IN TPC28T T5902 D5900 TPC28T T5903 U5900 1 F02JK2E R5904 1KOhm +2.5VREF LM4040BIM3 U5901 C5902 1UF/10V 1UF/10V 1 C5904 1UF/25V C5905 2 C5903 4.7UF/25V 2 TPC28T T5904 L78L05ACUTR INPUT OUTPUT GND +5VLCM +5V A A Title : ASUSTeK COMPUTER INC Size Custom Project Name Rev A6F 1.0 Date: Monday, March 06, 2006 POWER_DETECT Engineer: Johnson Zhang Sheet 59 of 63 BATTERY A/D_SD# (OVP) A/D_DOCK_IN D D R6001 47KOhm PMBS3906 BAT_S B C OVP=17.25V R6010 T6000 TPC28T R6007 B 1 +5VLCM U6000 PMBS3904 C Q6002 E C6005 0.1UF/16V VOUT1 VIN1VIN1+ GND VCC VOUT2 VIN2VIN2+ C LMV358IDR 2 C6002 1 C R6013 5.6KOhm 57.6KOhm R6006 C6001 4.7UF/10V 10UF/6.3V 10KOhm C6004 0.1UF/16V 1 +2.5VREF C6000 0.1UF/25V @ A/D_SD# 340KOhm E 57 R6003 Q6001 5.1KOhm 100KOhm T6001 TPC28T R6002 POWER GOOD DETECTER B B +3VS R6023 100KOhm +3VSUS JP6000 39,51 3V_5V_PWRGD 52 1.05V_1.5V_PWRGD A @ Q6010B UM6K1N DDR_PWRGD TPC28T T6005 3V_5V_PWRGD TPC28T T6006 1.05V_1.5V_PWRGD C6007 4.7UF/6.3V 1SS355 JP6003 Q6010A UM6K1N SHORTPIN D6001 T6007 TPC28T 1 @ SHORTPIN JP6001 VRM_PWRGD TPC28T T6004 1 2 53 DDR_PWRGD @ R6021 560KOhm D6000 1SS355 TPC28T T6003 39,50 VRM_PWRGD R6022 100KOhm FORCE_OFF# 28,51 21,25,33,36,37,39,61 SUSB# A SHORTPIN Title : ASUSTeK COMPUTER INC Size Custom Project Name Rev A6F 1.0 Date: Monday, March 06, 2006 POWER_PROTECT Engineer: Johnson Zhang Sheet 60 of 63 SUSC#_PWR POWER 21,25,33,36,37,39,60 SUSB# R6101 TPC28T T6105 1 TPC28T T6104 (1.52A) 1KOhm D 1 R6100 10KOhm 51,52,53,54,63 SUSB#_PWR G D C6100 0.1UF/50V @ +3V D S Q6100 PMN45EN TPC28T T6103 +3VO TPC28T T6102 TPC28T TPC28T T6100 T6101 C6101 0.01UF/50V DRAIN_2 SOURCE_3 SOURCE_4 GATE_2 TPC28T T6108 TPC28T T6109 +5V (5.52A) Q6106 N DRAIN_1 SOURCE_1 SOURCE_2 GATE_1 +5VO TPC28T TPC28T T6106 T6107 FDW2501NZ 0Ohm 1 R6102 C6102 3900PF/50V R6110 100KOhm TPC28T T6125 TPC28T T6123 C 100KOhm C 10K Q6105 UMC4N (0.001A) R6104 B B 47K 47K E 53,63 SUSC#_PWR +12V E 47K TPC28T T6124 C +12VSUS C SUSB#_PWR POWER TPC28T T6114 TPC28T T6112 11 +3VS 53,63 SUSC#_PWR (2.55A) R6106 TPC28T T6119 1KOhm B 0Ohm 1 G R6105 D B SUSC# TPC28T T6113 Q6102 PMN45EN S 1 +3VO 26,36,39 TPC28T TPC28T T6110 T6111 C6103 0.1UF/25V @ C6104 0.1UF/50V Q6108 PMN45EN TPC28T T6117 TPC28T T6118 11 +5VS (3.1A) +12VS (0.002A) G D 1 +5VO S TPC28T TPC28T T6115 T6116 0Ohm C6106 0.1UF/50V C6105 0.1UF/25V @ 1 R6107 R6108 100KOhm TPC28T T6121 TPC28T T6120 Title : R6109 C 10K B Q6104 UMC4N B 47K E 47K 1 51,52,53,54,63 SUSB#_PWR 100KOhm E 47K TPC28T T6122 C A +12VSUS A ASUSTeK COMPUTER INC Size Custom Project Name Rev A6F 1.0 Date: Monday, March 06, 2006 POWER_LOAD SWITCH Engineer: Johnson Zhang Sheet 61 of 63 A/D_DOCK_IN +5VCHG L78L05ACUTR (Regulator) D PRECHG MAX8724 (Controllor) MAX1836 (Regulator) VSUS_ON SHUT_DOWN# +2.5VREF LM4040BIM (Regulator) AC_APR_UC AC_BAT_SYS BAT D SUSC#_PWR AC_BAT_SYS +5VLCM SWITCH (F02JK2E) +5V BATSEL_2P# PRECHG A/D_SD# BAT_LEARN BATSEL_3S# CHG_EN# +12VSUS (1mA) MIC5235BM (Regulator) SUSB#_PWR +V3V +3VAO MIC5235BM (Regulator) UMC4N (SWITCH) +12V UMC4N (SWITCH) +12VS +3.3VSUS +12V +3VO (5.7A) PMN451N (SWITCH) +3V (2.7A) PMN45EN (SWITCH) +3VS (2.555A) +12V FDW2501NZ (SWITCH) +5V (1.3A) +12VS FDW2501NZ (SWITCH) +5VS (5.098A) CM8562 (Regulator) +2.5VO C TPS51020 SHUT_DOWN# FORCE_OFF# SUSC#_PWR +12VS (Controllor) C 3V_5V_PWRGD +5VSUS VSUS_ON +5VO(7.0A) SUSB#_PWR +5VAO +2.5VS (2.0A) B B +1.5VO +5VO +1.5VS (5.741A) ISL6227CAZ (Controllor) SUSB#_PWR +1.05VO +1.05VS(7.05A) 1.05V_1.5V_PWRGD +1.8VO +5VO SUSB#_PWR SUSC#_PWR NPC5214 (Controllor) +0.9VO +1.8V (8.2A) +0.9VS (2A) DDR_PWRGD PWR_OK_VGA A A +5VO & +3VO +VCORE (36A) ISL6262CRZ (Controllor) CPU_VRON VR_VID0~VR_VID6, STP_CPU#, PM_DPRSLPVR, MCH_OK, PM_PSI#,VCCSENSE,VSSSENSE Title : ASUSTeK COMPUTER INC VRM_PWRGD, CLK_PWR_GD# Size Custom Project Name Rev A6F 1.0 Date: Monday, March 06, 2006 POWER_FLOWCHART Engineer: Johnson Zhang Sheet 62 of 63 AC_BAT_SYS AC_BAT_SYS 12,50,51,52,53,54,57 D +3VA +3VA 4,12,20,28,37,39,54,59 +5VO +5VO 35,51,52,53,54,61 +3VO +3VO 51,52,61 +3VSUS +3VSUS 18,19,20,28,33,34,37,39,51,60 D FOR POWER TEST JP6300 +3VA +5VSUS +3V +5VSUS 20,36,37,51 +3V 12,18,22,26,30,31,32,34,35,36,38,41,54,61 +3VS 4,5,7,9,11,12,13,14,15,19,20,21,22,25,26,27,28,30,36,38,39,42,50,52,60,61 2 CPU_VRON_PWR 50 SGL_JUMP @ JP6301 +3VS 1 2 SUSB#_PWR SUSB#_PWR 51,52,53,54,61 SGL_JUMP @ +12VSUS +12VSUS 51,61 JP6302 +12V +12V +12VS +5V 4,32,36,61 +12VS 12,22,36,61 +5V 9,12,22,31,35,36,37,41,59,61 +5VS +5VS 4,13,19,20,21,22,27,28,36,37,38,44,50,61 +2.5VO +2.5VO 54 +2.5VS +2.5VS 9,13,36,54 +1.8VO +1.8VO 53 +1.8V +1.8V 7,10,14,15,36,53 +0.9VS +0.9VS 16,36,53 1 2 SUSC#_PWR SUSC#_PWR 53,61 SGL_JUMP @ C C BAT 29,57 +5VCHG +5VCHG 57,59 +5VLCM +5VLCM 37,57,59,60 BAT +2.5VREF 57,59,60 +2.5VREF +VCORE B +VCORE B 3,50 BAT_CON 40,57 BAT_CON A A Title : ASUSTeK COMPUTER INC Size Custom Project Name Rev A6F 1.0 Date: Monday, March 06, 2006 POWER_SIGNAL Engineer: Johnson Zhang Sheet 63 of 63 www.s-manuals.com ... +VCCP_AGTL+ C903 AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R 11 P 11 N 11 M 11 R10 P10 N10 M10 P9 N9... 10 8 10 9 11 0 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 12 0 12 1 12 2 12 3 12 4 12 5 12 6 12 7 12 8 12 9 1 VDD12 C3305 PM_CLKRUN# 19 ,30,38 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33... Vss100 Vss1 01 Vss102 Vss103 Vss104 Vss105 Vss106 Vss107 Vss108 Vss109 Vss 110 Vss 111 Vss 112 Vss 113 Vss 114 Vss 115 Vss 116 Vss 117 Vss 118 Vss 119 Vss120 Vss1 21 Vss122 Vss123 Vss124 Vss125 Vss126 Vss127