5 D C B A Content PAGE 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 36 37 40 41 42 43 44 45 46 48 50 51 52 53 56 57 60 61 65 67 70 71 72 73 74 75 76 77 78 79 Block Diagram System Setting CPU(1)_DMI,PEG,FDI,CLK,MISC CPU(2)_DDR3 CPU(3)_CFG,RSVD,GND CPU(4)_PWR CPU(5)_XDP DDR3 SO-DIMM_0 DDR3 SO-DIMM_1 DDR3 CA_DQ VOLTAGE VID controller PCH_IBEX(1)SATA,IHDA,RTC,LPC PCH_IBEX(2)_PCIE,CLK,SMB,PEG PCH_IBEX(3)_FDI,DMI,SYS PWR PCH_IBEX(4)_DP,LVDS,CRT PCH_IBEX(5)_PCI,NVRAM,USB PCH_IBEX(6)CPU,GPIO,MISC PCH_IBEX(7)_POWER,GND PCH_IBEX(8)_POWER,GND PCH_SPI ROM,OTH CLK_ICS9LPR362 EC_IT8541(1/2) EC_IT8541(2/2)KB, TP RST_Reset Circuit HANKSVILLE LAN_RJ45 CODEC-ALC269 AUD_Amp & Jack CB_R5C833 CB_R5C833 CB_4in1 CardReader CB_NewCard BUG_Debug CRT_LCD Panel CRT_D-Sub 80 81 82 83 84 86 88 90 91 92 93 94 PW_VCORE(MAX17034) PW_SYSTEM(MAX17020) PW_I/O_VTT_CPU&+1.1VM PW_I/O_DDR & VTT& +1.8VS PW_I/O_3VM & ME_+VM_PWEGD PW_+VGFX_CORE(MAX17028) PW_CHARGER(MAX17015) PW_DETECT PW_LOAD SWITCH PW_PROTECT PW_SIGNAL PW_FLOWCHART TV_HDMI FAN_Fan & Sensor XDD_HDD & ODD USB_USB Port *2 MINICARD(WLAN) LED_Indicator DSG_Discharge DC_DC & BAT Conn BT_Bluetooth ME_Conn & Skew Hole PCH_XDP, ONFI VGA_M96 Main (1) VGA_M96 Main (2) VGA_M96 MEM CHANNEL A VGA_M96 MEM CHANNEL B VGA_M96 Power (1) VGA_M96 Power (2) VGA_M96 THERMAL/Memory SS VGA_M96 Straps VGA_POWER_VGA_CORE & RAM VGA_POWER_VGA_+1.2VS_+1.1VS Power VCORE K72JK Schematic R2.0 Page 80 System Page 81 D 1.5VS & 1.05VS Page 82 DDR & VTT HDMI Page 83 PAGE 48 CRT +2.5VS CPU Arrandale PCIE x16 PARK-XT PAGE 46 DDR3 1066 Page 84 DDR3 SO-DIMM Charger PAGE 16-18 PAGE 70 Page 86 LCD Panel PAGE 3-6 Detect PAGE 45 Page 90 DMI x4 Load Switch Page 91 Touchpad PCIE x1 EC PAGE 31 ITE IT8502 Keyboard C GigaLAN RJ45 AR8131 PAGE 30 PAGE 31 PCIE x1 MiniCard USB Debug Conn WiFi PAGE 53 PAGE 44 PAGE 20-28 USB Port(1) PAGE 52 INT MIC Azalia Azalia Codec PAGE 45 IDT 92HD81 Jack USB Port(2) SATA PAGE 52 PAGE 36 PAGE 65 USB Port(3) 1st HDD PAGE 51 B PAGE 43 2nd HDD PAGE 51 Daughter Board USB Port(4) PAGE 43 ODD CardReader PAGE 51 Alcor 6433 PAGE 43 CMOS Camera PAGE 45 Clock Generator VID controller PAGE 29 DC & BATT Conn PAGE 19 PWM Fan PAGE 60 Discharge Circuit Bluetooth PAGE 57 PAGE 61 Reset Circuit PAGE 50 A PAGE 32 Title : Block Diagram Engineer: ASUSTeK COMPUTER INC NB4 Size Jerry Mou Project Name Custom Date: Page 92 PAGE 34 PAGE 33 PCH HM55 LPC Power Protect Rev K72Jr Friday, January 22, 2010 2.0 Sheet 1 of 99 EC IT8512 D C B A PCH GPIO Usage GPIO 00 GPO GPIO 01 GPO GPIO [02:05] Native GPIO 06 GPO Signal Name Pull Up / Pull Down Power +3VS PCI_INT[E:H]# INT PU 20K +3VS EXT PU 10K +5VS INT PU 20K +3VS GPIO 07 GPO INT PU 20K +3VS GPIO 08 GPI EXT_SMI# EXT PU & INT PU +3VSUS GPIO 09 Native Native EXT PU 10K EXT PU 10K +3VSUS GPIO 10 USB_OC#5 USB_OC#6 GPIO 11 GPI EXT_SCI# EXT PU 10K +3VSUS GPIO 12 GPO GPIO 13 GPO +3VSUS +3VSUS GPIO 14 GPO USB_OC#7 GPIO 15 GPO BT_LED GPIO 16 GPO GPIO 17 GPO INT PD 20K +3VSUS EXT PU 10K INT PD 20K +3VSUS +3VSUS EXT PU 10K INT PU 20K +3VS +3VS GPIO 18 Native CLKREQ1# EXT PU 10K +3VS GPIO 19 Native Native EXT PU 10K EXT PD 10K +3VS GPIO 20 SATA1GP CLKREQ2# GPIO 21 Native SATA0GP EXT PU 10K +3VS WLAN_LED +3VS GPIO 22 GPO GPIO 23 GPO GPIO 24 GPO GPIO 25 Native CLKREQ3# EXT PU 10K +3VSUS GPIO 26 Native CLKREQ4# +3VSUS GPIO 27 GPO EXT PU 10K INT PU 20K GPIO 28 GPO WLAN_ON# INT PU 20K +3VSUS +3VS INT PU 20K +3VS +3VSUS +3VSUS GPIO 29 GPO GPIO 30 Native ME_SusPwrDnAck EXT PU 10K +3VSUS GPIO 31 Native ME_AC_PRESENT EXT PU 10K +3VSUS GPIO 32 Native PM_CLKRUN# EXT PU 10K +3VS GPIO 33 GPI Native PCH_SPI_OV STP_PCI# INT PU 20K +3VS GPIO 34 GPIO 35 Native SATA_CLK_REQ# GPO EXT PD 10K EXT PU 10K +3VS GPIO 36 GPIO 37 GPO EXT PU 10K +3VS GPIO 38 GPI PCB_ID0 EXT PU/PD +3VS GPIO 39 GPI PCB_ID1 EXT PU/PD +3VS GPIO 40 Native EXT PU 10K +3VSUS GPIO 41 Native USB_OC#1 USB_OC#2 EXT PU 10K +3VSUS GPIO 42 Native USB_OC#3 EXT PU 10K +3VSUS GPIO 43 Native USB_OC#4 EXT PU 10K +3VSUS GPIO 44 Native CLK_REQ5# EXT PU 10K +3VSUS GPIO 45 Native CLK_REQ6# INT & EXT PU +3VSUS GPIO 46 GPO GPIO 47 Native GPIO 48 GPO GPIO 49 +3VSUS +3VS +3VS +3VSUS CLKREQ_PEG#A EXT PD 10K Native TEMP_ALERT# EXT PU 10K +3VS GPIO 50 Native PCI_REQ1# EXT PU 10K +5VS GPIO 51 Native PCI_GNT1# INT PU 20K +3VS GPIO 52 Native PCI_REQ2# EXT PU 10K +5VS GPIO 53 Native PCI_GNT2# INT PU 20K +3VS GPIO 54 Native PCI_REQ3# EXT PU 10K +5VS GPIO 55 Native PCI_GNT3# INT PU 20K +3VS +3VSUS +3VS GPIO 56 Native CLKREQ_PEG#B EXT PU 10K +3VSUS GPIO 57 GPO BT_ON EXT PU(DIODE) +3VSUS GPIO 58 Native SML1_CLK EXT PU 10K +3VSUS GPIO 59 Native USB_OC#0 EXT PU 10K +3VSUS GPIO 60 Native SML0ALERT# EXT PU 10K +3VSUS GPIO 61 Native SUS_STAT# +3VSUS GPIO 62 Native SUSCLK +3VSUS GPIO 63 Native SLP_S5# +3VSUS GPIO 64 Native CLK_OUT0 INT PD 20K +3VS GPIO 65 Native CLK_OUT1 INT PD 20K +3VS GPIO 66 Native CLK_OUT2 INT PD 20K +3VS GPIO 67 Native CLK_CARD_READER_48 INT PD 20K +3VS GPIO 72 Native PM_BATLOW# INT PU 20K +3VSUS GPIO 73 Native CLK_REQ0# EXT PU 10K +3VSUS GPIO 74 Native SML1ALERT# EXT PU 10K +3VSUS GPIO 75 Native SML1_DATA EXT PU 10K +3VSUS EC GPIO Use As GPA0 GPA1 GPA2 GPA3 GPA4 GPA5 GPA6 GPA7 GPB0 GPB1 GPB2 GPB3 GPB4 GPB5 GPB6 GPB7 GPC0 GPC1 GPC2 GPC3 GPC4 GPC5 GPC6 GPC7 GPD0 GPD1 GPD2 GPD3 GPD4 GPD5 GPD6 GPD7 GPE0 GPE1 GPE2 GPE3 GPE4 GPE5 GPE6 GPE7 GPF0 GPF1 GPF2 GPF3 GPF4 GPF5 GPF6 GPF7 GPG0 GPG1 GPG2 GPG6 GPH0 GPH1 GPH2 GPH3 GPH4 GPH5 GPH6 GPI0 GPI1 GPI2 GPI3 GPI4 GPI5 GPI6 GPI7 GPJ0 GPJ1 GPJ2 GPJ3 GPJ4 GPJ5 O O O O O O IO IO O O O IO IO O I O I I I I I O O O I O O O O I I O I I IO O I O O IO O O O O O O I I I I I I I O O O O O Signal Name PWR_LED# CHG_LED# CHG_FULL_LED# LCD_BL_PWM FAN0_PWM BATSEL_0 BATSEL_1 ME_AC_PRESENT_EC SMB0_CLK SMB0_DAT A20GATE RCIN# PM_RSMRST# SMB1_CLK SMB1_DAT PM_PWRBTN# AC_IN_OC# OP_SD# BAT1_IN_OC# PWRLIMIT# PM_SUSC# BUF_PLT_RST# EXT_SCI# EXT_SMI# LCD_BACKOFF# FAN0_TACH SD_CD#_EC VSUS_ON PWR_SW# LID_SW# TP_CLK TP_DAT THRO_CPU PCH_SPI_OV ME_SusPwrDnAck_EC PM_SUSB# OCMV_CTL0 OCMV_CTL1 PM_CLKRUN# CHG_EN SUSC_EC# SUSB_EC# NUM_LED# CAP_LED# SUS_PWRGD ALL_SYSTEM_PWRGD VRM_PWRGD PCH_TEMP_ALERT# CPU_VRON PM_PWROK VSET_EC ISET_EC - EC GPIO Use As GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 PCIE Signal Name PCIE I I Minicard WLAN PCIE PCIE - PCIE PCIE I I O GLAN PCIE PCIE D - SATA SATA HDD (1) SATA1 SATA ODD SATA4 SATA HDD (2) SATA5 O O K72J - USB port USB port USB port ( D/B ) USB port ( D/B ) MiniCard ( Full ) MiniCard ( Half ) Camera 10 C 11 Card Reader 12 Bluetooth 13 SM_BUS ADDRESS : PCH Master SM-Bus Device SM-Bus Address Clock Generator(ICS9LRS3162) 1101001x ( D2 ) SO-DIMM 1010000x ( A0 ) SO-DIMM 1010001x ( A2 ) B EC Master (SMB1) SM-Bus Device SM-Bus Address CPU Thermal Sensor(G781) 1001100x ( 98 ) VGA Thermal IC(G781-1) 1001101x ( 9A ) Device Identification CPU Thermal Sensor P/N: 1st 06G023048011 component name G781F S S S Clock Gen P/N: 1st 06G011610010 component name ICS9LRS3162 S S A VGA Thermal Sensor 1st 06G023048020 component name G781-1 S S Title : System Setting Size Custom Date: Engineer: ASUSTeK COMPUTER INC NB4 Jerry Mou Project Name Rev K72Jr Friday, December 11, 2009 2.0 Sheet of 99 U0301B 20Ohm 1% H_COMP3 AT23 R0304 20Ohm 1% H_COMP2 AT24 COMP2 R0305 49.9Ohm 1% H_COMP1 G16 COMP1 R0306 49.9Ohm 1% H_COMP0 AT26 VCC_AXGSENSE,VSS_AXGSENSE ~15mW power saving.(DG R0.8 P.70) VCCAXG, 30,88 PWRLIMIT# Can be connected to GND directly: SL0310 25 H_PECI D0301 RB751V-40 @ +VTT_CPU 49.9Ohm THRO_CPU R0322 R0317 0402 @ 1% H_CATERR# AK14 H_PECI_ISO AT15 H_PROCHOT_S# AK15 S RN0302B 1KOhm THERMTRIP# Q0301 AP26 22 PM_SYNC# *FDI_FSYNC[0],FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1] can be ganged together with one resistor *On the other hand,FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and FDI_INT signals on PCH side can be left as no connect without any power or functional impact T0303 22 H_DRAM_PWRGD SL0313 SL0314 SL0315 SL0316 0402 0402 0402 0402 PM_SYNC#_R AL15 VCCPWRGOOD_1_R AN14 VCCPWRGOOD_1 VCCPWRGOOD_0_R AN27 VCCPWRGOOD_0 VDDPWRGOOD_R AM26 BUF_PLT_RST# R0318 1.5KOhm 1% DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 D24 G24 F23 H23 22 22 22 22 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 D25 F24 E23 G23 FDI_FSYNC0 FDI_FSYNC1 F17 E17 FDI_INT C17 FDI_LSYNC0 FDI_LSYNC1 F18 D17 A FDI_TX#[0] FDI_TX#[1] FDI_TX#[2] FDI_TX#[3] FDI_TX#[4] FDI_TX#[5] FDI_TX#[6] FDI_TX#[7] FDI_TX[0] FDI_TX[1] FDI_TX[2] FDI_TX[3] FDI_TX[4] FDI_TX[5] FDI_TX[6] FDI_TX[7] FDI_FSYNC[0] FDI_FSYNC[1] FDI_INT FDI_LSYNC[0] FDI_LSYNC[1] PEG_RX[0] PEG_RX[1] PEG_RX[2] PEG_RX[3] PEG_RX[4] PEG_RX[5] PEG_RX[6] PEG_RX[7] PEG_RX[8] PEG_RX[9] PEG_RX[10] PEG_RX[11] PEG_RX[12] PEG_RX[13] PEG_RX[14] PEG_RX[15] PEG_TX#[0] PEG_TX#[1] PEG_TX#[2] PEG_TX#[3] PEG_TX#[4] PEG_TX#[5] PEG_TX#[6] PEG_TX#[7] PEG_TX#[8] PEG_TX#[9] PEG_TX#[10] PEG_TX#[11] PEG_TX#[12] PEG_TX#[13] PEG_TX#[14] PEG_TX#[15] PEG_TX[0] PEG_TX[1] PEG_TX[2] PEG_TX[3] PEG_TX[4] PEG_TX[5] PEG_TX[6] PEG_TX[7] PEG_TX[8] PEG_TX[9] PEG_TX[10] PEG_TX[11] PEG_TX[12] PEG_TX[13] PEG_TX[14] PEG_TX[15] TAPPWRGOOD +1.5V R0320 1.1KOhm 1% VDDPWRGOOD_R R0321 3.01KOHM 1% 70 J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 PCIENB_RXP0 PCIENB_RXP1 PCIENB_RXP2 PCIENB_RXP3 PCIENB_RXP4 PCIENB_RXP5 PCIENB_RXP6 PCIENB_RXP7 PCIENB_RXP8 PCIENB_RXP9 PCIENB_RXP10 PCIENB_RXP11 PCIENB_RXP12 PCIENB_RXP13 PCIENB_RXP14 PCIENB_RXP15 L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 PCIENB_TXN0 CX0301 PCIENB_TXN1 CX0302 PCIENB_TXN2 CX0303 PCIENB_TXN3 CX0304 PCIENB_TXN4 CX0305 PCIENB_TXN5 CX0306 PCIENB_TXN6 CX0307 PCIENB_TXN7 CX0308 PCIENB_TXN8 CX0309 PCIENB_TXN9 CX0310 PCIENB_TXN10 CX0311 PCIENB_TXN11 CX0312 PCIENB_TXN12 CX0313 PCIENB_TXN13 CX0314 PCIENB_TXN14 CX0315 PCIENB_TXN15 CX0316 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V GFX_VGA_RXN0 GFX_VGA_RXN1 GFX_VGA_RXN2 GFX_VGA_RXN3 GFX_VGA_RXN4 GFX_VGA_RXN5 GFX_VGA_RXN6 GFX_VGA_RXN7 GFX_VGA_RXN8 GFX_VGA_RXN9 GFX_VGA_RXN10 GFX_VGA_RXN11 GFX_VGA_RXN12 GFX_VGA_RXN13 GFX_VGA_RXN14 GFX_VGA_RXN15 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25 PCIENB_TXP0 PCIENB_TXP1 PCIENB_TXP2 PCIENB_TXP3 PCIENB_TXP4 PCIENB_TXP5 PCIENB_TXP6 PCIENB_TXP7 PCIENB_TXP8 PCIENB_TXP9 PCIENB_TXP10 PCIENB_TXP11 PCIENB_TXP12 PCIENB_TXP13 PCIENB_TXP14 PCIENB_TXP15 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V 0.1UF/16V GFX_VGA_RXP0 GFX_VGA_RXP1 GFX_VGA_RXP2 GFX_VGA_RXP3 GFX_VGA_RXP4 GFX_VGA_RXP5 GFX_VGA_RXP6 GFX_VGA_RXP7 GFX_VGA_RXP8 GFX_VGA_RXP9 GFX_VGA_RXP10 GFX_VGA_RXP11 GFX_VGA_RXP12 GFX_VGA_RXP13 GFX_VGA_RXP14 GFX_VGA_RXP15 SM_RCOMP0 R0331 SM_RCOMP1 R0332 SM_RCOMP2 R0333 1 AN15 AP15 PM_EXTTS#1 M_DRAMRST# 16,17 100Ohm 24.9Ohm 130Ohm 1% 1% 1% PM_EXTTS#0 16,17 +VTT_CPU RN0301A 10KOHM 10KOHM RN0301B AT28 AP27 XDP_PRDY# XDP_PREQ# AN28 AP28 AT27 XDP_TCLK XDP_TMS XDP_TRST# TDI TDO TDI_M TDO_M AT29 AR27 AR29 AP29 XDP_TDI_R XDP_TDO_R XDP_TDI_M XDP_TDO_M DBR# AN25 H_DBR#_R BPM#[0] BPM#[1] BPM#[2] BPM#[3] BPM#[4] BPM#[5] BPM#[6] BPM#[7] AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23 XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 R0336 0Ohm XDP_DBRESET# 7,22,67 XDP_OBS[7:0] C +VTT_CPU H_CPURST# R0313 @ 68OHM XDP_TMS R0345 @ 51Ohm XDP_TDI_R R0346 @ 51Ohm XDP_PREQ# R0347 @ 51Ohm BCLK_CPU_P_PCH T0304 XDP_TDO R0355 H_VTTPWRGD T0305 XDP_TCLK R0348 VCCPWRGOOD_0_R T0306 XDP_TRST# R0354 VCCPWRGOOD_1_R T0307 PLT_RST#_R T0308 XDP_TRST# T0309 XDP_TCLK T0310 JTAG MAPPING XDP_TMS T0311 XDP_TDI_R XDP_TDI_R T0312 XDP_TDO_M 51Ohm @ 51Ohm 51Ohm B 0402 R0350 SL0308 XDP_TDI 0Ohm XDP_TDO @ CX0317 CX0318 CX0319 CX0320 CX0321 CX0322 CX0323 CX0324 CX0325 CX0326 CX0327 CX0328 CX0329 CX0330 CX0331 CX0332 GFX_VGA_RXN[15:0] 70 XDP_TDO_R T0313 XDP_TDI_M T0314 XDP_TDO_M T0315 XDP_TDI_M XDP_TDO_R For CPU Boundary Scan SL0321 R0352 1 @ 0Ohm SL0309 0402 Arrandale Sighting Report : A PCI Express Graphics Hang With L1 Enabled in Rare Cases Title : CPU(1)_DMI,PEG DG R1.1 P.109: *On Clarksfield rPGA only designs, VCCPWRGOOD_1 on the Clarksfield processor can be left as No Connect Size Date: Engineer: ASUSTeK COMPUTER INC NB1 Custom GFX_VGA_RXP[15:0] 70 SOCKET989 SL0319 SL0320 RSTIN# CPU Socket : 12G011909890 Molex : 12G011909891 Tape & Reel : 12G011909893 750Ohm 1% PCIENB_RXN[15:0] 70 PCIENB_RXP[15:0] AL1 AM1 AN1 0402 0402 F6 0402 D22 C21 D20 C18 G22 E20 F20 G19 DMI_TX[0] DMI_TX[1] DMI_TX[2] DMI_TX[3] Intel(R) FDI E22 D21 D19 D18 G21 E19 F21 G18 DMI_TX#[0] DMI_TX#[1] DMI_TX#[2] DMI_TX#[3] VTTPWRGOOD 1 22 22 22 22 DMI_RX[0] DMI_RX[1] DMI_RX[2] DMI_RX[3] PCIENB_RXN0 PCIENB_RXN1 PCIENB_RXN2 PCIENB_RXN3 PCIENB_RXN4 PCIENB_RXN5 PCIENB_RXN6 PCIENB_RXN7 PCIENB_RXN8 PCIENB_RXN9 PCIENB_RXN10 PCIENB_RXN11 PCIENB_RXN12 PCIENB_RXN13 PCIENB_RXN14 PCIENB_RXN15 B24 D23 B23 A22 K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 PM_EXT_TS#[0] PM_EXT_TS#[1] TCK TMS TRST# DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 PEG_RX#[0] PEG_RX#[1] PEG_RX#[2] PEG_RX#[3] PEG_RX#[4] PEG_RX#[5] PEG_RX#[6] PEG_RX#[7] PEG_RX#[8] PEG_RX#[9] PEG_RX#[10] PEG_RX#[11] PEG_RX#[12] PEG_RX#[13] PEG_RX#[14] PEG_RX#[15] 22 22 22 22 DMI_RX#[0] DMI_RX#[1] DMI_RX#[2] DMI_RX#[3] SM_DRAMPWROK CLK_DMI_PCH 21 CLK_DMI#_PCH 21 CLKDREF CLKDREF# A18 A17 SOCKET989 A24 C23 B22 A21 PCI EXPRESS GRAPHICS DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI 22 22 22 22 49.9Ohm 1% AL14 R0319 750Ohm 1% U0301A B26 PEG_IRCOMP_R R0301 A26 B27 R0302 A25 EXP_RBIAS PLT_RST#_R PM_SYNC CLK_ITP_BCLK CLK_ITP_BCLK# E16 D16 7,24,30,32,33,53,64,67,70 AK13 AM15 H_PWRGD_XDP Arrandale Sighting Report : RESET_OBS# 58 H_VTTPWRGD C PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS SM_RCOMP[0] SM_RCOMP[1] SM_RCOMP[2] H_CPURST# BCLK_CPU_P_PCH 25 BCLK_CPU_N_PCH 25 AR30 AT30 D SM_DRAMRST# PRDY# PREQ# T0302 7,25 H_CPUPWRGD System May Hang With DMI L1 Enabled DPLL_REF_SSCLK DPLL_REF_SSCLK# 2N7002ET1G G 2 SL0305 SL0306 SL0307 RN0302A 1KOhm D 11 30 THRO_CPU DG R1.1 P.83: B PROCHOT# PWR MANAGEMENT 0402 0402 0402 AN26 3 1 1 PECI 68OHM 25 H_THRMTRIP# VCCFDIPLL FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1 FDI_INT CATERR# 0Ohm DPLL_REF_CLK,DPLL_REF_CLK# Connect to +V1.05S rail: SKTOCC# A16 B16 Connected to GND: R0307 AH24 PEG_CLK PEG_CLK# THERMAL For EC request, to read PECI via EC Connection: R0317.2 >Q0301.1 >U3001.118 FDI_FSYNC[0:1],FDI_LSYNC[0:1],FDI_INT,GFX_IMON TP_SKTOCC# COMP0 BCLK_ITP BCLK_ITP# JTAG & BPM Pull-down to GND via 1KΩ ± 5% resistor: D T0301 +VTT_CPU BCLK BCLK# CLOCKS FDI_TX#[0:7],FDI_TX[0:7],FDI_RX#[0:7],FDI_RX[0:7] COMP3 DDR3 MISC NC: R0303 MISC FDI disable: (For discrete graphic) Jerry Mou Project Name Rev K72Jr 2.0 Sheet Friday, December 11, 2009 of 99 U0301C U0301D M_A_DQ0 A10 M_A_DQ1 C10 M_A_DQ2 C7 M_A_DQ3 A7 M_A_DQ4 B10 M_A_DQ5 D10 M_A_DQ6 E10 M_A_DQ7 A8 M_A_DQ8 D8 M_A_DQ9 F10 M_A_DQ10 E6 M_A_DQ11 F7 M_A_DQ12 E9 M_A_DQ13 B7 M_A_DQ14 E7 M_A_DQ15 C6 M_A_DQ16 H10 M_A_DQ17 G8 M_A_DQ18 K7 M_A_DQ19 J8 M_A_DQ20 G7 M_A_DQ21 G10 M_A_DQ22 J7 M_A_DQ23 J10 M_A_DQ24 L7 M_A_DQ25 M6 M_A_DQ26 M8 M_A_DQ27 L9 M_A_DQ28 L6 M_A_DQ29 K8 M_A_DQ30 N8 M_A_DQ31 P9 M_A_DQ32 AH5 M_A_DQ33 AF5 M_A_DQ34 AK6 M_A_DQ35 AK7 M_A_DQ36 AF6 M_A_DQ37 AG5 M_A_DQ38 AJ7 M_A_DQ39 AJ6 M_A_DQ40 AJ10 M_A_DQ41 AJ9 M_A_DQ42 AL10 M_A_DQ43 AK12 M_A_DQ44 AK8 M_A_DQ45 AL7 M_A_DQ46 AK11 M_A_DQ47 AL8 M_A_DQ48 AN8 M_A_DQ49AM10 M_A_DQ50 AR11 M_A_DQ51 AL11 M_A_DQ52 AM9 M_A_DQ53 AN9 M_A_DQ54 AT11 M_A_DQ55 AP12 M_A_DQ56AM12 M_A_DQ57 AN12 M_A_DQ58AM13 M_A_DQ59 AT14 M_A_DQ60 AT12 M_A_DQ61 AL13 M_A_DQ62 AR14 M_A_DQ63 AP14 C B SA_DQ[0] SA_DQ[1] SA_DQ[2] SA_DQ[3] SA_DQ[4] SA_DQ[5] SA_DQ[6] SA_DQ[7] SA_DQ[8] SA_DQ[9] SA_DQ[10] SA_DQ[11] SA_DQ[12] SA_DQ[13] SA_DQ[14] SA_DQ[15] SA_DQ[16] SA_DQ[17] SA_DQ[18] SA_DQ[19] SA_DQ[20] SA_DQ[21] SA_DQ[22] SA_DQ[23] SA_DQ[24] SA_DQ[25] SA_DQ[26] SA_DQ[27] SA_DQ[28] SA_DQ[29] SA_DQ[30] SA_DQ[31] SA_DQ[32] SA_DQ[33] SA_DQ[34] SA_DQ[35] SA_DQ[36] SA_DQ[37] SA_DQ[38] SA_DQ[39] SA_DQ[40] SA_DQ[41] SA_DQ[42] SA_DQ[43] SA_DQ[44] SA_DQ[45] SA_DQ[46] SA_DQ[47] SA_DQ[48] SA_DQ[49] SA_DQ[50] SA_DQ[51] SA_DQ[52] SA_DQ[53] SA_DQ[54] SA_DQ[55] SA_DQ[56] SA_DQ[57] SA_DQ[58] SA_DQ[59] SA_DQ[60] SA_DQ[61] SA_DQ[62] SA_DQ[63] 16 16 16 M_A_BS0 M_A_BS1 M_A_BS2 AC3 AB2 U7 SA_BS[0] SA_BS[1] SA_BS[2] 16 16 16 M_A_CAS# M_A_RAS# M_A_WE# AE1 AB3 AE9 SA_CAS# SA_RAS# SA_WE# SA_CK[0] SA_CK#[0] SA_CKE[0] AA6 AA7 P7 M_CLK_DDR0 16 M_CLK_DDR#0 16 M_CKE0 16 SA_CK[1] SA_CK#[1] SA_CKE[1] Y6 Y5 P6 M_CLK_DDR1 16 M_CLK_DDR#1 16 M_CKE1 16 AE2 AE8 M_CS#0 16 M_CS#1 16 AD8 AF9 M_ODT0 16 M_ODT1 16 SA_CS#[0] SA_CS#[1] SA_ODT[0] SA_ODT[1] SA_DM[0] SA_DM[1] SA_DM[2] SA_DM[3] SA_DM[4] SA_DM[5] SA_DM[6] SA_DM[7] SA_DQS#[0] SA_DQS#[1] SA_DQS#[2] SA_DQS#[3] SA_DQS#[4] SA_DQS#[5] SA_DQS#[6] SA_DQS#[7] SA_DQS[0] SA_DQS[1] SA_DQS[2] SA_DQS[3] SA_DQS[4] SA_DQS[5] SA_DQS[6] SA_DQS[7] SA_MA[0] SA_MA[1] SA_MA[2] SA_MA[3] SA_MA[4] SA_MA[5] SA_MA[6] SA_MA[7] SA_MA[8] SA_MA[9] SA_MA[10] SA_MA[11] SA_MA[12] SA_MA[13] SA_MA[14] SA_MA[15] B9 D7 H7 M7 AG6 AM7 AN10 AN13 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 M_A_DM[7:0] 16 C9 F8 J9 N9 AH7 AK9 AP11 AT13 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 M_A_DQS#[7:0] 16 C8 F9 H9 M9 AH8 AK10 AN11 AR13 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS[7:0] 16 Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15 17 M_B_DQ[63:0] M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 M_A_A[15:0] 16 B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10 17 17 17 M_B_BS0 M_B_BS1 M_B_BS2 AB1 W5 R7 17 17 17 M_B_CAS# M_B_RAS# M_B_WE# AC5 Y7 AC6 SB_DQ[0] SB_DQ[1] SB_DQ[2] SB_DQ[3] SB_DQ[4] SB_DQ[5] SB_DQ[6] SB_DQ[7] SB_DQ[8] SB_DQ[9] SB_DQ[10] SB_DQ[11] SB_DQ[12] SB_DQ[13] SB_DQ[14] SB_DQ[15] SB_DQ[16] SB_DQ[17] SB_DQ[18] SB_DQ[19] SB_DQ[20] SB_DQ[21] SB_DQ[22] SB_DQ[23] SB_DQ[24] SB_DQ[25] SB_DQ[26] SB_DQ[27] SB_DQ[28] SB_DQ[29] SB_DQ[30] SB_DQ[31] SB_DQ[32] SB_DQ[33] SB_DQ[34] SB_DQ[35] SB_DQ[36] SB_DQ[37] SB_DQ[38] SB_DQ[39] SB_DQ[40] SB_DQ[41] SB_DQ[42] SB_DQ[43] SB_DQ[44] SB_DQ[45] SB_DQ[46] SB_DQ[47] SB_DQ[48] SB_DQ[49] SB_DQ[50] SB_DQ[51] SB_DQ[52] SB_DQ[53] SB_DQ[54] SB_DQ[55] SB_DQ[56] SB_DQ[57] SB_DQ[58] SB_DQ[59] SB_DQ[60] SB_DQ[61] SB_DQ[62] SB_DQ[63] SB_CK[0] SB_CK#[0] SB_CKE[0] W8 W9 M3 M_CLK_DDR2 17 M_CLK_DDR#2 17 M_CKE2 17 SB_CK[1] SB_CK#[1] SB_CKE[1] V7 V6 M2 M_CLK_DDR3 17 M_CLK_DDR#3 17 M_CKE3 17 AB8 AD6 M_CS#2 17 M_CS#3 17 AC7 AD1 M_ODT2 17 M_ODT3 17 SB_CS#[0] SB_CS#[1] SB_ODT[0] SB_ODT[1] SB_DM[0] SB_DM[1] SB_DM[2] SB_DM[3] SB_DM[4] SB_DM[5] SB_DM[6] SB_DM[7] DDR SYSTEM MEMORY - B 16 M_A_DQ[63:0] DDR SYSTEM MEMORY A D SB_DQS#[0] SB_DQS#[1] SB_DQS#[2] SB_DQS#[3] SB_DQS#[4] SB_DQS#[5] SB_DQS#[6] SB_DQS#[7] SB_DQS[0] SB_DQS[1] SB_DQS[2] SB_DQS[3] SB_DQS[4] SB_DQS[5] SB_DQS[6] SB_DQS[7] SB_CAS# SB_RAS# SB_WE# M_B_DM[7:0] 17 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 C D5 F4 J4 L4 AH2 AL4 AR5 AR8 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 M_B_DQS#[7:0] 17 C5 E3 H4 M5 AG2 AL5 AP5 AR7 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS[7:0] 17 B SB_MA[0] SB_MA[1] SB_MA[2] SB_MA[3] SB_MA[4] SB_MA[5] SB_MA[6] SB_MA[7] SB_MA[8] SB_MA[9] SB_MA[10] SB_MA[11] SB_MA[12] SB_MA[13] SB_MA[14] SB_MA[15] SB_BS[0] SB_BS[1] SB_BS[2] D4 E1 H3 K1 AH1 AL2 AR4 AT8 D U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1 M_B_A[15:0] 17 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15 SOCKET989 A A SOCKET989 Title : CPU(2)_DDR3 ASUSTeK COMPUTER INC NB1 Size Custom Engineer: Rev K72Jr 2.0 Date: Friday, December 11, 2009 Jerry Mou Project Name Sheet of 99 U0301H U0301I U0301E 10 mil D 18 DIMM0_VREF_DQ 18 DIMM1_VREF_DQ RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 RSVD6 RSVD7 RSVD8 SA_DIMM_VREFDQ SB_DIMM_VREFDQ RSVD11 RSVD12 RSVD13 RSVD14 RSVD34 RSVD35 RSVD36 RSVD_NCTF_37 RSVD38 RSVD39 RSVD_NCTF_40 RSVD_NCTF_41 T0578 T0567 T0566 T0565 T0569 T0568 T0571 T0572 T0574 T0570 T0575 T0573 T0576 T0577 T0592 T0581 T0580 T0579 T0583 1 1 1 1 1 1 1 1 1 CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16 CFG[0] CFG[1] CFG[2] CFG[3] CFG[4] CFG[5] CFG[6] CFG[7] CFG[8] CFG[9] CFG[10] CFG[11] CFG[12] CFG[13] CFG[14] CFG[15] CFG[16] CFG[17] RSVD_TP_86 RESERVED RSVD_NCTF_42 RSVD_NCTF_43 C 1 R0501 @ 0Ohm 2 B19 A19 H_RSVD17_R H_RSVD18_R R0502 @ 0Ohm U9 T9 R1.1,item L28 T0513 T0510 A20 B20 AC9 AB9 1 C1 A3 J29 J28 T0511 T0512 1 A34 A33 T0514 T0515 1 C35 B35 RSVD45 RSVD46 RSVD47 RSVD48 RSVD49 RSVD50 RSVD51 RSVD52 RSVD53 RSVD_NCTF_54 RSVD_NCTF_55 RSVD_NCTF_56 RSVD_NCTF_57 RSVD58 RSVD_TP_59 RSVD_TP_60 KEY RSVD62 RSVD63 RSVD64 RSVD65 AH25 AK26 AL26 AR2 T0504 AJ26 AJ27 AP1 AT2 1 T0501 T0506 AT3 AR1 1 T0507 T0503 1 1 T0508 T0509 T0502 T0505 AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33 AT33 AT34 AP35 AR35 AR32 E15 F15 A2 D15 C15 AJ15 AH15 RSVD64_R RSVD65_R R1.1,item L28 RSVD17 RSVD18 RSVD21 RSVD22 RSVD_NCTF_23 RSVD_NCTF_24 RSVD26 RSVD27 RSVD_NCTF_28 RSVD_NCTF_29 RSVD_NCTF_30 RSVD_NCTF_31 R0505 @ 0Ohm 2 R0506 @ 0Ohm RSVD15 RSVD16 RSVD19 RSVD20 1 RSVD_TP_66 RSVD_TP_67 RSVD_TP_68 RSVD_TP_69 RSVD_TP_70 RSVD_TP_71 RSVD_TP_72 RSVD_TP_73 RSVD_TP_74 RSVD_TP_75 RSVD_TP_76 RSVD_TP_77 RSVD_TP_78 RSVD_TP_79 RSVD_TP_80 RSVD_TP_81 RSVD_TP_82 RSVD_TP_83 RSVD_TP_84 RSVD_TP_85 B VSS AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 AP34 AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSS29 VSS30 VSS31 VSS32 VSS33 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS40 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS54 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VSS63 VSS64 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS VSS81 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS90 VSS91 VSS92 VSS93 VSS94 VSS95 VSS96 VSS97 VSS98 VSS99 VSS100 VSS101 VSS102 VSS103 VSS104 VSS105 VSS106 VSS107 VSS108 VSS109 VSS110 VSS111 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 VSS126 VSS127 VSS128 VSS129 VSS130 VSS131 VSS132 VSS133 VSS134 VSS135 VSS136 VSS137 VSS138 VSS139 VSS140 VSS141 VSS142 VSS143 VSS144 VSS145 VSS146 VSS147 VSS148 VSS149 VSS150 VSS151 VSS152 VSS153 VSS154 VSS155 VSS156 VSS157 VSS158 VSS159 VSS160 AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30 K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9 VSS161 VSS162 VSS163 VSS164 VSS165 VSS166 VSS167 VSS168 VSS169 VSS170 VSS171 VSS172 VSS173 VSS174 VSS175 VSS176 VSS177 VSS178 VSS179 VSS180 VSS181 VSS182 VSS183 VSS184 VSS185 VSS186 VSS187 VSS188 VSS189 VSS190 VSS191 VSS192 VSS193 VSS194 VSS195 VSS196 VSS197 VSS198 VSS199 VSS200 VSS201 VSS202 VSS203 VSS204 VSS205 VSS206 VSS207 VSS208 VSS209 VSS210 VSS211 VSS212 VSS213 VSS214 VSS215 VSS216 VSS217 VSS218 VSS219 VSS220 VSS221 VSS222 VSS223 VSS224 VSS225 VSS226 VSS227 VSS228 VSS229 VSS230 VSS231 VSS232 VSS233 D VSS NCTF RSVD32 RSVD33 AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30 AJ13 AJ12 VSS_NCTF1 VSS_NCTF2 VSS_NCTF3 VSS_NCTF4 VSS_NCTF5 VSS_NCTF6 VSS_NCTF7 AT35 TP_MCP_VSS_NCTF1 AT1 TP_MCP_VSS_NCTF2 AR34 B34 B2 B1 TP_MCP_VSS_NCTF6 A35 TP_MCP_VSS_NCTF7 1 T0564 T0561 1 T0563 T0562 C B SOCKET989 SOCKET989 SOCKET989 CFG strapping information: CFG[1:0]: PCI Express Port Bifurcation:(Clarksfield Only) - 11 = x 16 PEG (Default) - 10 = x PEG Intel sighting #: 402607(3393727) CFG[3]: PCIE Static Numbering Lane Reversal.(Auburndale Only) To drive a value of zero on CFG[0] pin use a 250 Ohm pull down resistor to Vss - 1:Normal Operation (Default) - 0:Lane Numbers Reversed 15 -> 0, 14 -> 1, CFG[4]: Embedded DisplayPort Detection.(Auburndale Only) - 1:Disabled - No Physical Display Port attached to Embedded DisplayPort - 0:Enabled - An external Display Port device is connected to the Embedded Display Port CFG0 R0535 @ 3.01KOHM 1% CFG4 3.01KOHM 1% CFG7 R0537 @ 3.01KOHM 1% eDP=3.3K PD CFG[7]: Fixed for PCI Express 2.0 jitter specifications.(Clarksfield) Clarksfield (only for early samples pre-ES1) - Connect to GND with 3.01K Ohm/5% resistor A For a common motherboard design (for AUB and CFD), the pull-down resistor should be used Does not impact AUB functionality Unmount if Intel has fixed this issue CFG3 R0536 @ R0538 @ A 3.01KOHM 1% Note: (Auburndale)Hardware Straps are sampled on the asserting edge of VCCPWRGOOD_0 and VCCPWRGOOD_1 and latched inside the processor Title : CPU(3)_CFG,GND Note: (Clarksfield)Hardware Straps are sampled after RSTIN# de-assertion Unmount R0501& R0502 & R0505 & R0506 for Intel CRB sugesstion ASUSTeK COMPUTER INC NB1 Size Jerry Mou Project Name Custom Date: Engineer: Rev K72Jr 2.0 Sheet Friday, December 11, 2009 of 99 +VGFX_CORE C0655 1 C0685 C0686 AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 + CE0604 330UF/2V ESR=6mOhm/Ir=3A 2 22UF/6.3V 22UF/6.3V @ DG R1.1,P41 1xbuck Stuffing option P10 N10 L10 K10 22UF/6.3V C0626 10UF/6.3V C C0627 10UF/6.3V AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 CPU_VID0 CPU_VID1 CPU_VID2 CPU_VID3 CPU_VID4 CPU_VID5 CPU_VID6 G15 H_VTTVID1 CPU_VID[0:6] 2 22UF/6.3V C0664 22UF/6.3V +1.8VS 1UF/10V 1UF/10V C0667 2.2UF/10V C0629 C0668 4.7UF/6.3V C0628 22UF/6.3V L26 L27 M26 C0659 VCCPLL1 VCCPLL2 VCCPLL3 22UF/6.3V C0665 C0658 J22 J20 J18 H21 H20 H19 22UF/6.3V C0657 VTT1_63 VTT1_64 VTT1_65 VTT1_66 VTT1_67 VTT1_68 22UF/6.3V 1 C0656 80 PM_PSI# AN33 VTT1_48 VTT1_49 VTT1_50 VTT1_51 VTT1_52 VTT1_53 VTT1_54 VTT1_55 VTT1_56 VTT1_57 VTT1_58 K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25 1.1V +VTT_CPU POWER CPU VIDS VTT_SELECT SENSE LINES VTT0_59 VTT0_60 VTT0_61 VTT0_62 PEG & DMI VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] PROC_DPRSLPVR VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15 VDDQ16 VDDQ17 VDDQ18 +VTT_CPU 22UF/6.3V +VTT_CPU PSI# VTT1_45 VTT1_46 VTT1_47 RN0601A 4.7KOHM2 RN0601B 4.7KOHM4 R0613 1KOhm C0618 22UF/6.3V 2 22UF/6.3V 2 C0617 C0654 GFX_VRON_EN GFXVR_DPRSLPVR GVR_PWR_MON +1.5V +VTT_CPU J24 J23 H25 AR25 AT25 AM24 10UF/6.3V GFX_VR_EN GFX_DPRSLPVR GFX_IMON D C0621 C0622 C0623 C0624 C0625 C0689 GRAPHICS VIDs 10UF/6.3V AM22 AP22 AN22 AP23 AM23 AP24 AN24 1UF/10V 1UF/10V 1UF/10V 1UF/10V 1UF/10V 10UF/6.3V C0611 GFX_VID[0] GFX_VID[1] GFX_VID[2] GFX_VID[3] GFX_VID[4] GFX_VID[5] GFX_VID[6] C0688 AR22 AT22 - 1.5V RAILS 10UF/6.3V 10UF/6.3V 2 C0687 C0608 10UF/6.3V @ 10UF/6.3V C0616 C0606 10UF/6.3V @ 10UF/6.3V C0615 C0604 10UF/6.3V 10UF/6.3V C0613 C0602 1 10UF/6.3V C0601 2 AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15 VTT0_33 VTT0_34 VTT0_35 VTT0_36 VTT0_37 VTT0_38 VTT0_39 VTT0_40 VTT0_41 VTT0_42 VTT0_43 VTT0_44 T0601 VAXG_SENSE VSSAXG_SENSE 1.8V 1.1V RAIL POWER VTT0_1 VTT0_2 VTT0_3 VTT0_4 VTT0_5 VTT0_6 VTT0_7 VTT0_8 VTT0_9 VTT0_10 VTT0_11 VTT0_12 VTT0_13 VTT0_14 VTT0_15 VTT0_16 VTT0_17 VTT0_18 VTT0_19 VTT0_20 VTT0_21 VTT0_22 VTT0_23 VTT0_24 VTT0_25 VTT0_26 VTT0_27 VTT0_28 VTT0_29 VTT0_30 VTT0_31 VTT0_32 +VTT_CPU CPU CORE SUPPLY C0666 22UF/6.3V 19 SOCKET989 B PM_DPRSLPVR T0633 80 Processor Decoupling +VCORE VCCSENSE 80 VSSSENSE 80 22UF/6.3V C0644 C0645 22UF/6.3V 22UF/6.3V C0643 22UF/6.3V 1 C0642 22UF/6.3V C0641 22UF/6.3V C0640 22UF/6.3V C0639 22UF/6.3V C0638 22UF/6.3V C0637 22UF/6.3V C0636 22UF/6.3V C0635 22UF/6.3V C0634 22UF/6.3V C0633 2 22UF/6.3V C0647 22UF/6.3V +VCORE 10UF/6.3V C0682 10UF/6.3V 1 C0681 C0683 10UF/6.3V 10UF/6.3V C0680 10UF/6.3V C0679 10UF/6.3V C0678 10UF/6.3V C0677 10UF/6.3V C0676 10UF/6.3V C0675 10UF/6.3V C0674 10UF/6.3V C0673 10UF/6.3V C0672 10UF/6.3V C0671 10UF/6.3V C0670 10UF/6.3V C0669 T0631 R0603 100Ohm 1% 1 VTT_SENSE TP_VSS_SENSE_VTT B15 A15 C0632 VCCSENSE_R VSSSENSE_R T0632 VTT_SENSE VSS_SENSE_VTT R0602 100Ohm 1% 80 AJ34 AJ35 I_MON VCC_SENSE VSS_SENSE AN35 ISENSE 1 +VCORE SENSE LINES B VCC1 VCC2 VCC3 VCC4 VCC5 VCC6 VCC7 VCC8 VCC9 VCC10 VCC11 VCC12 VCC13 VCC14 VCC15 VCC16 VCC17 VCC18 VCC19 VCC20 VCC21 VCC22 VCC23 VCC24 VCC25 VCC26 VCC27 VCC28 VCC29 VCC30 VCC31 VCC32 VCC33 VCC34 VCC35 VCC36 VCC37 VCC38 VCC39 VCC40 VCC41 VCC42 VCC43 VCC44 VCC45 VCC46 VCC47 VCC48 VCC49 VCC50 VCC51 VCC52 VCC53 VCC54 VCC55 VCC56 VCC57 VCC58 VCC59 VCC60 VCC61 VCC62 VCC63 VCC64 VCC65 VCC66 VCC67 VCC68 VCC69 VCC70 VCC71 VCC72 VCC73 VCC74 VCC75 VCC76 VCC77 VCC78 VCC79 VCC80 VCC81 VCC82 VCC83 VCC84 VCC85 VCC86 VCC87 VCC88 VCC89 VCC90 VCC91 VCC92 VCC93 VCC94 VCC95 VCC96 VCC97 VCC98 VCC99 VCC100 AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 FDI C +VTT_CPU AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26 VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36 GRAPHICS D AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16 DDR3 +VCORE U0301G 0805 POWER SL0601 U0301F C0684 10UF/6.3V A A Decoupling guide from Intel Schematic R0.9: SOCKET989 Schematic Checklist R0.7: VCORE 22uF * 16pcs VCORE 22uF * 12pcs 10uF * 16pcs 10uF * 16pcs 470uF* 6pcs(2 no stuff) Title : CPU(4)_PWR ASUSTeK COMPUTER INC NB1 470uF* 6pcs(2 no stuff) Size Custom Date: Engineer: Jerry Mou Project Name Rev K72Jr Friday, December 11, 2009 2.0 Sheet of 99 D D CPU XDP connector +VTT_CPU J0701 31 C 32 SIDE1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SIDE2 30 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 1 R0709 T0720 T0721 0Ohm /XDP CPUPWRGD_XDP R0708 HBPM3# HBPM2# HBPM1# HBPM0# XDP_RST#_R 1KOhm T0716 T0717 T0718 T0719 1 1 R0707 1KOhm /XDP H_PWRGD_XDP (45) XDP_TRST# H_CPUPWRGD (54) (39) 3,25 /XDP XDP_PREQ# XDP_PRDY# ( 3) ( 5) XDP_TDO XDP_TDI (52) (56) XDP_TMS XDP_TCLK (58) (57) XDP_DBRESET# 3,22,67 H_CPURST# (48) (46) SMB_DAT_S 16,17,19,28,29,67 SMB_CLK_S 16,17,19,28,29,67 FPC_CON_30P B R0715 0Ohm /XDP 1 1 1 1 XDP_OBS0 XDP_OBS1 XDP_OBS2 XDP_OBS3 XDP_OBS4 XDP_OBS5 XDP_OBS6 XDP_OBS7 T0730 PM_PWRBTN#_R 22 3 3 3 3 C FFC J0701 path Put these test point near J0701 (42) (40) CLK_ITP_BCLK# CLK_ITP_BCLK T0722 T0723 T0724 T0725 T0726 T0727 T0728 T0729 Put it away from the FFC path (44) +VTT_CPU B BUF_PLT_RST# 3,24,30,32,33,53,64,67,70 /XDP A A Title : CPU(5)_XDP ASUSTeK COMPUTER INC NB1 Size Custom Jerry Mou Project Name Rev K72Jr Date: Friday, December 11, 2009 Engineer: 2.0 Sheet of 99 D D C C B B A A Title : ASUSTeK COMPUTER INC NB1 Size NB_**** Ryan_Wang Project Name Custom Date: Engineer: Rev K72Jr 1.0 Friday, December 11, 2009 Sheet of 99 Main Board D D C C B B A A Title : NB_**** ASUSTeK COMPUTER INC NB1 Size Ryan_Wang Project Name Custom Date: Engineer: Rev K72Jr 1.0 Friday, December 11, 2009 Sheet of 99 Main Board D D C C B B A A Title : NB_**** ASUSTeK COMPUTER INC NB1 Size Ryan_Wang Project Name Custom Date: Engineer: Rev K72Jr 1.0 Friday, December 11, 2009 Sheet 10 of 99 IMVP6.5 CPU VCORE REGULATOR C8006 10UF/25V c1206_h75 2 C8004 1000PF/50V c0603 G 1 P_VCORE_SNB1_20 P_VCORE_BST1+_20 Icpu(max)