Aspire timeline 4810 5810 JM41 UMA WISTRON JM41 UMA

http://hobi-elektronika.net JM41 Block Diagram Intel CPU D CLK GEN Project code: 91.4CQ01.001 PCB P/N : 48.4CQ01.011 REVISION : 08266-1 SYSTEM DC/DC 36 TPS51125 INPUTS OUTPUTS 5V_S5(6A) 3D3V_S5(5A) DCBATOUT 5V_AUX_S5 PCB STACKUP 3D3V_AUX_S5 Thermal Sensor TOP L1 S L2 32 EMC2103 VCC/GND L3 S L4 VCC/GND L5 GND/VCC L6 D 37 RT8202 SMSC Penryn SFF ICS9LPRS365B INPUTS OUTPUTS DCBATOUT 1D05V_S0(10A) 4,5,6 HOST BUS DDR3 667/800/1066MHz@1.05V LVDS Cantiga-GS SFF 800/1066 17,18 MHz RGB CRT DDR Memory I/F DDR3 C LCD L7 L8 OUTPUTS DCBATOUT 1D5V_S3(11A) CRT 20 INTEGRATED GRAHPICS PCIex16 HDMI 7,8,9,10,11,12 X4 DMI 400MHz INPUTS 21 OUTPUTS DDR_VREF_S3 (1.2A) 5V_S5 C-Link0 Int MIC CHARGER MAX8731A ICH9M SFF 29 PCIe LAN Giga LAN PCIe ports Line Out PCI/PCI BRIDGE Codec 29 Realtek ALC269Q 28 MIC In B 39 RT9026 C LVDS, CRT I/F 800/1066 17,18 MHz S BOTTOM 19 AGTL+ CPU I/F 38 RT8202 INPUTS ACPI 2.0 AZALIA INPUTS 27 Mini Card 31 WLAN 12 USB 2.0/1.1 ports ETHERNET (10/100/1000MbE) High Definition Audio RJ45 27 INPUTS Matrix Storage Technology(DO) DCBATOUT LPC BUS SATA 22 SATA USB Port ODD SATA A KBC WPCE773LA0DG 33 25 23 SATA SSD SATA 22 Touch Pad 35 Cardreader RTS5159 SPI BIOS Winbond Camera 24 30 INT KB 33 (2MB) 34 INPUTS LPC DEBUG CONN MEDIA KEY 36 VCC_GFXCORE (7A) Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title MS/MS Pro/xD /MMC/SD BLOCK DIAGRAM Size Custom 30 40 OUTPUTS DCBATOUT Document Number Date: Monday, March 09, 2009 0~1.3V 64A VGA USB Mini USB Blue Tooth B VCC_CORE ISL6263A 13,14,15,16 HDD SATA 35 OUTPUTS Active Managemnet Technology(DO) 1.5W 6.0A CPU DC/DC Mini Card 31 3G Serial Peripheral I/F INT.SPKR CHG_PWR 18V ADP3207A USB LPC I/F 29 OUTPUTS DCBATOUT PCIe SATA 29 TXFM Atheros AR8131 26 41 Rev -1 JM41_UMA Sheet 1 of 40 A A B ICH9M Functional Strap Definitions ICH9 EDS 642879 Rev.1.5 ICH9M Integrated Pull-up http://hobi-elektronika.net and Pull-down Resistors Usage/When Sampled HDA_SDOUT XOR Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROK Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h) This signal has weak internal pull-down CL_CLK[1:0] PULL-UP 20K CL_DATA[1:0] PULL-UP 20K HDA_SYNC PCIE config1 bit0, Rising Edge of PWROK This signal has a weak internal pull-down Sets bit0 of RPC.PC(Config Registers:Offset 224h) CL_RST0# PULL-UP 20K GNT2#/ GPIO53 PCIE config2 bit2, Rising Edge of PWROK DPRSLPVR/GPIO16 PULL-DOWN 20K ENERGY_DETECT PULL-UP 20K GPIO20 Reserved This signal has a weak internal pull-up Sets bit2 of RPC.PC2(Config Registers:Offset 0224h) This signal should not be pulled high HDA_BIT_CLK PULL-DOWN 20K GNT1#/ GPIO51 ESI Strap (Server Only) Rising Edge of PWROK HDA_DOCK_EN#/GPIO33 PULL-UP 20K HDA_RST# PULL-DOWN 20K HDA_SDIN[3:0] PULL-DOWN 20K HDA_SDOUT PULL-DOWN 20K GNT0#: SPI_CS1#/ GPIO58 SPI_MOSI GPIO49 SATALED# SPKR TP3 GPIO33/ HDA_DOCK _EN# page 92 Signal GNT3#/ GPIO55 C Top-Block Swap Override Rising Edge of PWROK Comment ESI compatible mode is for server platforms only This signal should not be pulled low for desttop and mobile Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space) Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down ICH9 EDS 642879 SIGNAL GNT[3:0]#/GPIO[55,53,51] PULL-UP 20K GPIO[20] PULL-DOWN 20K Integrated TPM Enable, Rising Edge of CLPWROK Sample low: the Integrated TPM will be disabled Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable GPIO[49] PULL-UP 20K LDA[3:0]#/FHW[3:0]# PULL-UP 20K LAN_RXD[2:0] PULL-UP 20K LDRQ[0] PULL-UP 20K LDRQ[1]/GPIO23 PULL-UP 20K PME# PULL-UP 20K PWRBTN# PULL-UP 20K XOR Chain Entrance Rising Edge of PWROK Flash Descriptor Security Override Strap Rising Edge of PWROK Signal has weak internal pull-up Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8) SATALED# PULL-UP 15K If sampled high, the system is strapped to the "No Reboot" mode(ICH9 will disable the TCO Timer system reboot feature) The status is readable via the NO REBOOT bit SPI_CS1#/GPIO58/CLGPIO6 PULL-UP 20K SPI_MOSI PULL-DOWN 20K SPI_MISO PULL-UP 20K This signal should not be pull low unless using XOR Chain testing SPKR PULL-DOWN 20K TACH_[3:0] PULL-UP 20K TP[3] PULL-UP 20K USB[11:0][P,N] PULL-DOWN 15K Sampled low:the Flash Descriptor Security will be overridden If high,the security measures will be in effect.This should only be enabled in manufacturing environments using an external pull-up resister page 218 Pin Name CFG[2:0] CFG[4:3] CFG8 CFG[15:14] CFG[18:17] Strap Description FSB Frequency Select 0.5 Configuration 000 = FSB1067 011 = FSB667 010 = FSB800 others = Reserved Reserved CFG5 DMI x2 Select CFG6 iTPM Host Interface = DMI x2 = DMI x4 (Default) 0= The iTPM Host Interface is enabled(Note2) 1=The iTPM Host Interface is disalbed(default) = Transport Layer Security (TLS) cipher suite with no confidentiality = TLS cipher suite with confidentiality (default) CFG7 Intel Management engine Crypto strap CFG9 PCIE Graphics Lane = Reverse Lanes,15->0,14->1 ect 1= Normal operation(Default):Lane Numbered in order CFG10 PCIE Loopback enable = Enable (Note 3) 1= Disabled (default) PULL-DOWN 20K Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10) GNT0# is MSB, 01-SPI, 10-PCI, 11-LPC PCI Express Lane Reversal Rising Edge of PWROK No Reboot Rising Edge of PWROK Montevina Platform Design guide 22339 The pull-up or pull-down active when configured for native GLAN_DOCK# functionality and determined by LAN controller Boot BIOS Destination Selection 0:1 Rising Edge of PWROK DMI Termination Voltage, The signal is required to be low for desktop Rising Edge of PWROK applications and required to be high for mobile applications E Rev.1.5 Resistor Type/Value HDA_SYNC GLAN_DOCK# D Cantiga chipset and ICH9M I/O controller Hub strapping configuration CFG[13:12] CFG16 CFG19 00 10 01 11 XOR/ALL = = = = Reserve XOR mode Enabled ALLZ mode Enabled (Note 3) Disabled (default) FSB Dynamic ODT = Dynamic ODT Disabled = Dynamic ODT Enabled (Default) DMI Lane Reversal = Normal operation(Default): Lane Numbered in Order = Reverse Lanes DMI x4 mode[MCH -> ICH]:(3->0,2->1,1->2and0->3) DMI x2 mode[MCH -> ICH]:(3->0,2->1) CFG20 Digital Display Port (SDVO/DP/iHDMI) Concurrent with PCIe = Only Digital Display Port or PCIE is operational (Default) =Digital display Port and PCIe are operting simulataneously via the PEG port =No SDVO Card Present (Default) SDVO_CTRLDATA SDVO Present = SDVO Card Present = LFP Disabled (Default) L_DDC_DATA Local Flat Panel (LFP) Present 1= LFP Card Present; PCIE disabled NOTE: All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal iTPM can be disabled by a 'Soft-Strap' option in the Flash-decriptor section of the Firmware This 'Soft-Strap' is activated only after enabling iTPM via CFG6 Only one of the CFG10/CFG/12/CFG13 straps can be enabled at any time Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Reference Size A3 Document Number Date: Sunday, March 01, 2009 Rev -1 JM41_UMA Sheet of 40 A B C D E 1D05V_S0 3D3V_S0 3D3V_S0 2 2 2 2 2 C418 SCD1U16V2KX-3GP SCD1U16V2KX-3GP 3D3V_CLK_S0 3D3V_CLK_S0 C411 C417 SCD1U16V2KX-3GP C226 SC4D7U10V5ZY-3GP C412 SCD1U16V2KX-3GP C397 SCD1U16V2KX-3GP SCD1U16V2KX-3GP SCD1U16V2KX-3GP SC4D7U6D3V3KX-GP SC1U10V3KX-3GP 3D3V_48MPWR_S0 C407 C420 C405 1D05V_CLK_S0 C401 C394 SCD1U16V2KX-3GP R195 0R0603-PAD R61 0R0603-PAD 1D05V_CLK_S0 SC10P50V2JN-4GP GEN_XTAL_IN GEN_XTAL_OUT C416 X2 X-14D31818M-50GP PCLKCLK4 82.30005.A51 33R2J-2-GP 1CLK_48 R203 17 4,8 23 19 27 CLK_MCH_BCLK CLK_MCH_BCLK# NB CLK_PCIE_ICH 14 CLK_PCIE_ICH# 14 SB DMI CLK_PCIE_MINI1 25 CLK_PCIE_MINI1# 25 Wireless CR#_E CPU_SEL0 14 PM_STPPCI# 14 PM_STPCPU# 3D3V_S0 PCLKCLK2 PCLKCLK5 10KR2J-3-GP DY R200 10 11 12 13 14 PCLKCLK2 PCLK_FWH PCLKCLK4 PCLKCLK5 DY EC48 SC22P50V2JN-4GP PCLK_ICH 4,8 4,8 14 CPU_SEL1 CPU_SEL2 CLK_ICH14 R205 R2062 10KR2J-3-GP CPU_SEL2_R PCI0/CR#_A PCI1/CR#_B PCI2/TME PCI3 PCI4/27_SELECT PCI_F5/ITP_EN EC47 GND48 GNDPCI GNDREF DY SC22P50V2JN-4GP ICS9LPRS365BKLFT-GP-U EMI capacitor for Antenna team suggestion 71.09365.A03 SB SATA SRCT2/SATAT SRCC2/SATAC 28 29 CLK_PCIE_SATA 13 CLK_PCIE_SATA# 13 27MHZ_NONSS/SRCT1/SE1 27MHZ_SS/SRCC1/SE2 24 25 DREFSSCLK DREFSSCLK# SRCT0/DOTT_96 SRCC0/DOTC_96 20 21 DREFCLK DREFCLK# 3D3V_S0 RN23 SRN10KJ-6-GP 3RD = 71.00875.C03 PCI0/CR#_A Byte 5, bit = PCI0 enabled (default) 1= CR#_A enabled Byte 5, bit controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair PCI1/CR#_B Byte 5, bit = PCI1 enabled (default) 1= CR#_B enabled Byte 5, bit controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair PCI2/TME = Overclocking of CPU and SRC Allowed = Overclocking of CPU and SRC NOT allowed PCI3 PCI4/27M_SEL = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as DOT96, Pin14 as DOT96# = Pin17 as 27MHz, Pin 18 as 27MHz_SS, Pin13 as SRC-0, Pin14 as SRC-0# PCI_F5/ITP_EN =SRC8/SRC8# = ITP/ITP# SRCT3/CR#_C Byte 5, bit = SRC3 enabled (default) 1= CR#_C enabled Byte 5, bit controls whether CR#_C controls SRC0 or SRC2 pair Byte 5, bit = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pair 14 25 25 CR#_D CR#_C CR#_H CR#_E CLK_MCH_OE# SATACLKREQ# LAN_CLKREQ# WLAN_CLKREQ# PIN NAME DESCRIPTION SRCC3/CR#_D Byte 5, bit = SRC3 enabled (default) 1= CR#_D enabled Byte 5, bit controls whether CR#_D controls SRC1 or SRC4 pair Byte 5, bit 0 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pair SRCC7/CR#_E Byte 6, bit = SRC7# enabled (default) 1= CR#_F controls SRC6 SRCT7/CR#_F Byte 6, bit = SRC7 enabled (default) 1= CR#_F controls SRC8 SRCC11/CR#_G Byte 6, bit = SRC11# enabled (default) 1= CR#_G controls SRC9 SRCT11/CR#_H Byte 6, bit = SRC11 enabled (default) 1= CR#_H controls SRC10 SEL2 SEL1 SEL0 FSC FSB FSA 0 0 0 1 B C 1 0 CPU FSB 100M 133M 166M 200M 266M X 533M 667M 800M 1067M Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Clock Generator Size Document Number Rev JM41_UMA Date: Thursday, March 05, 2009 A NB CLK SRCT3/CR#_C SRCC3/CR#_D 2nd = 71.08513.003 ICS9LPRS365YGLFT setting table PIN NAME DESCRIPTION CLK_MCH_3GPLL CLK_MCH_3GPLL# CR#_C CR#_D 31 32 REF0/FSLC/TEST_SEL 33R2J-2-GP PCLK_KBC CLK48_ICH CR#_H CLK_ICH14 29 LAN 14 CLK_PWRGD GND PCLKCLK4 PCLKCLK5 PCLK_KBC PCLK_ICH SCLK SDATA 26 3D3V_S0 SB_20090205 28 14 16,17,18 SMBC_ICH 16,17,18 SMBD_ICH CLK_PCIE_LAN 25 CLK_PCIE_LAN# 25 GND GNDSRC 22 30 RN30 SRN10KJ-5-GP CPU USB_48MHZ/FSLA 18 15 CLK48_ICH X1 X2 CLK_CPU_BCLK CLK_CPU_BCLK# R207 10KR2J-3-GP 14 VDD96_IO VDDPLL3_IO CL=20pF±0.2pF VDDPLL3 VDDREF VDD48 VDDPCI U27 16 3D3V_48MPWR_S0 D Sheet E -1 of 40 ... Design> Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Reference Size A3 Document Number Date: Sunday, March 01, 2009 Rev -1 JM41_ UMA Sheet... 800M 1067M Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Clock Generator Size Document Number Rev JM41_ UMA Date: Thursday, March