Aspire 5560 wistron grada d AG1 pdf

A B C D Garda-D Block Diagram (Discrete) Mobile CPU CLK GEN IDT CV125PA (ICS 954206) 19 DDR2 533 MHz Calistoga 11,12 Ver.:A3 :71.945PM.A0U / QK58 533/667MHz 6,7,8,9,10 ALC883 Line Out (SPDIF) 29 29 INT.SPKR MODEM MDC Card 15,16,17,18 LPC BUS TPS51100 1D8V_S3 3D3V_S0 PWR SW TPS223130 PATA New card30 CARDBUS 1394 CardReader 1394 CONN 1D8V_S3 26 MAX8725 CHG_PWR DCBATOUT 26 26 ISL6262 BCM5787MKFBG-A1 BCM5789KFBG-C1 BCM4401EKFBG-B0 Giga LAN BCM5789/5787M INPUTS DCBATOUT 21 HDD 20 CDROM 18 100mA 38,39 OUTPUTS 0~1.3V 44A ATI M54 DC/DC 34 FAN5234 KBC Renesas RE144B LPC 31 Touch Pad 33 INT KB 33 52 INPUTS OUTPUTS DCBATOUT VGA_CORE_S0 DEBUG 34 CONN APL5331KAC 1D8V_S0 FIR 32 VCC_CORE_S0 35 SST25LF080A 32 MINI USB Blue-tooth 4.0A UP+5V CPU DC/DC RJ45 23 BIOS NS87381 PORT 21 18V 5V Mini Card*1 802.11A/B/G 42 OUTPUTS 30 23 MAXIM CHARGER MS/MS Pro/xD/ MMC/SD/SDIO in 43 1D5V_S0 INPUTS TXFM 10/100 BCM4401-E 22 SIO USB 43 2D5V_S0 APL5912-U 21 PCI Express 43 DDR_VREF_S0 APL5332KAC Support TypeII 27 TSP2220A 27 LAN SPI I/F SATA RJ11 PWR SW 802.11A/B/G PCIEx1 1D8V_S3 S PCMCIA SLOT Mini-PCI G1421B 29 1D05V_S0 BOTTOM ICH7M OP AMP 41 OUTPUTS DCBATOUT GND 24,25 Ver : B0, 71.ICH7M.A0U / QK65 KI.80101.017 TPS51124 INPUTS S PCMCIA I/F PCI BUS SYSTEM DC/DC VCC 14 45,46,47,48,49 TI PCI 7412 INT.MIC CRT 3D3V_S5 S VRAM x4 50,51 28 5V_S5 GND 14"WSXGA+ LCD 13 RGB CRT ATI M54P / M52P 14 40 OUTPUTS DCBATOUT TOP 128/256M AZALIA MIC In M56 Ver.: B24 M52 Ver.: A12 M54 Ver.: A12 100MHz DMI I/F Codec 29 PCI Express x16 11,12 Line In 29 LVDS 533/667MHz DDR2 533 MHz 400/533/667MHz INPUTS PCB STACKUP TVO HOST BUS TPS51120 Project code: 91.4A901.001 PCB P/N : 55.4A901.XXX REVISION : 05217-1 (Hannstar, ACCL) -1M-0111 G792 Yonah 478 1.83G/2G/2.16G 4, E SYSTEM DC/DC 43 1D2V_S0 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 BLOCK DIAGRAM Document Number Rev AG1 Date: Wednesday, January 11, 2006 -1M Sheet of 53 A B ICH7M Integrated Pull-up and Pull-down Resistors ICH7-M EDS 17837 C 1.5V1 EE_DIN, EE_DOUT, GNT[3:0], GPIO[25], GNT[4]#/GPIO48, GNT[5]#/GPO17, PME#, ICH7 internal 20K pull-ups SS2 bit6 SS1 bit5 SS0 bit4 0 -0.50 Down FSB Frequency Select -1.00 Down -1.50 Down CFG[4:3] Reserved PWRBTN#, TP[3] 0 1 -2.00 Down CFG5 DMI x2 Select 0 -0.75 Down CFG6 Reserved 1 -1.25 Down CFG7 1 -1.75 Down 1 -2.25 Down ICH7 internal 11.5K pull-downs ACZ_BIT_CLK, ACZ_RST#, ACZ_SDIN[2:0], ICH7 internal 20K pull-downs USB[7:0][P,N] ICH7 internal 15K pull-downs SATALED# ICH7 internal 15K pull-up LAN_CLK ICH7 internal 100K pull-down ICH7M IDE Integrated Series Termination Resistors DD[15:0], DIOW#, DIOR#, DREQ, DDACK#, IORDY, DA[2:0], DCS1#, 0 +-0.25 Center 0 +-0.5 Center 1 +-0.75 Center 1 +-1.0 Center 1 0 +-0.25 Center 1 +-0.5 Center 1 +-0.75 Center 1 1 +-1.0 Center PCI Routing approximately 33 ohm ICH7M Functional Strap Definitions Signal ACZ_SDOUT page 16 Comment Usage/When Sampled XOR Chain Entrance/ PCIE Port Config bit1, Rising Edge of PWROK Allows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers: offset 224h) ACZ_SYNC PCIE bit0, Rising Edge of PWROK Sets bit0 of RPC.PC(Config Registers:Offset 224h) EE_CS Reserved This signal should not be pull high EE_DOUT Reserved This signal should not be pull low GNT2# Reserved This signal should not be pull low GNT3# Top-Block Swap Override Rising Edge of PWROK Sampled low:Top-Block Swap mode(inverts A16 for all cycles targeting FWH BIOS space) Note: Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down GNT5#/ GPIO17#, GNT4#/ GPIO48 Boot BIOS Destination Selection Rising Edge of PWROK Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10) GNT5# is MSB, 01-SPI, 10-PCI, 11-LPC DPRSLPVR Reserved This signal should not be pull high GPIO25 Reserved Rising Edge of RSMRST# This signal should not be pull low INTVRMEN Integrated VccSus1_05 VRM Enable/Disable Always sampled Reserved Requires an external pull-up resistor REQ[4:1]# XOR Chain Selection Rising Edge of PWROK TBD, Chapter SATALED# Reserved This signal should not be pull low SPKR No Reboot Rising Edge of PWROK If sampled high, the system is strapped to the "No Reboot" mode(ICH7 will disable the TCO Timer system reboot feature) The status is readable via the NO REBOOT bit LINKALERT# TP3 XOR Chain Entrance Rising Edge of PWROK CFG8 CFG9 CFG[11:10] page 16 7412 22 MiniPCI 21 INT -> PIRQ A->G, B->B, C->F, D->G A/C -> E B/D -> E LAN 23 A -> H IDSEL DCS3#, IDEIRQ Strap Description CFG[2:0] DD[7], DDREQ REQ/GNT Configuration Pin Name EE_CS,SPI_ARB, SPI_CLK, SPKR, page Spread Amount% Calistoga Strapping Signals and EDS 17050 0.71 Configuration page ACZ_SDOUT, ACZ_SYNC, DPRSLPVR/GPIO16, SS3 Byte9 bit E LDRQ[0], LDRQ[1]/GPIO[41], LAD[3:0]#/FHW[3:0]#, LAN_RXD[2:0] D 954305D 27Mhz/LCDCLK Spread and Frequency Selection Table = DMI x2 = DMI x4 (Default) = Reserved =Mobile CPU(Default) CPU Strap Reserved PCI Express Graphics Lane Reversal = Reverse Lanes,15->0,14->1 ect 1= Normal operation(Default):Lane Numbered in order Reserved CFG[13:12] XOR/ALL Z test straps CFG[15:14] Reserved CFG16 FSB Dynamic ODT = Dynamic ODT Disabled = Dynamic ODT Enabled (Default) CFG17 Global R-comp Disable (All R-comps) = All R-comp Disable = Normal Operation (Default) CFG18 VCC Select = 1.05V (Default) = 1.5V CFG19 DMI Lane Reversal = Normal operation (Default):lane Numbered in order =Reverse Lane,4->0,3->1 ect 00 = Reserved 01 = XOR mode enabled 10 = All Z mode enabled 11 = Normal Operation (Default) Reserved 001 = FSB533 011 = FSB667 others = Reserved CFG20 SDVO/PCIE Concurrent SDVOCRTL _DATA SDVO Present = Only SDVO or PCIE x1 is operational (Default) =SDVO and PCIE x1 are operating simultaneously via the PEG port = No SDVO Card present (Default) 1= SDVO Card present NOTE: All strap signals are sampled with respect to the leading edge of the Calistoga GMCH PWORK in signal History Enables integrated VccSus1_05 VRM when sampled high This signal should not be pull low unless using XOR Chain testing Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 Reference Document Number Date: Tuesday, January 10, 2006 Rev AG1 SD Sheet of 53 A B C D E 3D3V_S0 1 1 R155 0R0603-PAD 2 2 C257 C254 C230 C255 C303 C258 C508 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP C226 SC4D7U10V5ZY-3GP 1 C301 SC1U6D3V2ZY-GP C229 SC1U6D3V2ZY-GP 3D3V_CLKGEN_S0 C228 SCD1U16V2ZY-2GP 3D3V_48MPWR_S0 R213 0R0603-PAD 3D3V_CLKPLL_S0 R158 0R0603-PAD 2 3D3V_S0 3D3V_S0 3D3V_S0 U24 R598 10KR2J-3-GP 31 22 25 32 34 30 16 SS_SEL H/L: 100/96MHz R597 10KR2J-3-GP 1 2 1 16 PM_STPPCI# DY R173 R176 R179 R209 R214 R210 R211 PCLK_KBC PCLK_LAN PCLK_PCM PCLK_SIO PCLK_FWH PCLK_MINI CLK_ICHPCI PCLK_FWH & PCLK_PCM need equal length MINI 2 2 33R2J-2-GP PCLKCLK0 33R2J-2-GP PCLKCLK1 22R2J-2-GP PCLKCLK2 33R2J-2-GP PCLKCLK3 22R2J-2-GP 33R2J-2-GP SS_SEL 33R2J-2-GP ITP_EN R174 10KR2J-3-GP H/L : CPU_ITP/SRC7 56 55 46 47 11,18 SMBC_ICH 11,18 SMBD_ICH 14 15 C225 GEN_XTAL_IN 2 GEN_XTAL_OUT_R SC20P50V2JN-1GP X2 32 X-14D31818M-31GP16 82.30005.831 C256 CLK14_SIO CLK_ICH14 50 GEN_XTAL_OUT 49 R154 470R2J-2-GP R177 22R2J-2-GP R181 22R2J-2-GP GEN_REF 52 475R2F-L1-GP R157 1GEN_IREF 39 3D3V_S0 SC20P50V2JN-1GP R212 10KR2J-3-GP 38 CLK_EN# DY 10 PCI0 PCI1 PCI2 PCI3 PCIF1/SEL100/96# PCIF0/ITP_EN PCI_STOP# SCL SDA DOT96 DOT96# XTAL_IN XTAL_OUT REF IREF VTT_PWRGD#/PD SRN33J-5-GP-U CLK_MCH_3GPLL CLK_MCH_3GPLL# RN21 SRN33J-5-GP-U CLK_PCIE_ICH 16 CLK_PCIE_ICH# 16 RN40 SRN33J-5-GP-U GIGA CLK_PCIE_LAN 35 CLK_PCIE_LAN# 35 SATA SRN33J-5-GP-U CLK_PCIE_SATA 15 CLK_PCIE_SATA# 15 CLK_PCIE_NEW 30 CLK_PCIE_NEW# 30 SRC1 SRC1# SRC2 SRC2# SRC3 SRC3# SRC4 SRC4# SRC5 SRC5# SRC6 SRC6# 19 20 22 23 24 25 26 27 31 30 33 32 CLK_MCH_3GPLL_1 CLK_MCH_3GPLL_1# CLK_PCIE_ICH_1 CLK_PCIE_ICH_1# CLK_PCIE_LAN_1 CLK_PCIE_LAN_1# CLK_PCIE_SATA_1 CLK_PCIE_SATA_1# CLK_PCIE_NEW_1 CLK_PCIE_NEW_1# CLK_PCIE_MINI1_1 CLK_PCIE_MINI1_1# CPU2_ITP/SRC7 CPU2_ITP#/SRC7# 36 35 CLK_PCIE_PEG_1 CLK_PCIE_PEG_1# RN28 CPU0 CPU0# CPU1 CPU1# 44 43 41 40 CLK_CPU_BCLK_1 CLK_CPU_BCLK_1# RN17 RN19 CPU_STOP# FSC/TEST_SEL FSB/TEST_MODE USB48/FSA 54 53 16 12 VSS_PCI VSS_PCI VDD_SRC VDD_SRC 34 21 51 45 38 13 29 VSS_REF VSS_CPU VSSA VSS48 VSS_SRC VDD_PCI VDD_PCI VDD_REF VDD_CPU VDDA VDD48 VDD_SRC 48 42 37 11 28 IDTCV125PAG-GP LVDS LVDS# RN35 17 18 RN25 CLK_MCH_BCLK_1 CLK_MCH_BCLK_1# RN29 NEW SRN33J-5-GP-U RN27 MINIC SRN33J-5-GP-U CLK_PCIE_MINI1 26 CLK_PCIE_MINI1# 26 VGA SRN33J-5-GP-U CLK_PCIE_PEG 45 CLK_PCIE_PEG# 45 SRN33J-5-GP-U CLK_CPU_BCLK CLK_CPU_BCLK# 4 SRN33J-5-GP-U CLK_MCH_BCLK CLK_MCH_BCLK# PM_STPCPU# 16 CPU_SEL2 CPU_SEL1 CLK48 22R2J-2-GP R601 22R2J-2-GP R600 R602 3D3V_CLKGEN_S0 2K2R2J-2-GP Dummy when use UMA CPU_SEL2 4,7 CPU_SEL1 4,7 CLK48_ICH 16 CLK48_CARDBUS CPU_SEL0 4,7 25 3D3V_CLKPLL_S0 3D3V_48MPWR_S0 71.00125.A0W EMI capacitor CLK_PCIE_MINI1 CLK_PCIE_MINI1# PCLK_MINI SEL2 SEL1 SEL0 CPU FSB 0 0 1 1 0 1 0 1 1 1 266M 133M 200M 166M 333M 100M 400M Reserved X 533M X 667M X X X X RN34 CLK_PCIE_MINI1 CLK_PCIE_MINI1# MINIC SRN49D9F-GP RN42 CLK_PCIE_LAN CLK_PCIE_LAN# GIGA SRN49D9F-GP RN32 CLK_PCIE_SATA CLK_PCIE_SATA# SATA SRN49D9F-GP RN20 CLK_PCIE_ICH CLK_PCIE_ICH# SRN49D9F-GP RN30 CLK_PCIE_NEW CLK_PCIE_NEW# NEW SRN49D9F-GP CLK_ICH14 CLK_CPU_BCLK CLK_CPU_BCLK# SRN49D9F-GP CLK_MCH_BCLK CLK_MCH_BCLK# SRN49D9F-GP RN18 CLK48_ICH RN16 RN31 CLK_PCIE_PEG CLK_PCIE_PEG# VGA SRN49D9F-GP RN36 CLK_MCH_3GPLL CLK_MCH_3GPLL# SRN49D9F-GP CLK_ICHPCI 4 EC20 EC18 EC19 DY SC22P50V2JN-4GP DY SC22P50V2JN-4GP DY SC22P50V2JN-4GP EC17 EC21 EC34 DY SC22P50V2JN-4GP DY SC22P50V2JN-4GP DY SC22P50V2JN-4GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 Clock Generator IDT CVT125PAG Document Number A B C D Rev AG1 Date: Tuesday, January 10, 2006 -1 Sheet E of 53 A B C D E TP27 TPAD30 U72A TP19 TPAD30 TP14 B25 B1 F3 F4 G3 G2 HIT# HITM# G6 E4 AD4 AD3 AD1 AC4 AC2 AC1 AC5 AA6 AB3 AB5 AB6 C20 PROCHOT# THERMDA THERMDC D21 A24 A25 THERM THERMTRIP# RSVD[11] H_LOCK# H_CPURST# H_RS#[2 0] H_RS#0 H_RS#1 H_RS#2 H_TRDY# H_HIT# H_HITM# XDP_BPM#0 XDP_BPM#1 XDP_BPM#2 XDP_BPM#3 XDP_BPM#4 XDP_BPM#5 XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST# XDP_DBRESET# TP41 TP44 TP46 TP40 TP43 TP47 TP39 TP30 TP33 TP29 TP42 TP18 H_THERMDA 6 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 H_THERMDC BCLK[0] BCLK[1] A22 A21 RSVD[12] T22 TP28 TPAD30 RSVD[13] RSVD[14] RSVD[15] RSVD[16] RSVD[17] RSVD[18] RSVD[19] RSVD[20] D2 F6 D3 C1 AF1 D22 C23 C24 TP20 TPAD30 TP24 TPAD30 R596 0R2J-2-GP TPAD30 TPAD30 TPAD30 TPAD30 PM_THRMTRIP-I# 36 PM_THRMTRIP# should connect to ICH7 and Calistoga without T-ing ( No stub) 1D05V_S0 R628 1KR2F-3-GP Layout Note: 0.5" max length R627 2KR2F-3-GP BGA479-SKT6-GPU1 62.10079.001 2nd source: 62.10053.401 CPU_PROCHOT# 38 DY CLK_CPU_BCLK CLK_CPU_BCLK# TP45 TP17 TP16 TP15 H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_DSTBN#0 H_DSTBP#0 H_DINV#0 R595 56R2J-4-GP 1 R605 0R0402-PAD C675 SC2200P50V2KX-2GP 1D05V_S0 H_THERMDA 19 H_THERMDC 19 PM_THRMTRIP-A# C7 H_D#[63 0] U72B 6 6 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_DSTBN#1 H_DSTBP#1 H_DINV#1 CPU_GTLREF0 C321 D[0]# D[1]# D[2]# D[3]# D[4]# D[5]# D[6]# D[7]# D[8]# D[9]# D[10]# D[11]# D[12]# D[13]# D[14]# D[15]# DSTBN[0]# DSTBP[0]# DINV[0]# N22 K25 P26 R23 L25 L22 L23 M23 P25 P22 P23 T24 R24 L26 T25 N24 M24 N25 M26 D[16]# D[17]# D[18]# D[19]# D[20]# D[21]# D[22]# D[23]# D[24]# D[25]# D[26]# D[27]# D[28]# D[29]# D[30]# D[31]# DSTBN[1]# DSTBP[1]# DINV[1]# AD26 R614 1KR2J-1-GP DYTEST1 1 2TEST2 R615 51R2F-2-GP 3,7 3,7 3,7 E22 F24 E26 H22 F23 G25 E25 E23 K24 G24 J24 J23 H26 F26 K22 H25 H23 G22 J26 CPU_SEL0 CPU_SEL1 CPU_SEL2 C26 GTLREF TEST2 B22 B23 C21 BSEL[0] BSEL[1] BSEL[2] AA23 AB24 V24 V26 W25 U23 U25 U22 AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24 W24 Y25 V23 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 D[48]# D[49]# D[50]# D[51]# D[52]# D[53]# D[54]# D[55]# D[56]# D[57]# D[58]# D[59]# D[60]# D[61]# D[62]# D[63]# DSTBN[3]# DSTBP[3]# DINV[3]# AC22 AC23 AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21 AE25 AF25 AF22 AF26 AD23 AE24 AC20 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 COMP[0] COMP[1] COMP[2] COMP[3] R26 U26 U1 V1 DPRSTP# DPSLP# DPWR# PWRGOOD SLP# PSI# E5 B5 D24 D6 D7 AE6 MISC TEST1 D25 D[32]# D[33]# D[34]# D[35]# D[36]# D[37]# D[38]# D[39]# D[40]# D[41]# D[42]# D[43]# D[44]# D[45]# D[46]# D[47]# DSTBN[2]# DSTBP[2]# DINV[2]# DATA GRP CONTROL H4 DATA GRP TPAD30 ADDR GROUP LOCK# RESET# RS[0]# RS[1]# RS[2]# TRDY# H_IERR# H_INIT# 15 RSVD[01] RSVD[02] RSVD[03] RSVD[04] RSVD[05] RSVD[06] RSVD[07] RSVD[08] RSVD[09] RSVD[10] D20 B3 AA1 AA4 AB2 AA3 M4 N5 T2 V3 B2 C3 TP37 TP31 TP36 TP35 TP26 TP25 TP34 TP32 IERR# INIT# H_DINV#[3 0] H_DSTBN#[3 0] H_DSTBP#[3 0] Place testpoint on H_IERR# with a GND 0.1" away SC1KP16V2KX-GP STPCLK# LINT0 LINT1 SMI# H_BREQ#0 D5 C6 B4 A3 F1 15 H_STPCLK# 15 H_INTR 15 H_NMI 15 H_SMI# H_DEFER# H_DRDY# H_DBSY# R613 56R2J-4-GP A20M# FERR# IGNNE# 6 A6 A5 C4 H_ADS# H_BNR# H_BPRI# H5 F21 E1 BPM[0]# BPM[1]# BPM[2]# BPM[3]# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR# XDP/ITP SIGNALS 15 H_A20M# 15 H_FERR# 15 H_IGNNE# A[17]# A[18]# A[19]# A[20]# A[21]# A[22]# A[23]# A[24]# A[25]# A[26]# A[27]# A[28]# A[29]# A[30]# A[31]# ADSTB[1]# H1 E2 G5 DATA GRP H_ADSTB#1 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 BR0# REQ[0]# REQ[1]# REQ[2]# REQ[3]# REQ[4]# Y2 U5 R3 W6 U4 Y5 U2 R4 T5 T3 W3 W5 Y4 W2 Y1 V4 DEFER# DRDY# DBSY# H CLK H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 ADS# BNR# BPRI# DATA GRP H_REQ#0 K3 H_REQ#1 H2 H_REQ#2 K2 H_REQ#3 J3 H_REQ#4 L5 1D05V_S0 A[3]# A[4]# A[5]# A[6]# A[7]# A[8]# A[9]# A[10]# A[11]# A[12]# A[13]# A[14]# A[15]# A[16]# ADSTB[0]# ADDR GROUP H_ADSTB#0 H_REQ#[4 0] J4 L4 M3 K5 M1 N2 J1 N3 P5 P2 L1 P4 P1 R1 L2 RESERVED H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#[31 3] H_DSTBN#2 H_DSTBP#2 H_DINV#2 H_DSTBN#3 H_DSTBP#3 H_DINV#3 COMP0 COMP1 COMP2 COMP3 R6301 R6291 R2871 R2861 2 2 BGA479-SKT6-GPU1 R284 XDP_TMS R282 XDP_TDO R283 H_CPURST# R606 27D4R2F-L1-GP 54D9R2F-L1-GP 27D4R2F-L1-GP 54D9R2F-L1-GP H_DPRSLP# 15,38 H_DPSLP# 15 H_DPWR# H_PWRGD 15,36 H_CPUSLP# 6,15 PSI# 38 Layout Note: Comp0, connect with Zo=27.4 ohm, make trace length shorter than 0.5" Comp1, connect with Zo=55 ohm, make trace length shorter than 0.5" 1D05V_S0 XDP_TDI 150R2F-1-GP DY DY 39D2R3F-2-GP 54D9R2F-L1-GP 54D9R2F-L1-GP 3D3V_S0 XDP_DBRESET# R207 1 DY 150R2F-1-GP XDP_TCK R299 27D4R2F-L1-GP XDP_TRST# R301 680R3F-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C All place within 2" to CPU Title Size A3 Document Number CPU (1 of 2) Date: Tuesday, January 10, 2006 A B C D Rev AG1 SC Sheet E of 53 A B C D E VCC_CORE_S0 U72D VCC_CORE_S0 A4 A8 A11 A14 A16 A19 A23 A26 B6 B8 B11 B13 B16 B19 B21 B24 C5 C8 C11 C14 C16 C19 C2 C22 C25 D1 D4 D8 D11 D13 D16 D19 D23 D26 E3 E6 E8 E11 E14 E16 E19 E21 E24 F5 F8 F11 F13 F16 F19 F2 F22 F25 G4 G1 G23 G26 H3 H6 H21 H24 J2 J5 J22 J25 K1 K4 K23 K26 L3 L6 L21 L24 M2 M5 M22 M25 N1 N4 N23 N26 P3 U72C 1 1 1 2 2 2 2 VCC_SENSE 38 VSS_SENSE 38 VCC_CORE_S0 1 DY VCCSENSE and VSSSENSE lines should be of equal length Layout Note: R298 100R2F-L1-GP-U 2 2 Layout Note: Provide a test point (with no stub) to connect a differential probe between VCCSENSE and VSSSENSE at the location where the two 54.9ohm resistors terminate the 55 ohm transmission line C700 C365 C341 C676 C680 C682 SC10U10V5ZY-1GPSC10U10V5ZY-1GP SC10U10V5ZY-1GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP C716 AE7 BGA479-SKT6-GPU1 C364 C363 C348 C347 C342 C340 C711 C368 SCD1U10V2KX-4GPSCD1U10V2KX-4GP SCD1U10V2KX-4GP SC4D7U6D3V3KX-GP SCD1U10V2KX-4GPSCD1U10V2KX-4GPSCD1U10V2KX-4GP SC4D7U6D3V3KX-GP VSSSENSE C674 H_VID0 38 SCD01U16V2KX-3GP H_VID1 38 VCC_CORE_S0 H_VID2 38 H_VID3 38 H_VID4 38 H_VID5 38 R300 H_VID6 38 100R2F-L1-GP-U H_VID[0 6] 38 AF7 1D05V_S0 HCB1608KF121T30-GP 68.00230.041 C673 SC4D7U6D3V3KX-GP VCCSENSE 1D5V_S0 L22 AD6 AF5 AE5 AF4 AE3 AF2 AE2 1D5V_VCCA_S0 VID[0] VID[1] VID[2] VID[3] VID[4] VID[5] VID[6] C369 SCD1U10V2KX-4GP B26 R285 0R0402-PAD VCCA CPU_V6 V6 G21 J6 K6 M6 J21 K21 M21 N21 N6 R21 R6 T21 T6 V21 W21 VCCP[01] VCCP[02] VCCP[03] VCCP[04] VCCP[05] VCCP[06] VCCP[07] VCCP[08] VCCP[09] VCCP[10] VCCP[11] VCCP[12] VCCP[13] VCCP[14] VCCP[15] VCCP[16] Layout Note 1D05V_S0 VCC[068] VCC[069] VCC[070] VCC[071] VCC[072] VCC[073] VCC[074] VCC[075] VCC[076] VCC[077] VCC[078] VCC[079] VCC[080] VCC[081] VCC[082] VCC[083] VCC[084] VCC[085] VCC[086] VCC[087] VCC[088] VCC[089] VCC[090] VCC[091] VCC[092] VCC[093] VCC[094] VCC[095] VCC[096] VCC[097] VCC[098] VCC[099] VCC[100] 2 VCC[001] VCC[002] VCC[003] VCC[004] VCC[005] VCC[006] VCC[007] VCC[008] VCC[009] VCC[010] VCC[011] VCC[012] VCC[013] VCC[014] VCC[015] VCC[016] VCC[017] VCC[018] VCC[019] VCC[020] VCC[021] VCC[022] VCC[023] VCC[024] VCC[025] VCC[026] VCC[027] VCC[028] VCC[029] VCC[030] VCC[031] VCC[032] VCC[033] VCC[034] VCC[035] VCC[036] VCC[037] VCC[038] VCC[039] VCC[040] VCC[041] VCC[042] VCC[043] VCC[044] VCC[045] VCC[046] VCC[047] VCC[048] VCC[049] VCC[050] VCC[051] VCC[052] VCC[053] VCC[054] VCC[055] VCC[056] VCC[057] VCC[058] VCC[059] VCC[060] VCC[061] VCC[062] VCC[063] VCC[064] VCC[065] VCC[066] VCC[067] AB20 AB7 AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20 A7 A9 A10 A12 A13 A15 A17 A18 A20 B7 B9 B10 B12 B14 B15 B17 B18 B20 C9 C10 C12 C13 C15 C17 C18 D9 D10 D12 D14 D15 D17 D18 E7 E9 E10 E12 E13 E15 E17 E18 E20 F7 F9 F10 F12 F14 F15 F17 F18 F20 AA7 AA9 AA10 AA12 AA13 AA15 AA17 AA18 AA20 AB9 AC10 AB10 AB12 AB14 AB15 AB17 AB18 VSS[001] VSS[002] VSS[003] VSS[004] VSS[005] VSS[006] VSS[007] VSS[008] VSS[009] VSS[010] VSS[011] VSS[012] VSS[013] VSS[014] VSS[015] VSS[016] VSS[017] VSS[018] VSS[019] VSS[020] VSS[021] VSS[022] VSS[023] VSS[024] VSS[025] VSS[026] VSS[027] VSS[028] VSS[029] VSS[030] VSS[031] VSS[032] VSS[033] VSS[034] VSS[035] VSS[036] VSS[037] VSS[038] VSS[039] VSS[040] VSS[041] VSS[042] VSS[043] VSS[044] VSS[045] VSS[046] VSS[047] VSS[048] VSS[049] VSS[050] VSS[051] VSS[052] VSS[053] VSS[054] VSS[055] VSS[056] VSS[057] VSS[058] VSS[059] VSS[060] VSS[061] VSS[062] VSS[063] VSS[064] VSS[065] VSS[066] VSS[067] VSS[068] VSS[069] VSS[070] VSS[071] VSS[072] VSS[073] VSS[074] VSS[075] VSS[076] VSS[077] VSS[078] VSS[079] VSS[080] VSS[081] VSS[082] VSS[083] VSS[084] VSS[085] VSS[086] VSS[087] VSS[088] VSS[089] VSS[090] VSS[091] VSS[092] VSS[093] VSS[094] VSS[095] VSS[096] VSS[097] VSS[098] VSS[099] VSS[100] VSS[101] VSS[102] VSS[103] VSS[104] VSS[105] VSS[106] VSS[107] VSS[108] VSS[109] VSS[110] VSS[111] VSS[112] VSS[113] VSS[114] VSS[115] VSS[116] VSS[117] VSS[118] VSS[119] VSS[120] VSS[121] VSS[122] VSS[123] VSS[124] VSS[125] VSS[126] VSS[127] VSS[128] VSS[129] VSS[130] VSS[131] VSS[132] VSS[133] VSS[134] VSS[135] VSS[136] VSS[137] VSS[138] VSS[139] VSS[140] VSS[141] VSS[142] VSS[143] VSS[144] VSS[145] VSS[146] VSS[147] VSS[148] VSS[149] VSS[150] VSS[151] VSS[152] VSS[153] VSS[154] VSS[155] VSS[156] VSS[157] VSS[158] VSS[159] VSS[160] VSS[161] VSS[162] P6 P21 P24 R2 R5 R22 R25 T1 T4 T23 T26 U3 U6 U21 U24 V2 V5 V22 V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16 AF19 AF21 AF24 BGA479-SKT6-GPU1 1 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 1 DY 1 1 DY 1 DY DY 1 1 Wistron Corporation Title 2 2 2 2 2 2 C715 C346 C344 C343 C701 C713 C702 C714 C703 C677 C370 C683 C712 C366 C678 SC10U10V5ZY-1GP SC10U10V5ZY-1GPSC10U10V5ZY-1GP SC10U10V5ZY-1GPSC10U10V5ZY-1GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP SC10U10V5ZY-1GPSC10U10V5ZY-1GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP SC10U10V5ZY-1GP 2 VCC_CORE_S0 Size A3 Document Number CPU (2 of 2) Date: Tuesday, January 10, 2006 A B C D Rev AG1 SA Sheet E of 53 A B C D E H_XRCOMP 2 H_XSWING R644 100R2F-L1-GP-U C743 SCD1U16V2ZY-2GP H_YRCOMP R639 24D9R2F-L-GP 1D05V_S0 R642 54D9R2F-L1-GP H_YSCOMP 1D05V_S0 CLK_MCH_BCLK CLK_MCH_BCLK# E1 E2 E4 H_XRCOMP H_XSCOMP H_XSWING H_YRCOMP H_YSCOMP H_YSWING Y1 U1 W1 H_YRCOMP H_YSCOMP H_YSWING AG2 AG1 H_CLKIN H_CLKIN# 1D05V_S0 R274 100R2F-L1-GP-U H_ADS# H_ADSTB#0 H_ADSTB#1 H_VREF H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# J7 W8 U3 AB10 H_DINV#0 H_DINV#1 H_DINV#2 H_DINV#3 H_DSTBN#_0 H_DSTBN#_1 H_DSTBN#_2 H_DSTBN#_3 K4 T7 Y5 AC4 H_DSTBN#0 H_DSTBN#1 H_DSTBN#2 H_DSTBN#3 H_DSTBP#_0 H_DSTBP#_1 H_DSTBP#_2 H_DSTBP#_3 K3 T6 AA5 AC5 H_DSTBP#0 H_DSTBP#1 H_DSTBP#2 H_DSTBP#3 H_HIT# H_HITM# H_LOCK# D3 D4 B3 H_REQ#_0 H_REQ#_1 H_REQ#_2 H_REQ#_3 H_REQ#_4 D8 G8 B8 F8 A8 H_REQ#0 H_REQ#1 H_REQ#2 H_REQ#3 H_REQ#4 H_RS#_0 H_RS#_1 H_RS#_2 B4 E6 D6 H_RS#0 H_RS#1 H_RS#2 H_SLPCPU# H_TRDY# E3 E7 R246 200R2F-L-GP C362 SCD1U16V2ZY-2GP H_DINV#[3 0] H_DSTBN#[3 0] H_DSTBP#[3 0] H_HIT# H_HITM# H_LOCK# H_REQ#[4 0] H_RS#[2 0] R646 0R0402-PAD H_CPUSLP# 4,15 H_TRDY# CALISTOGA C741 SCD1U16V2ZY-2GP R640 100R2F-L1-GP-U E8 B9 C13 J13 C6 F6 C7 B7 A7 C3 J9 H8 K13 H_DINV#_0 H_DINV#_1 H_DINV#_2 H_DINV#_3 H_YSWING R641 221R2F-2-GP H_XRCOMP H_XSCOMP H_XSWING H_ADS# H_ADSTB#_0 H_ADSTB#_1 H_VREF_0 H_BNR# H_BPRI# H_BREQ#0 H_CPURST# H_DBSY# H_DEFER# H_DPWR# H_DRDY# H_VREF_1 R645 221R2F-2-GP H_A#3 H_A#4 H_A#5 H_A#6 H_A#7 H_A#8 H_A#9 H_A#10 H_A#11 H_A#12 H_A#13 H_A#14 H_A#15 H_A#16 H_A#17 H_A#18 H_A#19 H_A#20 H_A#21 H_A#22 H_A#23 H_A#24 H_A#25 H_A#26 H_A#27 H_A#28 H_A#29 H_A#30 H_A#31 1D05V_S0 H9 C9 E11 G11 F11 G12 F9 H11 J12 G14 D9 J14 H13 J15 F14 D12 A11 C11 A12 A13 E13 G13 F12 B12 B14 C12 A14 C14 D14 H_XSCOMP H_A#_3 H_A#_4 H_A#_5 H_A#_6 H_A#_7 H_A#_8 H_A#_9 H_A#_10 H_A#_11 H_A#_12 H_A#_13 H_A#_14 H_A#_15 H_A#_16 H_A#_17 H_A#_18 H_A#_19 H_A#_20 H_A#_21 H_A#_22 H_A#_23 H_A#_24 H_A#_25 H_A#_26 H_A#_27 H_A#_28 H_A#_29 H_A#_30 H_A#_31 R647 54D9R2F-L1-GP H_D#_0 H_D#_1 H_D#_2 H_D#_3 H_D#_4 H_D#_5 H_D#_6 H_D#_7 H_D#_8 H_D#_9 H_D#_10 H_D#_11 H_D#_12 H_D#_13 H_D#_14 H_D#_15 H_D#_16 H_D#_17 H_D#_18 H_D#_19 H_D#_20 H_D#_21 H_D#_22 H_D#_23 H_D#_24 H_D#_25 H_D#_26 H_D#_27 H_D#_28 H_D#_29 H_D#_30 H_D#_31 H_D#_32 H_D#_33 H_D#_34 H_D#_35 H_D#_36 H_D#_37 H_D#_38 H_D#_39 H_D#_40 H_D#_41 H_D#_42 H_D#_43 H_D#_44 H_D#_45 H_D#_46 H_D#_47 H_D#_48 H_D#_49 H_D#_50 H_D#_51 H_D#_52 H_D#_53 H_D#_54 H_D#_55 H_D#_56 H_D#_57 H_D#_58 H_D#_59 H_D#_60 H_D#_61 H_D#_62 H_D#_63 2 1D05V_S0 F1 J1 H1 J6 H3 K2 G1 G2 K9 K1 K7 J8 H4 J3 K11 G4 T10 W11 T3 U7 U9 U11 T11 W9 T1 T8 T4 W7 U5 T9 W6 T5 AB7 AA9 W4 W3 Y3 Y7 W5 Y10 AB8 W2 AA4 AA7 AA2 AA6 AA10 Y8 AA1 AB4 AC9 AB11 AC11 AB3 AC2 AD1 AD9 AC1 AD7 AC6 AB5 AD10 AD4 AC8 HOST H_A#[31 3] U71A H_D#0 H_D#1 H_D#2 H_D#3 H_D#4 H_D#5 H_D#6 H_D#7 H_D#8 H_D#9 H_D#10 H_D#11 H_D#12 H_D#13 H_D#14 H_D#15 H_D#16 H_D#17 H_D#18 H_D#19 H_D#20 H_D#21 H_D#22 H_D#23 H_D#24 H_D#25 H_D#26 H_D#27 H_D#28 H_D#29 H_D#30 H_D#31 H_D#32 H_D#33 H_D#34 H_D#35 H_D#36 H_D#37 H_D#38 H_D#39 H_D#40 H_D#41 H_D#42 H_D#43 H_D#44 H_D#45 H_D#46 H_D#47 H_D#48 H_D#49 H_D#50 H_D#51 H_D#52 H_D#53 H_D#54 H_D#55 H_D#56 H_D#57 H_D#58 H_D#59 H_D#60 H_D#61 H_D#62 H_D#63 H_D#[63 0] R643 24D9R2F-L-GP Place them near to the chip ( < 0.5") Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 Document Number GMCH (1 of 5) A B C D Rev AG1 Date: Tuesday, January 10, 2006 SA Sheet E of 53 SM_CK#_0 SM_CK#_1 SM_CK#_2 SM_CK#_3 11,12 11,12 11,12 11,12 M_CKE0 M_CKE1 M_CKE2 M_CKE3 AU20 AT20 BA29 AY29 SM_CKE_0 SM_CKE_1 SM_CKE_2 SM_CKE_3 11,12 11,12 11,12 11,12 M_CS0# M_CS1# M_CS2# M_CS3# AW13 AW12 AY21 AW21 SM_CS#_0 SM_CS#_1 SM_CS#_2 SM_CS#_3 M_OCDCOMP0 M_OCDCOMP1 M_ODT0 M_ODT1 M_ODT2 M_ODT3 M_RCOMPN M_RCOMPP BA13 BA12 AY20 AU21 SM_ODT_0 SM_ODT_1 SM_ODT_2 SM_ODT_3 SM_VREF_0 SM_VREF_1 AF33 AG33 A27 A26 C40 D41 G_CLKIN# G_CLKIN D_REFCLKIN# D_REFCLKIN D_REFSSCLKIN# D_REFSSCLKIN DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 AE35 AF39 AG35 AH39 DMI_RXN_0 DMI_RXN_1 DMI_RXN_2 DMI_RXN_3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 AC35 AE39 AF35 AG39 DMI_RXP_0 DMI_RXP_1 DMI_RXP_2 DMI_RXP_3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 AE37 AF41 AG37 AH41 DMI_TXN_0 DMI_TXN_1 DMI_TXN_2 DMI_TXN_3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 AC37 AE41 AF37 AG41 DMI_TXP_0 DMI_TXP_1 DMI_TXP_2 DMI_TXP_3 16 DMI_RXN[3 0] PM_BMBUSY# PM_EXTTS#_0 PM_EXTTS#_1 PM_THRMTRIP# PWROK RSTIN# SDVO_CTRLCLK SDVO_CTRLDATA LT_RESET# NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC 16 DMI_RXP[3 0] MISC 16 DMI_TXP[3 0] PM 16 DMI_TXN[3 0] CLK DMI 2 CLK_MCH_3GPLL# CLK_MCH_3GPLL C737 C667 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 CFG18 CFG19 CFG20 SEL2 SEL1 SEL0 CPU 0 0 1 1 0 1 0 1 1 1 266M 133M 200M 166M 333M 100M 400M Reserved TP13 TPAD30 TP12 TPAD30 MCH_ICH_SYNC# D1 C41 C1 BA41 BA40 BA39 BA3 BA2 BA1 B41 B2 AY41 AY1 AW41 AW1 A40 A4 A39 A3 16 3D3V_S0 RN97 SRN10KJ-5-GP GMCH_DDCCLK GMCH_DDCDATA 3D3V_S0 R2542 DUMMY-R2 R2422 DUMMY-R2 R2412 DUMMY-R2 R2492 DUMMY-R2 R2552 DUMMY-R2 R2472 DUMMY-R2 R2602 DUMMY-R2 R2532 DUMMY-R2 R2522 DUMMY-R2 R2592 DUMMY-R2 R2512 DUMMY-R2 R256 DY 2K2R2J-2-GP R2772 DUMMY-R2 R2752 DUMMY-R2 R2482 DUMMY-R2 R2582 DUMMY-R2 R2502 DUMMY-R2 R2762 DUMMY-R2 1 RN43 SRN10KJ-5-GP 1D8V_S3 PM_EXTTS#0 PM_EXTTS#1 M_RCOMPN R271 80D6R2F-L-GP M_RCOMPP R272 80D6R2F-L-GP C37 B35 A37 LA_DATA#_0 LA_DATA#_1 LA_DATA#_2 B37 B34 A36 LA_DATA_0 LA_DATA_1 LA_DATA_2 G30 D30 F29 LB_DATA#_0 LB_DATA#_1 LB_DATA#_2 F30 D29 F28 LB_DATA_0 LB_DATA_1 LB_DATA_2 A16 C18 A19 TV_DACA_OUT TV_DACB_OUT TV_DACC_OUT J20 B16 B18 B19 TV_IREF TV_IRTNA TV_IRTNB TV_IRTNC E23 D23 C22 B22 A21 B21 CRT_BLUE CRT_BLUE# CRT_GREEN CRT_GREEN# CRT_RED CRT_RED# C26 C25 G23 J22 H23 CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_IREF CRT_VSYNC 1D05V_S0 CALISTOGA 3D3V_S0 LA_CLK# LA_CLK LB_CLK# LB_CLK DY G28 PM_BMBUSY# 16R237 F25 PM_EXTTS#0 VGATE_PWRGD 16,38,48 0R2J-2-GP H26 PM_EXTTS#1 R239 G6 PM_THRMTRIP-A# PWROK 16,19 0R0402-PAD AH33 R238 AH34 PLT_RST1# 16,20,26,30,31,32,34,35,45 1D5V_S0 100R2J-2-GP H28 H27 K28 A33 A32 E27 E26 VGA SM_RCOMP# SM_RCOMP AK1 AK41 CPU_SEL0 3,4 CPU_SEL1 3,4 CPU_SEL2 3,4 TV AV9 AT9 1 DDR_VREF_S3 SM_OCDCOMP_0 SM_OCDCOMP_1 K16 K18 J18 F18 E15 F15 E18 D19 D16 G16 E16 D15 G15 K15 C15 H16 G18 H15 J25 K27 J26 L_BKLTCTL L_BKLTEN L_CLKCTLA L_CLKCTLB L_DDC_CLK L_DDC_DATA L_IBG L_VBG L_VDDEN L_VREFH L_VREFL LVDS R244 R273 11,12 40D2R2F-GP 40D2R2F-GP 11,12 DY DY 11,12 11,12 AL20 AF10 CFG_0 CFG_1 CFG_2 CFG_3 CFG_4 CFG_5 CFG_6 CFG_7 CFG_8 CFG_9 CFG_10 CFG_11 CFG_12 CFG_13 CFG_14 CFG_15 CFG_16 CFG_17 CFG_18 CFG_19 CFG_20 U71C D32 J30 H30 H29 G26 G25 B38 C35 F32 C33 C32 CFG18 CFG19 EXP_A_COMPI EXP_A_COMPO D40 D38 EXP_A_RXN_0 EXP_A_RXN_1 EXP_A_RXN_2 EXP_A_RXN_3 EXP_A_RXN_4 EXP_A_RXN_5 EXP_A_RXN_6 EXP_A_RXN_7 EXP_A_RXN_8 EXP_A_RXN_9 EXP_A_RXN_10 EXP_A_RXN_11 EXP_A_RXN_12 EXP_A_RXN_13 EXP_A_RXN_14 EXP_A_RXN_15 F34 G38 H34 J38 L34 M38 N34 P38 R34 T38 V34 W38 Y34 AA38 AB34 AC38 PEG_RXN0 PEG_RXN1 PEG_RXN2 PEG_RXN3 PEG_RXN4 PEG_RXN5 PEG_RXN6 PEG_RXN7 PEG_RXN8 PEG_RXN9 PEG_RXN10 PEG_RXN11 PEG_RXN12 PEG_RXN13 PEG_RXN14 PEG_RXN15 EXP_A_RXP_0 EXP_A_RXP_1 EXP_A_RXP_2 EXP_A_RXP_3 EXP_A_RXP_4 EXP_A_RXP_5 EXP_A_RXP_6 EXP_A_RXP_7 EXP_A_RXP_8 EXP_A_RXP_9 EXP_A_RXP_10 EXP_A_RXP_11 EXP_A_RXP_12 EXP_A_RXP_13 EXP_A_RXP_14 EXP_A_RXP_15 D34 F38 G34 H38 J34 L38 M34 N38 P34 R38 T34 V38 W34 Y38 AA34 AB38 PEG_RXP0 PEG_RXP1 PEG_RXP2 PEG_RXP3 PEG_RXP4 PEG_RXP5 PEG_RXP6 PEG_RXP7 PEG_RXP8 PEG_RXP9 PEG_RXP10 PEG_RXP11 PEG_RXP12 PEG_RXP13 PEG_RXP14 PEG_RXP15 EXP_A_TXN_0 EXP_A_TXN_1 EXP_A_TXN_2 EXP_A_TXN_3 EXP_A_TXN_4 EXP_A_TXN_5 EXP_A_TXN_6 EXP_A_TXN_7 EXP_A_TXN_8 EXP_A_TXN_9 EXP_A_TXN_10 EXP_A_TXN_11 EXP_A_TXN_12 EXP_A_TXN_13 EXP_A_TXN_14 EXP_A_TXN_15 F36 GTXN0 G40 GTXN1 H36 GTXN2 J40 GTXN3 L36 GTXN4 M40 GTXN5 N36 GTXN6 P40 GTXN7 R36 GTXN8 T40 GTXN9 V36 GTXN10 W40 GTXN11 Y36 GTXN12 AA40 GTXN13 AB36 GTXN14 AC40 GTXN15 EXP_A_TXP_0 EXP_A_TXP_1 EXP_A_TXP_2 EXP_A_TXP_3 EXP_A_TXP_4 EXP_A_TXP_5 EXP_A_TXP_6 EXP_A_TXP_7 EXP_A_TXP_8 EXP_A_TXP_9 EXP_A_TXP_10 EXP_A_TXP_11 EXP_A_TXP_12 EXP_A_TXP_13 EXP_A_TXP_14 EXP_A_TXP_15 D36 GTXP0 F40 GTXP1 G36 GTXP2 H40 GTXP3 J36 GTXP4 L40 GTXP5 M36 GTXP6 N40 GTXP7 P36 GTXP8 R40 GTXP9 T36 GTXP10 V40 GTXP11 W36 GTXP12 Y40 GTXP13 AA36 GTXP14 AB40 GTXP15 GRAPHICS AW35 AT1 AY7 AY40 PCI-EXPRESS M_CLK_DDR#0 M_CLK_DDR#1 M_CLK_DDR#2 M_CLK_DDR#3 E 1D5V_PCIE_S0 11 11 11 11 D SM_CK_0 SM_CK_1 SM_CK_2 SM_CK_3 MUXING AY35 AR1 AW7 AW40 M_CLK_DDR0 M_CLK_DDR1 M_CLK_DDR2 M_CLK_DDR3 CFG 11 11 11 11 C U71B RSVD_0 H32 RSVD_1 T32 RSVD_2 R32 RSVD_3 F3 RSVD_4 F7 RSVD_5 AG11 RSVD_6 AF11 RSVD_7 H7 RSVD_8 J19 RSVD_9 K30 RSVD_10 J29 RSVD_11 A41 RSVD_12 A35 RSVD_13 A34 RSVD_14 D28 RSVD_15 D27 RSVD B DDR A C298 C297 C294 C293 C290 C289 C287 C284 C283 C280 C279 C248 C277 C245 C275 C273 C300 C299 C296 C295 C292 C291 C288 C286 C285 C282 C281 C249 C278 C247 C276 C274 B PEG_RXP[15 0] 45 45 PEG_TXN[15 0] 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PEG_TXN0 SCD1U16V2KX-3GP PEG_TXN1 SCD1U16V2KX-3GP PEG_TXN2 SCD1U16V2KX-3GP PEG_TXN3 SCD1U16V2KX-3GP PEG_TXN4 SCD1U16V2KX-3GP PEG_TXN5 SCD1U16V2KX-3GP PEG_TXN6 SCD1U16V2KX-3GP PEG_TXN7 SCD1U16V2KX-3GP PEG_TXN8 SCD1U16V2KX-3GP PEG_TXN9 SCD1U16V2KX-3GP PEG_TXN10 SCD1U16V2KX-3GP PEG_TXN11 SCD1U16V2KX-3GP PEG_TXN12 SCD1U16V2KX-3GP PEG_TXN13 SCD1U16V2KX-3GP PEG_TXN14 SCD1U16V2KX-3GP 45 PEG_TXN15PEG_TXP[15 0] SCD1U16V2KX-3GP PEG_TXP0 SCD1U16V2KX-3GP PEG_TXP1 SCD1U16V2KX-3GP PEG_TXP2 SCD1U16V2KX-3GP PEG_TXP3 SCD1U16V2KX-3GP PEG_TXP4 SCD1U16V2KX-3GP PEG_TXP5 SCD1U16V2KX-3GP PEG_TXP6 SCD1U16V2KX-3GP PEG_TXP7 SCD1U16V2KX-3GP PEG_TXP8 SCD1U16V2KX-3GP PEG_TXP9 SCD1U16V2KX-3GP PEG_TXP10 SCD1U16V2KX-3GP PEG_TXP11 SCD1U16V2KX-3GP PEG_TXP12 SCD1U16V2KX-3GP PEG_TXP13 SCD1U16V2KX-3GP PEG_TXP14 SCD1U16V2KX-3GP PEG_TXP15 SCD1U16V2KX-3GP CALISTOGA CFG20 CFG3 CFG4 When High 1K Ohm CFG5 CFG6 CFG6: CFG7 0=Moby Dick ,1=Calistoga (default) CFG8 CFG9 CFG10 CFG11 When Low choice lower than 3.5K Ohm CFG12 Wistron Corporation CFG13 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C CFG14 When PM replace to GM CFG15 Title CFG16 Size A3 CFG17 Document Number GMCH (2 of 5) C D Rev AG1 Date: Tuesday, January 10, 2006 A R594 24D9R2F-L-GP PEG_RXN[15 0] 45 -1 Sheet E of 53 A B C D E 4 SA_CAS# SA_DM_0 SA_DM_1 SA_DM_2 SA_DM_3 SA_DM_4 SA_DM_5 SA_DM_6 SA_DM_7 AY13 AJ33 AM35 AL26 AN22 AM14 AL9 AR3 AH4 M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7 SA_DQS_0 SA_DQS_1 SA_DQS_2 SA_DQS_3 SA_DQS_4 SA_DQS_5 SA_DQS_6 SA_DQS_7 SA_DQS#_0 SA_DQS#_1 SA_DQS#_2 SA_DQS#_3 SA_DQS#_4 SA_DQS#_5 SA_DQS#_6 SA_DQS#_7 AK33 AT33 AN28 AM22 AN12 AN8 AP3 AG5 AK32 AU33 AN27 AM21 AM12 AL8 AN3 AH5 M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7 M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7 SA_MA_0 SA_MA_1 SA_MA_2 SA_MA_3 SA_MA_4 SA_MA_5 SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9 SA_MA_10 SA_MA_11 SA_MA_12 SA_MA_13 AY16 AU14 AW16 BA16 BA17 AU16 AV17 AU17 AW17 AT16 AU13 AT17 AV20 AV12 M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 SA_RAS# SA_RCVENIN# SA_RCVENOUT# SA_WE# AW14 AK23 AK24 AY14 M_A_BS#0 11,12 M_A_BS#1 11,12 M_A_BS#2 11,12 M_A_CAS# 11,12 M_A_DM[7 0] 11 M_A_DQS[7 0] 11 M_A_DQS#[7 0] 11 M_A_A[13 0] 11,12 M_A_RAS# 11,12 SA_RCVENIN# SA_RCVENOUT# TP23 TPAD30 TP11 TPAD30 M_A_WE# 11,12 Place Test PAD Near to Chip as could as possible B AU12 AV14 BA20 SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63 MEMORY SA_BS_0 SA_BS_1 SA_BS_2 AK39 AJ37 AP39 AR41 AJ38 AK38 AN41 AP41 AT40 AV41 AU38 AV38 AP38 AR40 AW38 AY38 BA38 AV36 AR36 AP36 BA36 AU36 AP35 AP34 AY33 BA33 AT31 AU29 AU31 AW31 AV29 AW29 AM19 AL19 AP14 AN14 AN17 AM16 AP15 AL15 AJ11 AH10 AJ9 AN10 AK13 AH11 AK10 AJ8 BA10 AW10 BA4 AW4 AY10 AY9 AW5 AY5 AV4 AR5 AK4 AK3 AT4 AK5 AJ5 AJ3 SYSTEM MEMORY SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63 SYSTEM AJ35 AJ34 AM31 AM33 AJ36 AK35 AJ32 AH31 AN35 AP33 AR31 AP31 AN38 AM36 AM34 AN33 AK26 AL27 AM26 AN24 AK28 AL28 AM24 AP26 AP23 AL22 AP21 AN20 AL23 AP24 AP20 AT21 AR12 AR14 AP13 AP12 AT13 AT12 AL14 AL12 AK9 AN7 AK8 AK7 AP9 AN9 AT5 AL5 AY2 AW2 AP1 AN2 AV2 AT3 AN1 AL2 AG7 AF9 AG4 AF6 AG9 AH6 AF4 AF8 DDR M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63 A U71D 11 M_A_DQ[63 0] U71E M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63 DDR 11 M_B_DQ[63 0] SB_BS_0 SB_BS_1 SB_BS_2 AT24 AV23 AY28 SB_CAS# SB_DM_0 SB_DM_1 SB_DM_2 SB_DM_3 SB_DM_4 SB_DM_5 SB_DM_6 SB_DM_7 AR24 AK36 AR38 AT36 BA31 AL17 AH8 BA5 AN4 M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7 SB_DQS_0 SB_DQS_1 SB_DQS_2 SB_DQS_3 SB_DQS_4 SB_DQS_5 SB_DQS_6 SB_DQS_7 SB_DQS#_0 SB_DQS#_1 SB_DQS#_2 SB_DQS#_3 SB_DQS#_4 SB_DQS#_5 SB_DQS#_6 SB_DQS#_7 AM39 AT39 AU35 AR29 AR16 AR10 AR7 AN5 AM40 AU39 AT35 AP29 AP16 AT10 AT7 AP5 M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7 M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7 SB_MA_0 SB_MA_1 SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6 SB_MA_7 SB_MA_8 SB_MA_9 SB_MA_10 SB_MA_11 SB_MA_12 SB_MA_13 AY23 AW24 AY24 AR28 AT27 AT28 AU27 AV28 AV27 AW27 AV24 BA27 AY27 AR23 M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 SB_RAS# SB_RCVENIN# SB_RCVENOUT# SB_WE# AU23 AK16 AK18 AR27 M_B_BS#0 11,12 M_B_BS#1 11,12 M_B_BS#2 11,12 M_B_CAS# 11,12 M_B_DM[7 0] 11 M_B_DQS[7 0] 11 M_B_DQS#[7 0] 11 M_B_A[13 0] 11,12 M_B_RAS# 11,12 SB_RCVENIN# SB_RCVENOUT# TP22 TPAD30 TP21 TPAD30 M_B_WE# 11,12 Place Test PAD Near to Chip ascould as possible CALISTOGA CALISTOGA 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 Document Number GMCH (3 of 5) A B C D Rev AG1 Date: Tuesday, January 10, 2006 SA Sheet E of 53 A B C D E U71H B26 C39 AF1 VCCA_DPLLA VCCA_DPLLB VCCA_HPLL A38 B39 VCCA_LVDS VSSA_LVDS AF2 VCCA_MPLL H20 G20 VCCA_TVBG VSSA_TVBG E19 F19 C20 D20 E20 F20 VCCA_TVDACA0 VCCA_TVDACA1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACC0 VCCA_TVDACC1 AH1 AH2 VCCD_HMPLL0 VCCD_HMPLL1 A28 B28 C28 VCCD_LVDS0 VCCD_LVDS1 VCCD_LVDS2 D21 VCCD_TVDAC A23 B23 B25 VCC_HV0 VCC_HV1 VCC_HV2 H19 VCCD_QTVDAC 1D5V_HPLL_S0 1D5V_S0 1D5V_MPLL_S0 1D5V_S0 1D5V_S0 L11 1D5V_HPLL_S0 C400 R257 11D5V_TVDAC_S0 0R0603-PAD C339 SCD1U10V2KX-4GP C401 1D5V_S0 1 HCB1608KF121T30-GP 68.00230.041 L30 R619 0R0603-PAD 1 1 3D3V_S0 2 1D5V_MPLL_S0 HCB1608KF121T30-GP SC10U10V5ZY-1GP SCD1U10V2KX-4GP 68.00230.041 C738 C739 SC10U10V5ZY-1GP SCD1U10V2KX-4GP 2 C698 C697 SC10U10V5ZY-1GPSCD1U10V2KX-4GP 1D5V_S0 11D5V_QTVDAC_S0 C338 SCD1U10V2KX-4GP 2 R620 0R0603-PAD 1D5V_S0 1D5V_AUX C334 SCD1U10V2KX-4GP SCD1U10V2KX-4GP C330 SCD1U10V2KX-4GP C314 2 SCD1U10V2KX-4GP C336 1 R245 0R0805-PAD AK31 AF31 AE31 AC31 AL30 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AG29 AF29 AE29 AD29 AC29 AG28 AF28 AE28 AH22 AJ21 AH21 AJ20 AH20 AH19 P19 P16 AH15 P15 AH14 AG14 AF14 AE14 Y14 AF13 AE13 AF12 AE12 AD12 POWER VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4 VCCAUX5 VCCAUX6 VCCAUX7 VCCAUX8 VCCAUX9 VCCAUX10 VCCAUX11 VCCAUX12 VCCAUX13 VCCAUX14 VCCAUX15 VCCAUX16 VCCAUX17 VCCAUX18 VCCAUX19 VCCAUX20 VCCAUX21 VCCAUX22 VCCAUX23 VCCAUX24 VCCAUX25 VCCAUX26 VCCAUX27 VCCAUX28 VCCAUX29 VCCAUX30 VCCAUX31 VCCAUX32 VCCAUX33 VCCAUX34 VCCAUX35 VCCAUX36 VCCAUX37 VCCAUX38 VCCAUX39 VCCAUX40 VCCP_GMCH_CAP3 VCCP_GMCH_CAP2 VCCP_GMCH_CAP1 C740 SCD47U10V3ZY-GP C744 SCD47U10V3ZY-GP Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Document Number GMCH (4 of 5) Date: Tuesday, January 10, 2006 C C710 SCD22U16V3ZY-GP Size A3 B 1 CALISTOGA A C332 C742 SC2D2U6D3V3MX-1-GP SC4D7U10V5ZY-3GP VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC C361 SCD1U10V2KX-4GP F21 E21 G21 1D05V_S0 VCC3G0 VCC3G1 VCC3G2 VCC3G3 VCC3G4 VCC3G5 VCC3G6 VCCA_3GPLL VCCA_3GBG VSSA_3GBG 2D5V_3GBG_S0 VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2 AC14 AB14 W14 V14 T14 R14 P14 N14 M14 L14 AD13 AC13 AB13 AA13 Y13 W13 V13 U13 T13 R13 N13 M13 L13 AB12 AA12 Y12 W12 V12 U12 T12 R12 P12 N12 M12 L12 R11 P11 N11 M11 R10 P10 N10 M10 P9 N9 M9 R8 P8 N8 M8 P7 N7 M7 R6 P6 M6 A6 R5 P5 N5 M5 P4 N4 M4 R3 P3 N3 M3 R2 P2 M2 D2 AB1 R1 P1 N1 M1 C315 SCD1U10V2KX-4GP C671 VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20 VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49 VTT_50 VTT_51 VTT_52 VTT_53 VTT_54 VTT_55 VTT_56 VTT_57 VTT_58 VTT_59 VTT_60 VTT_61 VTT_62 VTT_63 VTT_64 VTT_65 VTT_66 VTT_67 VTT_68 VTT_69 VTT_70 VTT_71 VTT_72 VTT_73 VTT_74 VTT_75 VTT_76 C668 AJ41 AB41 Y41 V41 R41 N41 L41 AC33 G41 H41 1D05V_S0 VCCSYNC SC4D7U6D3V3KX-GP C669 SCD1U10V2KX-4GP 2 0R0603-PAD C316 1 R240 C670 1D5V_3GPLL_S0 SC4D7U6D3V3KX-GP R592 0R0805-PAD 1D5V_S0 C30 B30 A30 1D5V_PCIE_S0 SC4D7U6D3V3KX-GP 1D5V_S0 C672 SCD1U10V2KX-4GP R593 0R0603-PAD 2D5V_S0 SC4D7U6D3V3KX-GP 2D5V_3GBG_S0 H22 D Rev AG1 SA Sheet E of 53 A 1D05V_S0 AC41 AA41 W41 T41 VCC_NCTF0 P41 VCC_NCTF1 VSS_NCTF0 AE27 M41 VCC_NCTF2 VSS_NCTF1 AE26 J41 VCC_NCTF3 VSS_NCTF2 AE25 F41 VCC_NCTF4 VSS_NCTF3 AE24 AV40 VCC_NCTF5 VSS_NCTF4 AE23 AP40 VCC_NCTF6 VSS_NCTF5 AE22 AN40 VCC_NCTF7 VSS_NCTF6 AE21 AK40 VCC_NCTF8 VSS_NCTF7 AE20 AJ40 VCC_NCTF9 VSS_NCTF8 AE19 AH40 VCC_NCTF10 VSS_NCTF9 AE18 AG40 VCC_NCTF11 VSS_NCTF10 AC17 Y17 AF40 VCC_NCTF12 VSS_NCTF11 AE40 VCC_NCTF13 VSS_NCTF12 U17 B40 VCC_NCTF14 1D5V_AUX AY39 VCC_NCTF15 AW39 VCC_NCTF16 AV39 VCC_NCTF17 AR39 VCC_NCTF18 AN39 VCC_NCTF19 VCCAUX_NCTF0 AG27 AJ39 VCC_NCTF20 VCCAUX_NCTF1 AF27 AC39 VCC_NCTF21 VCCAUX_NCTF2 AG26 AB39 VCC_NCTF22 VCCAUX_NCTF3 AF26 AG25 AA39 VCC_NCTF23 VCCAUX_NCTF4 Y39 VCC_NCTF24 VCCAUX_NCTF5 AF25 W39 VCC_NCTF25 VCCAUX_NCTF6 AG24 V39 VCC_NCTF26 VCCAUX_NCTF7 AF24 AG23 T39 VCC_NCTF27 VCCAUX_NCTF8 R39 VCC_NCTF28 VCCAUX_NCTF9 AF23 P39 VCC_NCTF29 VCCAUX_NCTF10 AG22 N39 VCC_NCTF30 VCCAUX_NCTF11 AF22 M39 VCC_NCTF31 VCCAUX_NCTF12 AG21 L39 VCC_NCTF32 VCCAUX_NCTF13 AF21 J39 VCC_NCTF33 VCCAUX_NCTF14 AG20 H39 VCC_NCTF34 VCCAUX_NCTF15 AF20 AG19 G39 VCC_NCTF35 VCCAUX_NCTF16 F39 VCC_NCTF36 VCCAUX_NCTF17 AF19 D39 VCC_NCTF37 VCCAUX_NCTF18 R19 AT38 VCC_NCTF38 VCCAUX_NCTF19 AG18 AF18 AM38 VCC_NCTF39 VCCAUX_NCTF20 AH38 VCC_NCTF40 VCCAUX_NCTF21 R18 AG38 VCC_NCTF41 VCCAUX_NCTF22 AG17 AF38 VCC_NCTF42 VCCAUX_NCTF23 AF17 AE17 AE38 VCC_NCTF43 VCCAUX_NCTF24 C38 VCC_NCTF44 VCCAUX_NCTF25 AD17 AK37 VCC_NCTF45 VCCAUX_NCTF26 AB17 AH37 VCC_NCTF46 VCCAUX_NCTF27 AA17 AB37 VCC_NCTF47 VCCAUX_NCTF28 W17 AA37 VCC_NCTF48 VCCAUX_NCTF29 V17 Y37 VCC_NCTF49 VCCAUX_NCTF30 T17 R17 W37 VCC_NCTF50 VCCAUX_NCTF31 V37 VCC_NCTF51 VCCAUX_NCTF32 AG16 T37 VCC_NCTF52 VCCAUX_NCTF33 AF16 R37 VCC_NCTF53 VCCAUX_NCTF34 AE16 P37 VCC_NCTF54 VCCAUX_NCTF35 AD16 N37 VCC_NCTF55 VCCAUX_NCTF36 AC16 M37 VCC_NCTF56 VCCAUX_NCTF37 AB16 L37 VCC_NCTF57 VCCAUX_NCTF38 AA16 Y16 J37 VCC_NCTF58 VCCAUX_NCTF39 H37 VCC_NCTF59 VCCAUX_NCTF40 W16 G37 VCC_NCTF60 VCCAUX_NCTF41 V16 F37 VCC_NCTF61 VCCAUX_NCTF42 U16 D37 VCC_NCTF62 VCCAUX_NCTF43 T16 AY36 VCC_NCTF63 VCCAUX_NCTF44 R16 AW36 VCC_NCTF64 VCCAUX_NCTF45 AG15 AN36 VCC_NCTF65 VCCAUX_NCTF46 AF15 AH36 VCC_NCTF66 VCCAUX_NCTF47 AE15 AG36 VCC_NCTF67 VCCAUX_NCTF48 AD15 AC15 AF36 VCC_NCTF68 VCCAUX_NCTF49 AE36 VCC_NCTF69 VCCAUX_NCTF50 AB15 AC36 VCC_NCTF70 VCCAUX_NCTF51 AA15 C36 VCC_NCTF71 VCCAUX_NCTF52 Y15 B36 VCC_NCTF72 VCCAUX_NCTF53 W15 BA35 VCCAUX_NCTF54 V15 AV35 VCCAUX_NCTF55 U15 AR35 VCCAUX_NCTF56 T15 AH35 VCCAUX_NCTF57 R15 AB35 AA35 CALISTOGA Y35 W35 V35 T35 R35 P35 N35 C320 C337 C317 C319 C333 C335 C318 TC20 M35 ST220U2VBM-3GP SC10U10V5ZY-1GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP L35 SC10U10V5ZY-1GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP J35 H35 G35 Place these Caps close VCC_0 ~ VCC_110 F35 D35 AN34 1D8V_S3 U71F AD27 AC27 AB27 AA27 Y27 W27 V27 U27 T27 R27 AD26 AC26 AB26 AA26 Y26 W26 V26 U26 T26 R26 AD25 AC25 AB25 AA25 Y25 W25 V25 U25 T25 R25 AD24 AC24 AB24 AA24 Y24 W24 V24 U24 T24 R24 AD23 V23 U23 T23 R23 AD22 V22 U22 T22 R22 AD21 V21 U21 T21 R21 AD20 V20 U20 T20 R20 AD19 V19 U19 T19 AD18 AC18 AB18 AA18 Y18 W18 V18 U18 T18 1 1 1 2 2 2 NCTF VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 VSS_159 VSS_160 VSS_161 VSS_162 VSS_163 VSS_164 VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170 VSS_171 VSS_172 VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179 E CALISTOGA C399 DY C695 C709 C686 U71J AT23 AN23 AM23 AH23 AC23 W23 K23 J23 F23 C23 AA22 K22 G22 F22 E22 D22 A22 BA21 AV21 AR21 AN21 AL21 AB21 Y21 P21 K21 J21 H21 C21 AW20 AR20 AM20 AA20 K20 B20 A20 AN19 AC19 W19 K19 G19 C19 AH18 P18 H18 D18 A18 AY17 AR17 AP17 AM17 AK17 AV16 AN16 AL16 J16 F16 C16 AN15 AM15 AK15 N15 M15 L15 B15 A15 BA14 AT14 AK14 AD14 AA14 U14 K14 H14 E14 AV13 AR13 AN13 AM13 AL13 AG13 P13 F13 D13 B13 AY12 AC12 K12 H12 E12 AD11 AA11 Y11 VSS_180 VSS_181 VSS_182 VSS_183 VSS_184 VSS_185 VSS_186 VSS_187 VSS_188 VSS_189 VSS_190 VSS_191 VSS_192 VSS_193 VSS_194 VSS_195 VSS_196 VSS_197 VSS_198 VSS_199 VSS_200 VSS_201 VSS_202 VSS_203 VSS_204 VSS_205 VSS_206 VSS_207 VSS_208 VSS_209 VSS_210 VSS_211 VSS_212 VSS_213 VSS_214 VSS_215 VSS_216 VSS_217 VSS_218 VSS_219 VSS_220 VSS_221 VSS_222 VSS_223 VSS_224 VSS_225 VSS_226 VSS_227 VSS_228 VSS_229 VSS_230 VSS_231 VSS_232 VSS_233 VSS_234 VSS_235 VSS_236 VSS_237 VSS_238 VSS_239 VSS_240 VSS_241 VSS_242 VSS_243 VSS_244 VSS_245 VSS_246 VSS_247 VSS_248 VSS_249 VSS_250 VSS_251 VSS_252 VSS_253 VSS_254 VSS_255 VSS_256 VSS_257 VSS_258 VSS_259 VSS_260 VSS_261 VSS_262 VSS_263 VSS_264 VSS_265 VSS_266 VSS_267 VSS_268 VSS_269 VSS_270 VSS_271 VSS_272 VSS B C J11 D11 B11 AV10 AP10 AL10 AJ10 AG10 AC10 W10 U10 BA9 AW9 AR9 AH9 AB9 Y9 R9 G9 E9 A9 AG8 AD8 AA8 U8 K8 C8 BA7 AV7 AP7 AL7 AJ7 AH7 AF7 AC7 R7 G7 D7 AG6 AD6 AB6 Y6 U6 N6 K6 H6 B6 AV5 AF5 AD5 AY4 AR4 AP4 AL4 AJ4 Y4 U4 R4 J4 F4 C4 AY3 AW3 AV3 AL3 AH3 AG3 AF3 AD3 AC3 AA3 G3 AT2 AR2 AP2 AK2 AJ2 AD2 AB2 Y2 U2 T2 N2 J2 H2 F2 C2 AL1 CALISTOGA C313 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 Document Number GMCH (5 of 5) AG1 Date: Tuesday, January 10, 2006 A VSS_273 VSS_274 VSS_275 VSS_276 VSS_277 VSS_278 VSS_279 VSS_280 VSS_281 VSS_282 VSS_283 VSS_284 VSS_285 VSS_286 VSS_287 VSS_288 VSS_289 VSS_290 VSS_291 VSS_292 VSS_293 VSS_294 VSS_295 VSS_296 VSS_297 VSS_298 VSS_299 VSS_300 VSS_301 VSS_302 VSS_303 VSS_304 VSS_305 VSS_306 VSS_307 VSS_308 VSS_309 VSS_310 VSS_311 VSS_312 VSS_313 VSS_314 VSS_315 VSS_316 VSS_317 VSS_318 VSS_319 VSS_320 VSS_321 VSS_322 VSS_323 VSS_324 VSS_325 VSS_326 VSS_327 VSS_328 VSS_329 VSS_330 VSS_331 VSS_332 VSS_333 VSS_334 VSS_335 VSS_336 VSS_337 VSS_338 VSS_339 VSS_340 VSS_341 VSS_342 VSS_343 VSS_344 VSS_345 VSS_346 VSS_347 VSS_348 VSS_349 VSS_350 VSS_351 VSS_352 VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360 Wistron Corporation SCD1U16V2ZY-2GP C359 SCD1U16V2ZY-2GP C331 SCD1U16V2ZY-2GP C736 SCD1U16V2ZY-2GP C360 SCD1U10V2KX-4GP DY SCD1U10V2KX-4GP C708 SCD1U10V2KX-4GP TC21 AK34 AG34 AF34 AE34 AC34 C34 AW33 AV33 AR33 AE33 AB33 Y33 V33 T33 R33 M33 H33 G33 F33 D33 B33 AH32 AG32 AF32 AE32 AC32 AB32 G32 B32 AY31 AV31 AN31 AJ31 AG31 AB31 Y31 AB30 E30 AT29 AN29 AB29 T29 N29 K29 G29 E29 C29 B29 A29 BA28 AW28 AU28 AP28 AM28 AD28 AC28 W28 J28 E28 AP27 AM27 AK27 J27 G27 F27 C27 B27 AN26 M26 K26 F26 D26 AK25 P25 K25 H25 E25 D25 A25 BA24 AU24 AL24 AW23 CALISTOGA SCD1U10V2KX-4GP VCC VCC_SM_0 VCC_SM_1 VCC_SM_2 VCC_SM_3 VCC_SM_4 VCC_SM_5 VCC_SM_6 VCC_SM_7 VCC_SM_8 VCC_SM_9 VCC_SM_10 VCC_SM_11 VCC_SM_12 VCC_SM_13 VCC_SM_14 VCC_SM_15 VCC_SM_16 VCC_SM_17 VCC_SM_18 VCC_SM_19 VCC_SM_20 VCC_SM_21 VCC_SM_22 VCC_SM_23 VCC_SM_24 VCC_SM_25 VCC_SM_26 VCC_SM_27 VCC_SM_28 VCC_SM_29 VCC_SM_30 VCC_SM_31 VCC_SM_32 VCC_SM_33 VCC_SM_34 VCC_SM_35 VCC_SM_36 VCC_SM_37 VCC_SM_38 VCC_SM_39 VCC_SM_40 VCC_SM_41 VCC_SM_42 VCC_SM_43 VCC_SM_44 VCC_SM_45 VCC_SM_46 VCC_SM_47 VCC_SM_48 VCC_SM_49 VCC_SM_50 VCC_SM_51 VCC_SM_52 VCC_SM_53 VCC_SM_54 VCC_SM_55 VCC_SM_56 VCC_SM_57 VCC_SM_58 VCC_SM_59 VCC_SM_60 VCC_SM_61 VCC_SM_62 VCC_SM_63 VCC_SM_64 VCC_SM_65 VCC_SM_66 VCC_SM_67 VCC_SM_68 VCC_SM_69 VCC_SM_70 VCC_SM_71 VCC_SM_72 VCC_SM_73 VCC_SM_74 VCC_SM_75 VCC_SM_76 VCC_SM_77 VCC_SM_78 VCC_SM_79 VCC_SM_80 VCC_SM_81 VCC_SM_82 VCC_SM_83 VCC_SM_84 VCC_SM_85 VCC_SM_86 VCC_SM_87 VCC_SM_88 VCC_SM_89 VCC_SM_90 VCC_SM_91 VCC_SM_92 VCC_SM_93 VCC_SM_94 VCC_SM_95 VCC_SM_96 VCC_SM_97 VCC_SM_98 VCC_SM_99 VCC_SM_100 VCC_SM_101 VCC_SM_102 VCC_SM_103 VCC_SM_104 VCC_SM_105 VCC_SM_106 VCC_SM_107 AU41 AT41 AM41 AU40 BA34 AY34 AW34 AV34 AU34 AT34 AR34 BA30 AY30 AW30 AV30 AU30 AT30 AR30 AP30 AN30 AM30 AM29 AL29 AK29 AJ29 AH29 AJ28 AH28 AJ27 AH27 BA26 AY26 AW26 AV26 AU26 AT26 AR26 AJ26 AH26 AJ25 AH25 AJ24 AH24 BA23 AJ23 BA22 AY22 AW22 AV22 AU22 AT22 AR22 AP22 AK22 AJ22 AK21 AK20 BA19 AY19 AW19 AV19 AU19 AT19 AR19 AP19 AK19 AJ19 AJ18 AJ17 AH17 AJ16 AH16 BA15 AY15 AW15 AV15 AU15 AT15 AR15 AJ15 AJ14 AJ13 AH13 AK12 AJ12 AH12 AG12 AK11 BA8 AY8 AW8 AV8 AT8 AR8 AP8 BA6 AY6 AW6 AV6 AT6 AR6 AP6 AN6 AL6 AK6 AJ6 AV1 AJ1 SCD1U10V2KX-4GP 1 VCC_0 VCC_1 VCC_2 VCC_3 VCC_4 VCC_5 VCC_6 VCC_7 VCC_8 VCC_9 VCC_10 VCC_11 VCC_12 VCC_13 VCC_14 VCC_15 VCC_16 VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53 VCC_54 VCC_55 VCC_56 VCC_57 VCC_58 VCC_59 VCC_60 VCC_61 VCC_62 VCC_63 VCC_64 VCC_65 VCC_66 VCC_67 VCC_68 VCC_69 VCC_70 VCC_71 VCC_72 VCC_73 VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79 VCC_80 VCC_81 VCC_82 VCC_83 VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89 VCC_90 VCC_91 VCC_92 VCC_93 VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99 VCC_100 VCC_101 VCC_102 VCC_103 VCC_104 VCC_105 VCC_106 VCC_107 VCC_108 VCC_109 VCC_110 SC10U10V5ZY-1GP 2 D U71I C B U71G AA33 W33 P33 N33 L33 J33 AA32 Y32 W32 V32 P32 N32 M32 L32 J32 AA31 W31 V31 T31 R31 P31 N31 M31 AA30 Y30 W30 V30 U30 T30 R30 P30 N30 M30 L30 AA29 Y29 W29 V29 U29 R29 P29 M29 L29 AB28 AA28 Y28 V28 U28 T28 R28 P28 N28 M28 L28 P27 N27 M27 L27 P26 N26 L26 N25 M25 L25 P24 N24 M24 AB23 AA23 Y23 P23 N23 M23 L23 AC22 AB22 Y22 W22 P22 N22 M22 L22 AC21 AA21 W21 N21 M21 L21 AC20 AB20 Y20 W20 P20 N20 M20 L20 AB19 AA19 Y19 N19 M19 L19 N18 M18 L18 P17 N17 M17 N16 M16 L16 ST220U2VBM-3GP 1D05V_S0 D Rev SA Sheet E 10 of 53 1 C373 2 C322 SC10U35V0ZY-1GP D D D D U30 IRF7807ZPBF-GP C685 SC10U35V0ZY-1GP D SC10U35V0ZY-1GP DCBATOUT_6262 EC321 SCD1U25V3ZY-1GP Panasonic ETQP4LR36WFC 10*11.5*4mm 0.34uH / 24A DCR=1.1mohm S S S G ENG 38 1 TC7 2 38 6262_ISENP1 2 6262_ISENN1 G77 GAP-CLOSE-PWR TC6 C684 SCD1U25V3ZY-1GP DY C 1 G76 GAP-CLOSE-PWR TC9 SE330U2VDM-L2GP S S S G C SE330U2VDM-L2GP D D D D S S S G U29 IRF7805ZPBF-GP D D D D Id=30A Qg=8~11nC, Rdson=14.4~18mohm U28 IRF7805ZPBF-GP 8 TC4 L-D36UH-1-GP 6262_LGATE1 SE330U2VDM-L2GP 38 L23 SE330U2VDM-L2GP 6262_PHASE1 Iomax=44A OCP>=88A VCC_CORE_S0 6262_UGATE1 38 38 D ENG KEMET 330uF / 3V / V size ESR=9mohm / Iripple=3.7A 1 DY Panasonic ETQP4LR36WFC 10*11.5*4mm 0.34uH / 24A DCR=1.1mohm B 6262_PHASE2 38 6262_LGATE2 B L-D36UH-1-GP S S S G TC8 2 2 G83 GAP-CLOSE-PWR 4 1 G82 GAP-CLOSE-PWR SE330U2VDM-L2GP D D D D S S S G U35 IRF7805ZPBF-GP D D D D Id=46A Qg=15~21nC, Rdson=6.9~8.6mohm 8 TC5 U32 IRF7805ZPBF-GP SE330U2VDM-L2GP 38 L27 6262_UGATE2 38 C372 SCD1U25V3ZY-1GP 2 SC10U35V0ZY-1GP C717 S S S G ENG C311 SC10U35V0ZY-1GP D D D D U33 IRF7807ZPBF-GP C718 SC10U35V0ZY-1GP DCBATOUT_6262 ENG A 38 6262_ISENP2 38 6262_ISENN2 A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title CPU Vcore Power_2 Size A3 Document Number Date: Tuesday, January 10, 2006 Rev AG1 SD Sheet 39 of 53 A B C D E G48 1 2 51120_VREF2 0R0402-PAD C793 C777 SC33P50V2JN-3GP DY VFB1 N/A not use ADJ VFB2 N/A not use ADJ 5V Fixed Output 3.3V Fixed Output EN1,EN2 Switcher OFF not use Swithchr ON Switcher ON EN3,EN5 not use LDO ON 2 180k/CH1 280k/CH2 51120_COMP2 C782 SC390P50V3JN-GP DY LDO OFF VREG3 on DY 51120_VFB2 B GAP-CLOSE-PWR G43 GAP-CLOSE-PWR G44 GAP-CLOSE-PWR G45 GAP-CLOSE-PWR G46 GAP-CLOSE-PWR G47 3D3V_S5 GAP-CLOSE-PWR NEC 220uF ,V size ESR=25mohm Iripple=2.2A G104 51120_AGND Vout=1V*(R1+R2)/R2 GAP-CLOSE-PWR R674 22KR2J-GP DY C781 SC1KP25V3MX-GP 51120_AGND For TPS51120, Vout=5V If you use If you use If you use Vout=3.3V If you use If you use If you use a 6.8uH inductor, the minimum ESR is 70m ohm a 4.7uH inductor, the minimum ESR is 48m ohm a 3.3uH inductor, the minimum ESR is 34m ohm a 4.7uH inductor, the minimum ESR is 51m ohm a 3.3uH inductor, the minimum ESR is 36m ohm a 2.5uH inductor, the minimum ESR is 27m ohm Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title 5V_UP_S5/3D3V_S5/5V_S5 Size A3 DY Document Number Date: Tuesday, January 10, 2006 51120_AGND A 3D3V Iomax=6A OCP>12A R662 TC12 30K9R3F-GP ST220U6D3VDM-15GP 220k/CH1 330k/CH2 DY 51120_AGND 290k/CH1 440k/CH2 3D3V_PWR C785 SC1KP25V3MX-GP 380k/CH1 590k/CH2 DY D-Cap MODE GAP-CLOSE-PWR G42 DY DY TONSEL CURRENT MODE PWM R661 13K3R2F-L1-GP R675 22KR2J-GP COMP N/A N/A PWM Iomax=11A Qg=9.8nC, Rdson=19.6~24mohm GAP-CLOSE-PWR G41 2 IND-3D3UH-43-GP U48 AO4422-1-GP V5FILT EC471 SCD1U25V3ZY-1GP ENG L36 51120_DRVH2 51120_LL2 51120_TONSEL R341 C795 74.51120.073 51120_DRVL2 C786 SC390P50V3JN-GP 2 Iomax=11A Qg=9.8nC, Rdson=20~25mohm R340 0R0402-PAD SC 1 U47 AO4422-1-GP 51120_DRVH1 51120_DRVH2 27 14 51120_CS2 SKIPSEL GAP-CLOSE-PWR G53 5V_S5 GAP-CLOSE-PWR 3D3V_PWR DRVH1 DRVH2 AUTOSKIP AUTOSKIP /FAULTS OFF FLOAT DCBATOUT_51120 38,41,43,48 25 16 CPUCORE_ON DRVL1 DRVL2 51120_PGOOD1 R342 51120_PGOOD2 0R0402-PAD R339 0R0402-PAD 51120_DRVL1 51120_DRVL2 30 11 51120_COMP1 VREF2 GAP-CLOSE-PWR G39 51120_AGND GND 1 COMP2 COMP1 PGOOD1 PGOOD2 51120_LL2 51120_LL1 OCP 51120_AGND 51120_CS1 15 26 S S S G 15KR3F-GP R353 20KR3F-GP GAP-CLOSE-PWR G38 D D D D NEC 220uF ,V size ESR=25mohm Iripple=2.2A 23 18 51120_V5FILT R355 20 22 V5FILT VIN 28 13 24 17 33 51120_AGND TC13 ST220U6D3VDM-15GP R338 100KR2J-1-GP LL2 LL1 S S S G C779 SC1KP25V3MX-GP TPS51120RHBR-GPU1 GAP-CLOSE-PWR G37 VREF2 5V_PWR G40 GAP-CLOSE-PWR G36 51120_AGND 51120_VREF2 DY VO1 VO2 GAP-CLOSE-PWR G35 U45 SKIPSEL TONSEL 51120_SKIPSEL 32 31 5V_PWR 3D3V_PWR CS1 CS2 VFB2 VFB1 5V Iomax=6A OCP>12A R668 7K5R3F-GP SC10U35V0ZY-1GP DY 51120_DRVL1 D D D D 51120_VFB2 51120_VFB1 3D3V_S0 EN1 EN2 EN3 EN5 PGND1 PGND2 GND GND 29 12 10 VBST1 VBST2 VREG3 VREG5 19 21 2 51120_EN1 51120_EN2 1TPAD28 1TPAD28 R667 30KR2F-GP 51120_VFB1 51120_COMP2 1R663 0R0603-PAD 51120_COMP1 1R666 0R0603-PAD C783 20R0402-PAD 0R0402-PAD 51120_V5FILT 51120_VREG3 DY SC10U35V0ZY-1GP 1 R664 R665 51120_V5FILT C455 SCD1U50V3ZY-GP C780 SC33P50V2JN-3GP Iomax=11A Qg=9.8nC, Rdson=19.6~24mohm 2 U50 AO4422-1-GP 1 SC10U10V5KX-2GP SC10U10V5KX-2GP R352 0R0402-PAD R356 0R0402-PAD TP52 TP53 GS 10*10*4 4D7uH 5V_PWR DCR=25mohm, Isat=6A IND-4D7UH-85-GP S S S G 51120_VBST1_11 R357 51120_VBST1 0R0603-PAD SCD1U50V3ZY-GP 51120_VREG5 36 TPS51120_EN1_5 36 TPS51120_EN2_3D3 D D D D C456 51120_LL1 L37 51120_DRVH1 51120_LL1 C453 51120_AGND DCBATOUT_51120 51120_LL2 51120_VBST2_11 R351 51120_VBST2 0R0603-PAD SCD1U50V3ZY-GP C784 EC470 SCD1U25V3ZY-1GP GAP-CLOSE-PWR G34 C454 SC1U10V3KX-3GP R354 51120_VREG5 5D1R3F-GP GAP-CLOSE-PWR C794 GAP-CLOSE-PWR G52 Iomax=11A Qg=9.8nC, Rdson=20~25mohm 51120_V5FILT C792 1 GAP-CLOSE-PWR G51 U49 AO4422-1-GP GAP-CLOSE-PWR G50 G33 SC10U35V0ZY-1GP DCBATOUT_51120 SC10U35V0ZY-1GP S S S G DCBATOUT DCBATOUT_51120 D D D D GAP-CLOSE-PWR G49 1 C D Rev -1 AG1 Sheet E 40 of 53 DCBATOUT_51124 SC10U35V0ZY-1GP 2 SC10U35V0ZY-1GP 1D8V_PWR G102 Voutsetting=1.838V R780 27KR2F-L-GP DY 1D8V Iomax=7A OCP>14A SE220U2D5VDM-3GP 1 2 C873 2 GAP-CLOSE-PWR G98 GAP-CLOSE-PWR G99 GAP-CLOSE-PWR G96 GAP-CLOSE-PWR G100 GAP-CLOSE-PWR G97 GAP-CLOSE-PWR G103 GAP-CLOSE-PWR G101 GAP-CLOSE-PWR 1 C443 SCD1U50V3ZY-GP DY 1 Panasonic 220uF ESR=15mohm Iripple=2.7A 51124_GND DY R781 51124_PGD1 51124_PGD2 TRIP1 TRIP2 38,40,43,48 PGND1 PGND2 GND GND 18 13 25 DY DRVH1 DRVH2 21 10 R786 51124_TONSEL 51124_DRVH1 51124_DRVH2 51124_V5FILT 10KR2J-3-GP R788 0R0402-PAD 51124_GND 51124_GND 51124_DRVL2 1 TPS51124RGER-GPU1 51124_TRIP1 51124_TRIP2 CPUCORE_ON 24 LL1 LL2 17 14 2 0R0402-PAD 51124_DRVL1 R790 20KR3F-GP 51124_GND 2C878 G105 51124_VBST1 GAP-CLOSE-PWR SCD1U50V3ZY-GP IND-3D3UH-55-GP 51124_LL2 2 C879 51124_VBST2 51124_GND C447 SCD1U50V3ZY-GP DY Vtrip(mV)=Rtrip(Kohm)*10(uA) Iocp=(Vtrip/Rdson)+((1/(2*L*f))*((Vin-Vout)*Vout)/Vin)) R794 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 75KR3F-GP ENG SCD1U50V3ZY-GP 1 TC10 R793 1 DY 51124_VFB2 C880 30K1R3F-GP 20 11 20KR3F-GPR789 20KR3F-GP R789 51124_GND 51124_LL1 ENG SC33P50V3JN-GP S S S G 51124_DRVL2 1D05V_PWR D D D D U39 AO4422-1-GP 51124_GND Voutsetting=1.051V L34 EC424 OCP>14A SCD1U25V3ZY-1GP SE220U2VDM-8GP 51124_LL2 SC10U35V0ZY-1GP S S S G 51124_DRVH2 1D05V Iomax=7A C445 2 SC10U35V0ZY-1GP C446 D D D D U40 AO4422-1-GP 1 51124_GND EN1 EN2 DY C877 SCD01U16V3KX-GP DCBATOUT_51124 DY C876 SCD01U16V3KX-GP 51124_LL1 51124_LL2 23 R784 TONSEL DRVL1 DRVL2 51124_EN1_1 51124_EN2_1 0R0402-PAD 0R0402-PAD V5FILT V5IN R785 R787 15 16 VBST1 VBST2 51124_V5FILT 0R0402-PAD PGOOD1 PGOOD2 51124_GND 16,31,43 PM_SLP_S5# 16,18,30,31,36,43,52 PM_SLP_S3# VO1 VO2 U44 R783 19 12 C875 SC1U10V3ZY-6GP GAP-CLOSE-PWR 1D05V_PWR 1D8V_PWR 51124_VFB2 51124_VFB1 GAP-CLOSE-PWR G86 R782 3D3R3J-L-GP VFB1 VFB2 GAP-CLOSE-PWR G88 22 51124_VFB1 1D8V_PWR 100KR2J-1-GP 1 GAP-CLOSE-PWR G87 5V_S5 GAP-CLOSE-PWR G84 1 R779 39K2R2F-L-GP 3D3V_S0 GAP-CLOSE-PWR G91 DY D28 GAP-CLOSE-PWR GAP-CLOSE-PWR G92 1D8V_S3 TC11 51124_DRVL1 1D8V / 7.0A OCP>=14A IND-3D3UH-55-GP K GAP-CLOSE-PWR G32 C874 GAP-CLOSE-PWR G85 SC4D7U10V5ZY-3GP C426 U42 AO4422-1-GP SSM24PT-GP G90 1 S S S G GAP-CLOSE-PWR G31 L35 A GAP-CLOSE-PWR G30 1 ENG 51124_DRVH1 51124_LL1 GAP-CLOSE-PWR G29 C425 SC33P50V3JN-GP 1D05V_S0 GAP-CLOSE-PWR G28 D D D D 1D05V_PWR EC444 SCD1U25V3ZY-1GP S S S G 1D05V_S0/7A OCP>=14A 1 D D D D U43 AO4422-1-GP G27 DCBATOUT_51124 DCBATOUT 51124_GND Vout=0.75V*(R1+R2)/R2 Panasonic 220uF ESR=15mohm Iripple=2.7A TONSEL GND OPEN V5FILT 230k/CH1 283k/CH2 283k/CH1 346k/CH2 346k/CH1 423k/CH2 Title TPS51124 1D8V_S3/1D05V_S0 Size A3 Document Number Date: Tuesday, January 10, 2006 Rev -1 AG1 Sheet 41 of 53 MAX8725_PDS AD+ ID = 10A @ VGS = 10V DCBATOUT U61 AC_IN Threshold 2.089V Max G MAX8725_ACOK 2 1 SC10U35V0ZY-1GP SC10U35V0ZY-1GP 8725_CSIP CSIN BATT GND 17 16 15 8725_CSIN 84.27002.L04 D 2N7002-8-GP Q31 S 1st BTY MAX8725_CLS R490 20KR2F-L-GP Pre-CHG_I = 305mA BATA_CHG_I = (0.075/R477)*(VICTL/3.6) =3.0A BATB_CHG_I = (0.075/R477)*(VICTL/3.6) =2.46A SCD1U25V3ZY-1GP ISOURCE_MAX = (0.075/R465)*(VCLS/VREF) =4.1A So,Constant Power=19V*4.1A=77.9W EC49 SCD1U25V3ZY-1GP EC50 1 G15 GAP-CLOSE A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Current limit setting: 85W(85W/20V=4.25A) B CHG_PWR-3 CHARGER_MAX8725 Size A3 Document Number Rev AG1 Date: Tuesday, January 10, 2006 DY R488 15K4R2F-GP 31 C29 C881 SC1KP25V3MX-GP V_REF :4.2235V (=2.8V = Cell V( MODE ) = 1.8V = Cell MAX8725_ACIN 11 10 DHIV PDL LDO C558 100KR2J-1-GP SC1U10V3ZY-6GP CHG_V_PWM MAX8725_ICTL MAX8725_MODE PDS SRC DCIN C51 S S S G 31 DY R503 When V(ICTL)VCELL=VBAT/CELL =VREF+(VVCTL-1.8) /9.52 =4.1998V G56 GAP-CLOSE G57 GAP-CLOSE AC_IN > 2.089V > AC DETECT D D D D 2 R507 13KR2F-GP Near MAX1909 Pin U16 S S S G 1 C30 SC1U10V3ZY-6GP Near MAX1909 Pin 24 MAX8725_ACIN R465 D01R3720F-2-GP C567 SC1U50V5ZY-1-GP 2 C549 AO4407-1-GP SCD1U50V3KX-GP AD+_TO_SYS 1 R489 100KR2F-L1-GP D D D D D S S S G SCD1U50V3ZY-GP -1 Sheet 42 of 53 A B C D E 1D5V_S0 Iomax=4.0A R27 1KR2F-3-GP GAP-CLOSE-PWR FB 2 1D5V_S0 TC1 ST100U4VBM-L1-GP APL5912-KAC-GP 74.05912.A71 5912_FB SO-8-P DDR_VREF_S0 APL5331_1D2V_VREF R29 VIN VREF VCNTL GND GND VOUT NC NC NC GAP-CLOSE-PWR TC2 ST100U4VBM-L1-GP APL5331KAC-TRLGP C774 SC10U10V5ZY-1GP 74.05331.B31 74.51100.079 C775 SC10U10V5ZY-1GP Vout=1.8V*R2/(R1+R2) Trace Length=1cm (500mils) Trace Width=8mils Trace Resistance>25mohm SO-8-P 2nd source: 74.02997.079 1D2V_S0 2K2R2F-GP C76 SCD1U16V2ZY-2GP -1 Modify 11 TPS51100DGQR-GP DY SCD1U16V2ZY-2GP C772 SC10U10V5ZY-1GP C771 DDR_VREF_S3 GAP-CLOSE-PWR G22 1D2V_PWR U7 GAP-CLOSE-PWR GAP-CLOSE-PWR G21 R30 1KR2F-3-GP 1 GAP-CLOSE-PWR G93 Vo(cal.)=1.200V 2 GAP-CLOSE-PWR G94 GND PM_SLP_S3# VIN VDDQSNS S5 VLDOIN GND VTT S3 PGND VTTREF VTTSNS 10 16,31,41 PM_SLP_S5# U74 GAP-CLOSE-PWR G19 2 G95 1 C18 SCD1U16V2ZY-2GP 1D8V_S0 C429 SC1U10V3ZY-6GP C432 SC10U10V5ZY-1GP 2 0D9V_PWR C565 SC10U10V5ZY-1GP 1D8V_S3 G20 5V_S5 1 0D9V Iomax=1A 5V_S5 Trace Length=3cm Trace Width=5mils Trace Resistance>80mohm 1D2V_S0 Iomax=2A 1D8V_S0 TC3 ST100U4VBM-L1-GP R204 2KR2F-3-GP Vo=0.8*(1+(R1/R2)) 16,18,30,31,36,41,52 C239 R165 1K78R3F-GP VOUT VOUT OCP=6A Vo(cal.)=1.512V Rh/Rl=(Vout/0.8)-1 EN VIN VIN SCD01U16V2KX-3GP GAP-CLOSE-PWR G16 DY 1 PM_SLP_S3# POK 1 GAP-CLOSE-PWR G17 GND R28 2K21R3F-L-GP 0R0402-PAD 38,40,41,48 CPUCORE_ON 74.05332.B31 U22 R202 2 1 C237 SC10U10V5ZY-1GP 2D5V_S0 G18 C271 SC10U10V5ZY-1GP Vo (cal.)=2.568V 2D5V_PWR C238 SC1U10V3ZY-6GP VCNTL 2 C40 SC10U10V5ZY-1GP APL5332KAC-TRLGP VIN BS FB VOUT NC#8 NC#7 GND NC#5 GND U6 1D8V_S3 5V_S5 3D3V_S0 2D5V Iomax=1A 4 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title 0D9V/1D2V/1D5V/2D5V Size A3 Document Number Date: Tuesday, January 10, 2006 A B C D Rev -1 AG1 Sheet E 43 of 53 ADAPTER IN CIRCUIT AD+ DCIN1 SCD47U50V5ZY A EC55 SCD1U50V3ZY-GP R469 330KR2F-L-GP 1 D3 C550 U62 S S S G D D D D D AO4407-1-GP AD+_G MH1 EC51 2 SCD1U10V2KX-4GP SCD1U50V3ZY-GP EC56 K AD+_JK DC-JACK116-GP 22.10037.C61 R470 100KR2F-L1-GP Q32 R2 R1 C C B E D MMPZ5250BPT-GP 31 PDTA144EU-1GPU Q5 CHT2222APT-GP B AD_OFF E connect to KBC C C MAIN BATTERY CONNECTOR 2 KBC_3D3V_AUX 3D3V_AUX_S5 D10 BAV99PT-GP-U DY DY D9 BAV99PT-GP-U D8 BAV99PT-GP-U 83.00099.K11 BAT1 R73 100KR2F-L1-GP RN8 31 BATA_SCL 31 BATA_SDA 31,42 BATA_IN# BATA_CLK_1 3BATA_DAT_1 SRN33J-5-GP-U 1 C560 SCD1U50V3ZY-GP C561 DUMMY-C3 SYN-CON7-15-GP 20.80352.007 B DY EC9 SC1KP25V3MX-GP DY EC10 SCD1U10V2KX-4GP DY EC11 B SCD1U10V2KX-4GP BT+ A A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title AD/BATT CONN Size A3 Document Number Rev AG1 Date: Tuesday, January 10, 2006 -1 Sheet 44 of 53 U70A STRAPS PART OF PCIE TEST PADS PCIE TEST POINTS MUST BE WITHIN 250 MILS OF THE ASIC BALL WITH POSITIVE AND NEGATIVE SIGNALS THE SAME DISTANCE PEG_TXP0 PEG_TXN0 AJ31 AH31 PCIE_RX0P PCIE_RX0N PEG_TXP1 PEG_TXN1 AH30 AG30 PCIE_RX1P PCIE_RX1N PEG_TXP2 PEG_TXN2 AG32 AF32 PCIE_RX2P PCIE_RX2N PEG_TXP3 PEG_TXN3 AF31 AE31 PCIE_RX3P PCIE_RX3N PEG_TXP4 PEG_TXN4 AE30 AD30 D PEG_TXP5 PEG_TXN5 PEG_TXP6 PEG_TXN6 TPAD28 TP72 TPAD28 TP73 AC31 AB31 AB30 AA30 PCIE_RX5P PCIE_RX5N PCIE_RX6P PCIE_RX6N PCIE_RX7P PCIE_RX7N I N T E R F A C E PCIE_TX0P PCIE_TX0N 1 SCD1U16V2KX-3GP PEG_RXP0 SCD1U16V2KX-3GP PEG_RXN0 STRAP_B_PTX_PWRS_ENB GPIO0 PCIE_TX1P PCIE_TX1N AJ25 AH25 C75 C74 1 SCD1U16V2KX-3GP PEG_RXP1 SCD1U16V2KX-3GP PEG_RXN1 STRAP_B_PTX_DEEMPH_EN GPIO1 PCIE_TX2P PCIE_TX2N AH28 AG28 C117 C118 SCD1U16V2KX-3GP PEG_RXP2 SCD1U16V2KX-3GP PEG_RXN2 PCIE_TX3P PCIE_TX3N AG27 AF27 C114 C113 SCD1U16V2KX-3GP PEG_RXP3 SCD1U16V2KX-3GP PEG_RXN3 PCIE_TX4P PCIE_TX4N AF25 AE25 C122 C121 SCD1U16V2KX-3GP PEG_RXP4 SCD1U16V2KX-3GP PEG_RXN4 PCIE_TX5P PCIE_TX5N AE28 AD28 PCIE_TX6P PCIE_TX6N AD27 AC27 PCIE_TX7P PCIE_TX7N AC25 AB25 PCIE_TX8P PCIE_TX8N AB28 AA28 C170 C171 SCD1U16V2KX-3GP PEG_RXP8 SCD1U16V2KX-3GP PEG_RXN8 ROMIDCFG(3:0) GPIO[9,13:11] MEMORY APERTURE SIZE GPIO[13:11] C115 C116 C159 C161 SCD1U16V2KX-3GP PEG_RXP5 SCD1U16V2KX-3GP PEG_RXN5 Y31 W31 PCIE_RX9P PCIE_RX9N PCIE_TX9P PCIE_TX9N AA27 Y27 C163 C162 SCD1U16V2KX-3GP PEG_RXP9 SCD1U16V2KX-3GP PEG_RXN9 PEG_TXP10 PEG_TXN10 W30 V30 PCIE_RX10P PCIE_RX10N PCIE_TX10P PCIE_TX10N Y25 W25 C158 C157 SCD1U16V2KX-3GP PEG_RXP10 SCD1U16V2KX-3GP PEG_RXN10 PCIE SIGNALS CONNECT TO ROOT COMPLEX PEG_TXP11 PEG_TXN11 V32 U32 PCIE_RX11P PCIE_RX11N PCIE_TX11P PCIE_TX11N W28 V28 C167 C168 SCD1U16V2KX-3GP PEG_RXP11 SCD1U16V2KX-3GP PEG_RXN11 REFER TO PCI EXPRESS DESIGN GUIDE FOR RECOMMENDED AC COUPLING CAPS PLACEMENT ALONG THE TX INTERCONNECT PEG_TXP12 PEG_TXN12 U31 T31 PCIE_RX12P PCIE_RX12N PCIE_TX12P PCIE_TX12N V27 U27 C169 C166 SCD1U16V2KX-3GP PEG_RXP12 SCD1U16V2KX-3GP PEG_RXN12 PEG_TXP13 PEG_TXN13 T30 R30 PCIE_RX13P PCIE_RX13N PCIE_TX13P PCIE_TX13N U25 T25 C160 C222 SCD1U16V2KX-3GP PEG_RXP13 SCD1U16V2KX-3GP PEG_RXN13 SCD1U16V2KX-3GP PEG_RXP14 SCD1U16V2KX-3GP PEG_RXN14 SCD1U16V2KX-3GP PEG_RXP15 SCD1U16V2KX-3GP PEG_RXN15 PEG_TXN[15 0] PEG_RXN[15 0] PEG_TXP[15 0] PEG_TXN[15 0] GPIO5 R32 P32 PCIE_RX14P PCIE_RX14N PCIE_TX14P PCIE_TX14N T28 R28 PEG_TXP15 PEG_TXN15 P31 N31 PCIE_RX15P PCIE_RX15N PCIE_TX15P PCIE_TX15N R27 P27 C220 C219 AL28 AK28 PCIE_REFCLKP PCIE_REFCLKN B 7,16,20,26,30,31,32,34,35 PLT_RST1# R111 100R2J-2-GP VGA_RST# 2 SC100P50V2JN-3GP C420 PCIE_TEST AG24 PERSTB AA24 PCIE_TEST AF24 PERSTB_MASK PCIE_CALRN PCIE_CALRP AE24 AD24 PCIE_CALRN PCIE_CALRP PCIE_CALI AB24 PCIE_CALI DEBUG ACCESS R112 2PERSTB_MASK 10KR2F-2-GP Tie To VSS M52P-GP 71.0M52P.00U M54P:71.0M54P.A0U M56P:71.0M56P.B0U 23 DO NOT INSTALL 10K RESISTORS NO DEBUG ACCESS (M26X) GPIO8 DO NOT INSTALL 10K RESISTORS DON'T FORCE COMPLIANCE STATE(M52P,M54P,M56P) MEMID SERIAL FLASH ROM TYPE (M26X,M52P,M54P,M56P) - SERIAL M25P10 ROM 1011 IF NO ROM GPIO11(M26X) AND GPIO12,13(M52,M54,M56) SET MEMORY APERTURE SIZE SEE M26X,M54X,M56X DATA BOOK FOR MEMORY,FRAME BUFFER APERATURE SETTINGS TBD MEMORY TYPE AND SPEED SELECT TBD H2SYNC V2SYNC GENERICC NO STRAP FUNCTION RSVD PCIE_TEST NO STRAP FUNCTION C DO NOT INSTALL 10K RESISTORS ATI FEATURE NOT ENABLED (M52P,M54P,M56P) NO STRAP (M26X) ATI FEATURE NOT ENABLED (M52P,M54P,M56P) NO STRAP (M26X) 3D3V_S0 1D2V_S0 22 21 20 MEM_ID0 MEM_ID2 MEM_ID1 MEM_ID3 1 0 1 INSTALL 10K RESISTORS (3:0) R538 2KR2F-3-GP R133 562R3F-GP R135 1K47R3F-GP FOR M26X PCIE_CALRN = 100R PCIE CALRP = 150R PCIE CALI = 10K FOR M52P,M54P,M56P PCIE_CALRN = 2K PCIE CALRP = 562R PCIE CALI = 1.47K DO NOT INSTALL 10K RESISTOR NO ATI FEATURE ENABLED (M52P,M54P,M56P) Calibration Clock CLK_PCIE_PEG CLK_PCIE_PEG# CLK_PCIE_PEG CLK_PCIE_PEG# DO NOT INSTALL 10K RESISTORS NO ATI FEATURE ENABLED NORMAL RANGE (M26X) RSVD C221 C223 D GPIO6 MEM_TYPE PEG_TXP14 PEG_TXN14 TBD NO ATI FEATURE ENABLED (M52P,M54P,M56P) FORCE_COMPLIANCE PEG_TXP9 PEG_TXN9 PEG_TXP[15 0] TRANSMITTER DE-EMPHASIS ENABLE DEPENDS ON PCIE CHIPSET BEING USED FOR M26X,M5X INSTALL WITH ATI RS480,RS400,RX480, RC410,RS482 CHIPSETS FOR M26X ONLY DO NOT INSTALL WITH INTEL 915PM CHIPSET NO DEBUG ACCESS (M52P,M54P,M56P) COMMON MODE RANGE SCD1U16V2KX-3GP PEG_RXP7 SCD1U16V2KX-3GP PEG_RXN7 INSTALL 10K RESISTOR DO NOT FORCE COMPLIANCE STATE QUICKLY (M26X) RSVD C164 C165 TRANSMITTER POWER SAVINGS ENABLE - FULL TX OUTPUT SWING NOT REVERSED LANE (M26X) GPIO4 STRAP_FORCE_COMPLIANCE sets the desired PCIE PLL bandwidth for M5x parts SCD1U16V2KX-3GP PEG_RXP6 SCD1U16V2KX-3GP PEG_RXN6 PCIE_RX8P PCIE_RX8N PEG_RXN[15 0] GPIO(3:2) DEBUG ACCESS AA32 Y32 PEG_RXP[15 0] RSVD REVERSE LANES RECOMMENDED DESCRIPTION OF RECOMMENDED SETTING C72 C73 PEG_TXP8 PEG_TXN8 PEG_RXP[15 0] C PEG_TXP7 PEG_TXN7 1 AD32 AC32 PCIE_RX4P PCIE_RX4N P C I E X P R E S S PIN AK27 AJ27 1 1 0 1 1 0 0 0 0 0 0 MEM 64M 64M 128M 256M 128M 256M 128M 256M SIZE 16M*16 16M*16 16M*16 32M*16 16M*16 32M*16 16M*16 32M*16 VENDOR CHIPs Infineon Hynix Samsung Samsung Infineon Infineon Hynix Hynix x2 x2 x4 x4 x4 x4 x4 x4 46 46 46 46 46 46 46 46 46 46 46 46 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO8 GPIO11 GPIO12 GPIO13 GPIO9 46 46 46 46 46 46 46 MEM_ID3 MEM_ID2 MEM_ID1 MEM_ID0 DAC2_HSY DAC2_VSY GENERICC R64 R52 R53 R58 R49 R51 1 DY R56 DY R66 DY R50 256M R54 DY R65 R61 DY GPIO[9,13:11]=0000 for 128M DY R59 DY R55 1 128In256 R63 R60 128Hy256R106 DY R104 DY R537 DY R151 PCIE_TEST DY When no ROM GPIO[13:12] GPIO[13:12] GPIO[13:12] GPIO[13:12] GPIO[13:12] VGA THERMAL SENSOR DY DY DY 2 2 2 2 2 2 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 2 2 2 2 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP 10KR2J-3-GP B is attached, GPIO[9] is set to is used to select the frame buffer aperture size = 00: 128M frame buffer, same as ROM strap 00 = 01: 256M frame buffer, same as ROM strap 01 = 10: 64M frame buffer, same as ROM strap 10 = 11: reserved, same as ROM strap 11 A A Wistron Corporation Place near GPU 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title IT IS REQUIRED TO DESIGN IN A THERMAL SENSOR TO FACILITATE THERMAL EVALUATION AND TO PROTECT THE ASIC ATI M5X-P PCIE 1/4 Size A3 Document Number Rev AG1 Date: Tuesday, January 10, 2006 SD Sheet 45 of 53 U70B AK9 AJ9 & TX4M TX4P AK11 AJ11 M U L T I M E D I A TX5M TX5P AK12 AJ12 13 13 ANY UNUSED GPIO CAN OPTIONALLY MEMORY TYPE CONFIG STRAPS C137 2K2R2J-2-GP 3D3V_S0 G792_DXN3 FOR M26X MPVDD CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO VDDC AG12 C65 SC2200P50V2KX-2GP AH12 VGA_PVDD AJ14 C98 SC1U6D3V2KX-GP AH14 2 VGA_MPVDD A6 A5 C656 C657 SC1U6D3V2KX-GP SCD1U10V2KX-4GP 2 0R0603-PAD R591 0R0603-PAD 1 C66 SC10U10V5ZY-1GP R57 AC8 19 VGA_VREF G792_DXP3 19 2 52 GPIO_PWRCNTL PLACE VREF DIVIDER AND CAP CLOSE TO ASIC VGA_CORE_S0 GPIO11 GPIO12 GPIO13 1 45 45 SCD1U10V2KX-4GP45 VGA_XTALIN TPAD28 TP71 R132 1KR2J-1-GP VOLTAGE DIVIDER 3.3V MEM SS MODOUT TO 1.2V XTALIN/OUT 3D3V_S0 VGA_TESTEN R94 10KR2J-3-GP AL25 AM25 AVSSQ AVSSN_1 AVSSN_2 AK23 AK25 AJ24 VDD1DI AM23 VSS1DI AL23 R2 DAC2 (TV/CRT2) G2 B2 AK15 AM15 AL15 H2SYNC V2SYNC AF15 AG15 Y C COMP AJ15 AJ13 AH15 VREFG DMINUS PVDD PVSS Thermal Diode R2SET AK14 A2VDD_1 A2VDD_2 AM16 AL16 A2VSSN_1 A2VSSN_2 AM17 AL17 NC_A2VDDQ AL14 PLL & XTAL MPVDD MPVSS AL26 1AM26 XTALIN XTALOUT AG14 PLLTEST AG22 TESTEN AC7 ROMCSb AK17 AJ19 AF18 AH17 AG17 AG19 AH19 M52P-GP 510R2F-L-GP RSET AVDD_1 AVDD_2 Monitor Interface A2VSSQ AK13 VDD2DI AJ16 VSS2DI AJ17 HPD1 VGA_AVDD AH22 AH23 Test DDC2DATA DDC2CLK AH13 AG13 ROM DDC3DATA DDC3CLK AE12 AF12 GENERICC AE23 LPVSS AE18 LVSSR_10 LVSSR_9 LVSSR_8 AF22 AF17 AF21 LVSSR_1 LVSSR_2 LVDS PLL LVSSR_3 and I/O LVSSR_4 GND LVSSR_5 LVSSR_6 LVSSR_7 External SSC LVDS PLL and I/O GND VGA_VDD1DI C103 DAC2_HSY DAC2_VSY C R1101 R1091 R107 R539 HCB1608KF121T30-GP C107 2D5V_S0 FOR M26X AVDD CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V SC1U6D3V2KX-GP C106 C104 R108 0R0603-PAD 2D5V_S0 FOR M26X VDD1DI CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V DAC2 CAN BE TV SIGNALS OR SECONDARY CRT SIGNALS AS CONTROLLED BY AN INTERNAL MUX DAC2_HSY 45 DAC2_VSY 45 ATI_TV_LUMA 14 ATI_TV_CRMA 14 ATI_TV_COMP 14 VGA_TV_RSET R102 VGA_A2VDD VGA_A2VDDQ VGA_VDD2DI C94 AF11 R743 100KR2J-1-GP DDC1DATA DDC1CLK DY adjust SWING at 1.2v GPIO_0 General GPIO_1 Purpose GPIO_2 I/O GPIO_3 GPIO_4 GPIO_5 GPIO_6 GPIO_7_BLON GPIO_8 GPIO_9 GPIO_10 GPIO_11 GPIO_12 GPIO_13 GPIO_14 GPIO_15 GPIO_16 GPIO_17 NC_AB6 DPLUS 1KR2F-3-GP VGA_CRT_RSET R105 715R2F-GP C101 TPAD28 TP70 C99 R103 C102 0R3-0-U-GP SC1U6D3V2KX-GP R62 C100 0R3-0-U-GP ATI_DDCDAT 14 ATI_DDCCLK 14 B 2D5V_S0 TV SCD1U10V2KX-4GP 2D5V_S0 TPAD28 TP6 VGA_GENERICB R134 AL22 SCD1U10V2KX-4GP FOR M26X PVDD CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V AD4 AD2 AD1 AD3 AC1 AC2 AC3 AB2 AC6 AC5 AC4 AB3 AB4 AB5 AD5 R484 POW_SW AB8 10KR2J-3-GP VGA_GPIO16 AA8 1VGA_ALERT# AB7 R48 AB6 GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO8 GPIO9 R127 499R2F-2-GP MEM_ID3 MEM_ID2 MEM_ID1 MEM_ID0 AF23 SCD1U10V2KX-4GP B 45 45 BE45 45 45 45 45 45 45 45 45 3D3V_S0 R91 45 499R2F-2-GP 45 EDID_DAT EDID_CLK EDID_DAT EDID_CLK GENERICB 2D5V_S0 ATI_HSY 14 ATI_VSY 14 RN14 SRN4K7J-8-GP AJ23 AJ22 AK22 FOR M26X TXVDDR CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V ATI_RED 14 ATI_GREEN 14 ATI_BLUE 14 No Spread HSYNC VSYNC GENERICA 0R0603-PAD +-1.5% H FOR M26X TPVDD CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V L H AK24 AM24 AL24 H 2D5V_S0 +-1.0% R G B DAC / CRT D R523 1 H AJ7 AK7 AL7 AM7 AK8 L 3D3V_S0 TXVSSR_1 TXVSSR_2 TXVSSR_3 TXVSSR_4 TXVSSR_5 R524 0R0603-PAD C581 SCD1U10V2KX-4GP SC1U6D3V2KX-GP SC1U6D3V2ZY-GP L VGA_TXVDDR C603 C604 SC1U6D3V2KX-GP L AJ6 AK6 AL6 AM6 ANY UNUSED GPIO CAN OPTIONALLY BE PANEL TYPE CONFIG STRAPS Center Spread +-0.5% SEL1 SEL0 TXVDDR_1 TXVDDR_2 TXVDDR_3 TXVDDR_4 Modulation Rate A 1KR2J-1-GP DVPCNTL_0 DVPCNTL_1 DVPCNTL_2 DVPCLK DVPDATA_0 DVPDATA_1 DVPDATA_2 DVPDATA_3 DVPDATA_4 DVPDATA_5 DVPDATA_6 DVPDATA_7 DVPDATA_8 DVPDATA_9 DVPDATA_10 DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14 DVPDATA_15 DVPDATA_16 DVPDATA_17 DVPDATA_18 DVPDATA_19 DVPDATA_20 DVPDATA_21 DVPDATA_22 DVPDATA_23 AL8 C582 SC1U6D3V2KX-GP MB88154_XO 82.30034.211 C580 AF2 AF1 AF3 AG1 AG2 AG3 AH2 AH3 AJ2 AJ1 AK2 AK1 AK3 AL2 AL3 AM3 AE6 AF4 AF5 AG4 AJ3 AH4 AJ4 AG5 AH5 AF6 AE7 AG6 R93 TPVSS VGA_TPVDD X7 XTAL-27MHZ-31-GP NC_DVOVMODE_0 NC_DVOVMODE_1 AM8 SC1U6D3V2ZY-GP MB88154_XI 12 SC27P50V2JN-2-GP SC27P50V2JN-2-GP C 1MR2J-1-GP 147R2F-GP TPVDD C579 R519 DVPCNTL,DVPDATA[23 0] FOR M26X ARE CONFIGURED FOR CONNECT TO +1.8V OR VSS +3.3V SIGNALING MODE TO DEFINE DVO SIGNAL LEVEL ON THIS DESIGN FOR M52P,M54P,M56P AK4 AL4 NOT CONNECTED 1 R113 VGA_XTALIN DUAL LINK IS ONLY SUPPORTED ON M56P DO NOT CONNECT TXM,P[3:5] WITH M52P,M54P,M26X 150R2F-1-GP 150R2F-1-GP 150R2F-1-GP TX3M TX3P R1011 R981 R100 AL12 AM12 TV 150R2F-1-GP 150R2F-1-GP 150R2F-1-GP TX2M TX2P AL11 AM11 V I D E O 2 MB88154PNF-JN-GP 71.88154.A0A 180R2F-1-GP C576 Expand GPIO MB88154_XI GPIO_34 GPIO_33 GPIO_32 GPIO_31 GPIO_30 GPIO_29 GPIO_28 GPIO_27 GPIO_26 GPIO_25 GPIO_24 GPIO_23 GPIO_22 GPIO_21 GPIO_20 GPIO_19 GPIO_18 VIP Host/External TMDS VGA_GPIO16 3D3V_SS_S0 2 CKOUT VDD VSS XIN 1 0R2J-2-GP SEL1 REFOUT SEL0 XOUT R114 R493 R521 0R2J-2-GP VGA_XTALIN_1 MB88154_XO5 SCD1U10V2KX-4GP 2 D AG8 AH7 AG9 AH8 AJ8 AH9 AG10 AF10 AH6 AF8 AF7 AE9 AE10 AG7 AF9 AF13 AE13 U67 TX1M TX1P R518 0R3-0-U-GP DY TX0M TX0P R522 DUMMY-R2 AL9 AM9 AK10 AL10 SCD1U10V2KX-4GP TXCM TXCP Integrated TMDS 3D3V_S0 R520 0R2J-2-GP PART OF SC1U6D3V2KX-GP 3D3V_S0 FOR M26X A2VDDQ CONNECT TO +1.8V FOR M52P,M54P,M56P IT IS NO CONNECT TV 2D5V_S0 FOR M26X VDD2DI CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V For CRT For DVI A For THERMAL SENSOR GENERICC Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C 45 FOR M26X GENERICC NO CONNECT OR EXT SPREAD SPECTRUM INPUT FOR M52P,M54P,M56P IT IS GPIO Title ATI M5X-P IO 2/4 Size A3 Document Number Rev AG1 Date: Tuesday, January 10, 2006 -1M Sheet 46 of 53 H31 J29 J26 G23 E21 B15 D14 J17 QSA_0 QSA_1 QSA_2 QSA_3 QSA_4 QSA_5 QSA_6 QSA_7 J31 K29 K25 F23 D20 B16 D16 H15 QSA_0B QSA_1B QSA_2B QSA_3B QSA_4B QSA_5B QSA_6B QSA_7B K31 K28 K26 G24 D21 C16 D15 J15 ODTA ODTA1 F29 D24 CLKA0 CLKA0b D31 E31 CKEA0 B30 RASA0b B28 CASA0b C29 WEA0b B31 CSA0b_0 CSA0b_1 B29 C28 MDB0 MDB1 MDB2 MDB3 MDB4 MDB5 MDB6 MDB7 MDB8 MDB9 MDB10 MDB11 MDB12 MDB13 MDB14 MDB15 MDB16 MDB17 MDB18 MDB19 MDB20 MDB21 MDB22 MDB23 MDB24 MDB25 MDB26 MDB27 MDB28 MDB29 MDB30 MDB31 MDB32 MDB33 MDB34 MDB35 MDB36 MDB37 MDB38 MDB39 MDB40 MDB41 MDB42 MDB43 MDB44 MDB45 MDB46 MDB47 MDB48 MDB49 MDB50 MDB51 MDB52 MDB53 MDB54 MDB55 MDB56 MDB57 MDB58 MDB59 MDB60 MDB61 MDB62 MDB63 1D8V_S0 R581 B12 C12 B11 C11 C8 B7 C7 B6 F12 D12 E11 F11 F9 D8 D7 F7 G12 G11 H12 H11 H9 E7 F8 G8 G6 G7 H8 J8 K8 L8 K9 L9 K5 L4 K4 L5 N5 N6 P4 R4 P2 R2 T3 T2 W3 W2 Y3 Y2 T4 R5 T5 T6 V5 W5 W6 Y4 R8 T8 R7 T7 V7 W7 W8 W9 DQB_0 DQB_1 DQB_2 DQB_3 DQB_4 DQB_5 DQB_6 DQB_7 DQB_8 DQB_9 DQB_10 DQB_11 DQB_12 DQB_13 DQB_14 DQB_15 DQB_16 DQB_17 DQB_18 DQB_19 DQB_20 DQB_21 DQB_22 DQB_23 DQB_24 DQB_25 DQB_26 DQB_27 DQB_28 DQB_29 DQB_30 DQB_31 DQB_32 DQB_33 DQB_34 DQB_35 DQB_36 DQB_37 DQB_38 DQB_39 DQB_40 DQB_41 DQB_42 DQB_43 DQB_44 DQB_45 DQB_46 DQB_47 DQB_48 DQB_49 DQB_50 DQB_51 DQB_52 DQB_53 DQB_54 DQB_55 DQB_56 DQB_57 DQB_58 DQB_59 DQB_60 DQB_61 DQB_62 DQB_63 read strobe DQMAb_0 DQMAb_1 DQMAb_2 DQMAb_3 DQMAb_4 DQMAb_5 DQMAb_6 DQMAb_7 Ch-B FOR M52P,M54P,M26X PIN H2 IS MAB12 (BA0) PIN H3 IS MAB13 (BA1) PIN D5 IS MAB15 (BA2) PIN F5 IS MAB14 FOR M56P PIN H2 IS MA14 (BA0) PIN H3 IS MA15 (BA1) PIN D5 IS MA13 (BA2) PIN F5 IS MAB12 Part of D26 F28 D28 D25 E24 E26 D27 F25 C26 B26 D29 B27 E27 E29 B25 C25 MAB_0 MAB_1 MAB_2 MAB_3 MAB_4 MAB_5 MAB_6 MAB_7 MAB_8 MAB_9 MAB_10 MAB_11 MAB_12 MAB_13 MAB_14 MAB_15 G4 E6 E4 H4 J5 G5 F4 H6 G3 G2 D4 F2 F5 D5 H2 H3 DQMBb_0 DQMBb_1 DQMBb_2 DQMBb_3 DQMBb_4 DQMBb_5 DQMBb_6 DQMBb_7 B8 D9 G9 K7 M5 V2 W4 T9 MAB0 MAB1 MAB2 MAB3 MAB4 MAB5 MAB6 MAB7 MAB8 MAB9 MAB10 MAB11 B_BA0 B_BA1 50,51 50,51 DQMB#0 DQMB#1 DQMB#2 DQMB#3 DQMB#4 DQMB#5 DQMB#6 DQMB#7 RDQSB0 RDQSB1 RDQSB2 RDQSB3 RDQSB4 RDQSB5 RDQSB6 RDQSB7 B9 D10 H10 K6 N4 U2 U4 V8 QSB_0B QSB_1B QSB_2B QSB_3B QSB_4B QSB_5B QSB_6B QSB_7B B10 E10 G10 J7 M4 U3 V4 V9 WDQSB0 WDQSB1 WDQSB2 WDQSB3 WDQSB4 WDQSB5 WDQSB6 WDQSB7 D6 J4 ODTB0 ODTB1 ODTB ODTB1 MAB12_14 50,51 TP10 TPAD28 QSB_0 QSB_1 QSB_2 QSB_3 QSB_4 QSB_5 QSB_6 QSB_7 CLKB0 CLKB0b B4 B5 CLKB0 CLKB0# CKEB0 C2 CKEB0 RASB0b E2 RASB0# CASB0b D3 CASB0# WEB0b B2 WEB0# CSB0b_0 CSB0b_1 D2 E3 CSB0_0# CSB0_1# CLKB1 CLKB1b N2 P3 CLKB1 CLKB1# D For GDDR2 50 50,51 RASB0# RASB1# 50 50,51 CASB0# CASB1# 50 50,51 WEB0# WEB1# 50 CSB0_0# 50,51 CSB1_0# 50 50,51 CKEB0 CKEB1 50 50 CLKB0 CLKB0# 51 51 CLKB1 CLKB1# RASB0# RASB1# CASB0# CASB1# WEB0# WEB1# CSB0_0# CSB1_0# C CKEB0 CKEB1 CLKB0 CLKB0# CLKB1 CLKB1# RDQSB[7 0] 50,51 RDQSB[7 0] ODTB0 50 ODTB1 50,51 DQMB#[7 0] 50,51 DQMB#[7 0] MDB[63 0] 50,51 MDB[63 0] MAB[11 0] 50,51 MAB[11 0] WDQSB[7 0] 50,51 WDQSB[7 0] B TP9 TPAD28 TP8 TPAD28 CASA1b B22 WEA1b B21 CSA1b_0 CSA1b_1 B23 C23 R590 100R2F-L1-GP-U 1D8V_S0 MVREFD_1 MVREFS_1 CKEB1 L3 CKEB1 AA3 DRAM_RST RASB1b J2 RASB1# AA5 TEST_MCLK CASB1b L2 CASB1# AA2 TEST_YCLK WEB1b M2 WEB1# AA7 MEMTEST CSB1b_0 CSB1b_1 K2 K3 CSB1_0# CSB1_1# M52P-GP B3 C3 B24 RASA1b MVREFD1 MVREFS1 C666 SCD1U10V2KX-4GP CKEA1 C22 B20 C19 CLKA1 CLKA1b 100R2F-L1-GP-U MVREFD_0 MVREFS_0 read strobe C31 C30 MAA_0 MAA_1 MAA_2 MAA_3 MAA_4 MAA_5 MAA_6 MAA_7 MAA_8 MAA_9 MAA_10 MAA_11 MAA_12 MAA_13 MAA_14 MAA_15 B DQA_0 DQA_1 DQA_2 DQA_3 DQA_4 DQA_5 DQA_6 DQA_7 DQA_8 DQA_9 DQA_10 DQA_11 DQA_12 DQA_13 DQA_14 DQA_15 DQA_16 DQA_17 DQA_18 DQA_19 DQA_20 DQA_21 DQA_22 DQA_23 DQA_24 DQA_25 DQA_26 DQA_27 DQA_28 DQA_29 DQA_30 DQA_31 DQA_32 DQA_33 DQA_34 DQA_35 DQA_36 DQA_37 DQA_38 DQA_39 DQA_40 DQA_41 DQA_42 DQA_43 DQA_44 DQA_45 DQA_46 DQA_47 DQA_48 DQA_49 DQA_50 DQA_51 DQA_52 DQA_53 DQA_54 DQA_55 DQA_56 DQA_57 DQA_58 DQA_59 DQA_60 DQA_61 DQA_62 DQA_63 write strobe C M31 M30 L31 L30 H30 G31 G30 F31 M27 M29 L28 L27 J27 H29 G29 G27 M26 L26 M25 L25 J25 G28 H27 H26 F26 G26 H25 H24 H23 H22 J23 J22 E23 D22 D23 E22 E20 F20 D19 D18 B19 B18 C17 B17 C14 B14 C13 B13 D17 E18 E17 F17 E15 E14 F14 D13 H18 H17 G18 G17 G15 G14 H14 J14 MEMORY INTERFACE A D U70D Ch-A FOR M52P,M54P,M26X PIN B25 IS MA12 (BA0) PIN C25 IS MA13 (BA1) PIN E29 IS MA15 (BA2) PIN E27 IS MA14 FOR M56P PIN B25 IS MA14 (BA0) PIN C25 IS MA15 (BA1) PIN E29 IS MA13 (BA2) PIN E27 IS MA12 Part of write strobe U70C MEMORY INTERFACE B R580 RN15 SRN4K7J-8-GP M52P-GP R714 243R3F-GP PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC R589 2 C665 SC Modify A 100R2F-L1-GP-U A SCD1U10V2KX-4GP 100R2F-L1-GP-U Wistron Corporation PLACE MVREF DIVIDERS AND CAPS CLOSE TO ASIC 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title ATI M5X-P MEM 3/4 Size A3 Document Number Rev AG1 Date: Tuesday, January 10, 2006 SC Sheet 47 of 53 VGA_VDDRH1 SC1U6D3V2KX-GP SC1U6D3V2KX-GP C151 C154 FOR M26X VDD25 CONNECT TO +1.5V FOR M52P,M54P,M56P CONNECT TO +2.5V C148 R130 0R0603-PAD C147 R136 0R0603-PAD 2D5V_S0 FOR M26X VDDPLL CONNECT TO VDDC FOR M52P,M54P,M56P CONNECT TO +1.2V R147 0R0805-PAD R152 0R0603-PAD C 1D2V_S0 VGA_CORE_S0 FOR M26X LPVDD CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V 2D5V_S0 R67 0R0805-PAD 2D5V_S0 FOR M26X LVDDR PINS AE20,AF20,AF19 CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +2.5V R131 0R0805-PAD 2D5V_S0 FOR M26X LVDDR PINS AC21,AC22,AD21,AD22,AE21,AE22 CONNECT TO +2.8V FOR M52P,M54P,M56P CONNECT TO +2.5V B C244 SC1U6D3V2KX-GP R166 0R3-0-U-GP PART OF Forward S 3D3V_S0 G D Q11 2N7002-8-GP VGA_BBN 0R2J-2-GP R149 VGA_BBP M56P 0R2J-2-GP BACK BIASING APPLIES TO M56P ONLY IF BACK BIAS NOT USED ON M56,CONNECT BBN PINS TO VSS AND BBP PINS TO VDDC BBN,BBP PINS ARE NO CONNECT FOR M26X,M54P,M52P G R148 1 VGA_CORE_S0 Y23 K15 R10 AC17 AC14 M23 V10 K18 BBN_4 BBN_3 BBN_2 BBN_1 BBP_4 BBP_3 BBP_2 BBP_1 L10 K22 AA10 VDD25_4 VDD25_5 VDD25_6 S 7,16,38 VARY_BL DIGON GENERICD Only used in dual-channel LVDS mode TXCLK_UP TXCLK_UN TXOUT_U3P TXOUT_U3N TXOUT_U2P TXOUT_U2N TXOUT_U1P TXOUT_U1N TXOUT_U0P TXOUT_U0N AJ21 AK21 AH21 AG21 AG20 AH20 AK20 AJ20 AG18 AH18 ATI_TXBCLK+ 13 ATI_TXBCLK- 13 ATI_TXBOUT2+ ATI_TXBOUT2ATI_TXBOUT1+ ATI_TXBOUT1ATI_TXBOUT0+ ATI_TXBOUT0- 13 13 13 13 13 13 LVDS channel This channel is used as the transmitting channel in single channel LVDS mode TXOUT_L0N TXOUT_L0P TXOUT_L1N TXOUT_L1P TXOUT_L2N TXOUT_L2P TXOUT_L3N TXOUT_L3P TXCLK_LN TXCLK_LP AK19 AL19 AL20 AM20 AL21 AM21 AK18 AJ18 AL18 AM18 ATI_TXAOUT0ATI_TXAOUT0+ ATI_TXAOUT1ATI_TXAOUT1+ ATI_TXAOUT2ATI_TXAOUT2+ 13 13 13 13 13 13 BLON_IN 31 ATI_LCDVDD_ON C210 C195 C142 FOR M26X GENERICD NO CONNECT OR EXT SPREAD SPECTRUM OUTPUT FOR M52P,M54P IT IS A GPIO FOR M56P IT IS A BACK BIAS REGULATOR CONTROL R129 10KR2J-3-GP A CONNECT THESE VDD25 PINS TO 2.5V FOR M52P,M54P,M56P THESE VDD25 PINS ARE NO CONNECT FOR M26X Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title ATI M5X-P Power 4/4 Size C Date: 13 ATI_TXACLK- 13 ATI_TXACLK+ 13 M52P-GP 2D5V_S0 38,40,41,43 SC1U6D3V2ZY-GP CPUCORE_ON SCD1U10V2KX-4GP VGATE_PWRGD R206 0R2J-2-GPDY SCD1U10V2KX-4GP R167 0R0402-PAD SA rework 0924 BLON_IN AD12 AE11 AD23 M56P R205 100KR2J-1-GP PWROK# Control and External SSC Compatibility D BLON CAN ALSO BE A PWM OUTPUT FOR BRIGHTNESS CONTROL U70G Q10 SI2301BDS-T1-GP DY M52P-GP 1 2 C197 C208 C149 2 2 SC1U6D3V2ZY-GP 2 SC4D7U6D3V3KX-GP 2 1 C97 C206 C201 C146 C153 SC1U6D3V2KX-GP 2 VGA_LVDDRL1 C155 M52P-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP 1 C67 C251 2 VGA_LVDDRL0 LVDDR/VDDL1_1 LVDDR/VDDL1_2 LVDDR/VDDL1_3 LVDDR/VDDL2_1 LVDDR/VDDL2_2 LVDDR/VDDL2_3 AC21 AC22 AD22 AE21 AD21 AE22 AF20 AE20 AF19 2 SC1U6D3V2KX-GP SC1KP16V2KX-GP SC1KP16V2KX-GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP SC4D7U6D3V3KX-GP 2 1 PCI-Express Core LVDDR/VDDL0_1 LVDDR/VDDL0_2 LVDDR/VDDL0_3 C202 VSSRH0 VSSRH1 VGA_VDDCI C212 A28 E1 AE19 1 R171 0R0603-PAD VDDRH0 VDDRH1 C172 SC1U6D3V2ZY-GP 1 VGA_VDDRH0 A27 F1 VGA_VDDPLL VGA_LPVDD LPVDD/VDDL0 C200 C150 SC1U6D3V2ZY-GP 1 2 I/O Internal SCD01U25V2KX-3GP 2 1SC10U6D3V5MX-3GP SCD01U25V2KX-3GP 2 SC1U6D3V2ZY-GP SCD01U25V2KX-3GP SCD01U25V2KX-3GP SCD01U25V2KX-3GP SC1U6D3V2KX-GP 2 2 2 SC1U6D3V2KX-GP SCD01U25V2KX-3GP SCD01U25V2KX-3GP 1 SC1U6D3V2KX-GP 1 SCD01U25V2KX-3GP SCD01U25V2KX-3GP SC1U6D3V2KX-GP R172 0R0603-PAD W10 T14 W17 P16 T23 K14 U19 C205 C152 SCD1U10V2KX-4GP VGA_VDDR5 C93 VDDR4 AND VDDR5 IN M26X CAN BE 1.8V OR 3.3V DEPENDING ON M26X DVOMODE OR M52P,M54P,M56P REGISTER CONFIGURATION 1D8V_S0 VDDCI_1 VDDCI_2 VDDCI_3 VDDCI_4 VDDCI_5 VDDCI_6 VDDCI_7 VGA_VDD25 C143 C144 SCD1U10V2KX-4GPSCD1U10V2KX-4GP SC1U6D3V2KX-GP SC1U6D3V2ZY-GP AC15 C145 C204 SCD1U10V2KX-4GP VDDR5_1 VDDR5_2 VDDR5_3 VDDR5_4 VDDPLL C140 C207 SCD1U10V2KX-4GP AE2 AE3 AE4 AE5 VGA_VDDR4 C96 C91 AC13 AC16 AC18 C108C110 VGA_CORE_S0 C198 SCD1U10V2KX-4GP VDDR4_1 VDDR4_2 VDDR4_3 VDDR4_4 VDD25_1 VDD25_2 VDD25_3 C111 C109 D R116 0R0805-PAD SCD1U10V2KX-4GPSCD1U10V2KX-4GP R92 0R0603-PAD AJ5 AM5 AL5 AK5 AC11 AC12 P14 U15 W14 W15 R17 R15 V15 V16 T16 U16 T17 U17 V14 R18 T18 V18 P18 P19 R19 W19 AD11 C112 R150 0R0805-PAD SCD1U10V2KX-4GP C95 VDDC_1 VDDC_2 VDDC_3 VDDC_4 VDDC_5 VDDC_6 VDDC_7 VDDC_8 VDDC_9 VDDC_10 VDDC_11 VDDC_12 VDDC_13 VDDC_14 VDDC_15 VDDC_16 VDDC_17 VDDC_18 VDDC_19 VDDC_20 VDDC_21 VDDC_22 VDDC_23 VGA_PCIE_VDDR12_2 C217 C213 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP 0R0603-PAD VDDR3_1 VDDR3_2 VDDR3_3 VDDR3_4 VDDR3_5 VDDR3_6 VDDR3_7 VDDR3_8 AL31 AM31 AM30 AL32 AL30 AM28 AL29 AM29 AM27 SCD1U10V2KX-4GP R536 C138 AB9 AB10 AA9 AC19 AD18 AC20 AD19 AD20 P O W E R PCIE_VDDR_12_1 PCIE_VDDR_12_2 PCIE_VDDR_12_3 PCIE_VDDR_12_4 PCIE_VDDR_12_5 PCIE_VDDR_12_6 PCIE_VDDR_12_7 PCIE_VDDR_12_8 PCIE_VDDR_12_9 C216 1D2V_S0 FOR M26X PCIE_VDDR12 CONNECT TO +1.8V FOR M52P,M54P,M56P CONNECT TO +1.2V SCD1U10V2KX-4GPSCD1U10V2KX-4GP C139 TC19 ST100U6D3VDM-5 C218 R153 0R0805-PAD C156 SCD1U10V2KX-4GPSCD1U10V2KX-4GP C141 SC1U6D3V2KX-GP SC1U6D3V2KX-GP C252 VGA_PCIE_VDDR12_1 SCD1U10V2KX-4GPSCD1U10V2KX-4GP VGA_VDDR3 C215 C246 N29 N28 N27 N26 N25 SCD1U10V2KX-4GPSCD1U10V2KX-4GP K23 C199 C658 PCIE_VDDR_12_10 PCIE_VDDR_12_11 PCIE_VDDR_12_12 PCIE_VDDR_12_13 PCIE_VDDR_12_14 SCD1U10V2KX-4GP VSS_159 C214 C196 C194 PCIE_PVDD_12_1 PCIE_PVDD_12_2 PCIE_PVDD_12_3 PCIE_PVDD_12_4 SCD1U10V2KX-4GP CORE GND C250 C180 C209 C224 V23 N23 P23 U23 I/0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 C211 C203 Memory I/O A B1 H1 L1 P1 U1 Y1 AD7 AE8 AL1 A2 AM2 AD10 E8 H5 K10 M8 T10 E12 AC9 AF14 AD8 C5 F10 J3 L6 M6 P6 AA4 AG11 V3 AG16 R3 C6 C9 F6 H7 J6 C253 VDDR1_1 VDDR1_2 VDDR1_3 VDDR1_4 VDDR1_5 VDDR1_6 VDDR1_7 VDDR1_8 VDDR1_9 VDDR1_10 VDDR1_11 VDDR1_12 VDDR1_13 VDDR1_14 VDDR1_15 VDDR1_16 VDDR1_17 VDDR1_18 VDDR1_20 VDDR1_21 VDDR1_22 VDDR1_23 VDDR1_24 VDDR1_25 VDDR1_26 VDDR1_27 VDDR1_28 VDDR1_29 VDDR1_30 VDDR1_31 VDDR1_32 VDDR1_33 VDDR1_34 VDDR1_35 VDDR1_36 VDDR1_37 VDDR1_38 VDDR1_39 VDDR1_40 VDDR1_41 VDDR1_42 VDDR1_43 VDDR1_45 VDDR1_46 Memory I/O Clock B PCIE_PVSS VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSS_98 VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112 VSS_113 VSS_114 VSS_115 VSS_116 VSS_117 VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125 VSS_126 VSS_127 VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135 VSS_136 VSS_137 VSS_138 VSS_139 VSS_140 VSS_141 VSS_142 VSS_143 VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156 VSS_157 VSS_158 SCD1U10V2KX-4GP W23 PCI-Express GND C PCIE_VSS_1 PCIE_VSS_2 PCIE_VSS_3 PCIE_VSS_4 PCIE_VSS_5 PCIE_VSS_6 PCIE_VSS_7 PCIE_VSS_8 PCIE_VSS_9 PCIE_VSS_10 PCIE_VSS_11 PCIE_VSS_12 PCIE_VSS_13 PCIE_VSS_14 PCIE_VSS_15 PCIE_VSS_16 PCIE_VSS_17 PCIE_VSS_18 PCIE_VSS_19 PCIE_VSS_20 PCIE_VSS_21 PCIE_VSS_22 PCIE_VSS_23 PCIE_VSS_24 PCIE_VSS_25 PCIE_VSS_26 PCIE_VSS_27 PCIE_VSS_28 PCIE_VSS_29 PCIE_VSS_30 PCIE_VSS_31 PCIE_VSS_32 PCIE_VSS_33 PCIE_VSS_34 PCIE_VSS_35 PCIE_VSS_36 PCIE_VSS_37 PCIE_VSS_38 PCIE_VSS_39 PCIE_VSS_40 PCIE_VSS_41 PCIE_VSS_42 PCIE_VSS_43 PCIE_VSS_44 PCIE_VSS_45 PCIE_VSS_46 PCIE_VSS_47 PCIE_VSS_48 PCIE_VSS_49 PCIE_VSS_50 PCIE_VSS_51 PCIE_VSS_52 PCIE_VSS_53 PCIE_VSS_54 PCIE_VSS_55 PCIE_VSS_56 PCIE_VSS_57 PCIE_VSS_58 PCIE_VSS_59 PCIE_VSS_60 PCIE_VSS_61 PCIE_VSS_62 PCIE_VSS_63 PCIE_VSS_64 PCIE_VSS_65 PCIE_VSS_66 PCIE_VSS_67 PCIE_VSS_68 PCIE_VSS_69 PCIE_VSS_70 PCIE_VSS_71 PCIE_VSS_72 PCIE_VSS_73 PCIE_VSS_74 PCIE_VSS_75 PCIE_VSS_76 PCIE_VSS_77 PCIE_VSS_78 PCIE_VSS_79 PCIE_VSS_80 PCIE_VSS_81 PCIE_VSS_82 AD16 AA6 P7 P5 M3 M9 L7 M7 AD17 AH11 A8 U7 C10 E9 F3 J9 N7 N3 Y5 AM13 AC10 Y6 U6 E5 AL13 A11 U8 U9 U10 R6 AD6 V6 AD14 AD13 D11 J12 K12 A13 F13 E13 F15 K16 J21 H16 T15 V17 C15 C4 U14 P15 A16 E16 G13 G16 P17 R16 R14 W16 C18 F16 W18 U18 AE16 AE17 A19 H32 F19 G19 N8 Y7 T19 V19 G21 C21 F21 AE14 AK16 U5 F22 F18 K30 C24 F24 M24 A25 D30 E25 G25 G20 G22 F27 E28 H21 C27 E32 H28 J30 K17 K27 M32 A22 C20 E19 H20 J24 M28 J28 J16 F30 L29 A31 B32 E30 AE15 AG23 AD9 AF16 AH10 AJ10 AD15 AH16 C1 J1 M1 R1 V1 AA1 A3 P9 J10 N9 P10 A9 Y10 P8 R9 Y9 J11 A21 M10 N10 Y8 J18 J19 K21 A12 H13 A15 J20 J13 K11 K19 A18 L23 K20 K24 L24 H19 A24 K13 J32 A30 C32 F32 L32 SCD1U10V2KX-4GP D AH27 AC23 AL27 R23 P25 R25 T26 U26 W26 Y26 AB26 AC26 AD25 AE26 AF26 AD26 AG25 AH26 AC28 Y28 U28 P28 AH29 AF28 V29 AC29 W27 AB27 V26 AJ26 AJ32 AK29 P26 P29 R29 T29 U29 W29 Y29 AA29 AB29 AD29 AE29 AF29 AG29 AJ29 AK26 AK30 AG26 N30 R31 AF30 AC30 V31 P30 AA31 U30 AD31 AK32 AJ28 Y30 AJ30 AK31 AA23 AG31 N24 AB23 P24 R24 T24 U24 V24 W24 Y24 AC24 AH24 V25 AA25 R26 AA26 T27 AE27 VGA_PCIE_PVDD12 PART OF -1 Modify LVDS PLL, I/O 1D8V_S0 Part of U70E U70F Document Number Rev AG1 -1 Sheet Tuesday, January 10, 2006 48 of 53 Ideal Power Up Sequence Real Power Up Sequence D D VBBN VBBN VBBP VBBP VDDC VDDC MVDDC PCIE_VDDR_12 MVDDC PCIE_VDDR_12 1mS PCIE_PVDD_12 C PCIE_PVDD_12 VDD25 VDD25 VDDR1 VDDR1 1/16W, 25V 0603 => 1/16W, 75V 0805 => 1/10W, 100V Size 2=>0402, 3=>0603, 5=>0805, 6=>1206, 0=>1210 10KR3 10K Ohm If no letter, it means J: 5% 1/16W, 75V 0603 33D3R5 33.3 Ohm If no letter, it means J: 5% 1/10W, 100V 0805 1KR3F 1K Ohm F: 1% 1/16W, 75V 0603 The naming rule is value + R + size + tolerance For the value, it can be read by the number before R (R means resistor) For the tolerance, it can be read from the last letter For the rating, we don't show on the symbol name For the size, R2=>0402, R3=>0603, R5=>0805, C VDDR3 General Guidelines: • BBN and BBP must ramp up before or at the same time as VDDC but not after • VDDC and MVDDC must be ramped up first, followed by PCIE_VDDR_12, PCIE_PVDD12, VDD25, VDDR1 and VDDR3 (and other I/O powers) • All powers must be ramped up within 5ms of each other (from the ramp of VDDC to 90% of VDDR3) • VDD25 can be ramped with VDDC or VDDR1 but it cannot be ramped later than VDDR1 • The power down is the opposite of the power on sequence: VDDR3/VDDR1 -> VDD25 ->VDDC/MVDDC/BBN/BBP Due to the level shifter design in the memory I/Os, in order to avoid over-stressing the thin oxide transistors when VDDR1 is powered on but VDDC is not, VDDC must ramp up before VDDR1 Similarly, VDDC must ramp up before VDDR3 The level shifter design is a function of the transistor types used in 90nm technology and of the voltage level support The drawback of ramping up VDDC before the I/O voltages (such as VDDR1 and VDDR3) is that parasitic P/N junctions are forward biased, thus creating a conduction path These conduction paths will pump up VDDR1 (from the memory IOs) and VDDR3 (from the GPIOs) The real power up sequence will appear as follows: Figure 2-2 Real Power Up Sequence As long as MVDDC ramps up with VDDC, the pump voltage on VDDR1 should be all right since the DRAM spec will not be violated B CAPACITOR Symbol name Value A Tolerance (J: +/-5, K: +/-10, M: +/-20, Z: +80/-20) Rating ( X5R / X7R < 80%, Y5V/Y5U/Z5U < 1/3 ) Size 2=>0402, 3=>0603, 5=>0805, 6=>1206, 0=>1210 SCD1U10V2MX-1 0.1uF M/X5R 10V 0402 SC10U6D3V5MX 10uF M/X5R 6.3V 0805 SC2D2U16V5ZY 2.2uF Z/Y5V 16V 0805 The naming rule is Capacitor type + value + rating + size + tolerance + material SCD1U10V2MX-1 SC=> SMT Ceremic, TC=> POS cap or SP cap D1U => 0.1uF 10V => the voltage rating is 10V 2=> 0402, 3=>0603, 5=>0805 M=>tolerance J, K, M, Z X=> X7R/X5R, Y=> Y5V -1 => symbol version, nonsense to EE characteristic A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 ATI M5X-P POWER SEQUENCE Document Number Rev AG1 Date: Tuesday, January 10, 2006 SA Sheet 49 of 53 CHAN B DDR2 84BGA 32MX16 MEMORY D D C192 SC1U6D3V2KX-GP C182 SCD1U10V2KX-4GP SCD1U10V2KX-4GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SCD1U10V2KX-4GP SC1U6D3V2KX-GP SCD1U10V2KX-4GP C188 C190 1 C185 C186 C664 C189 1D8V_S0 DDR_VREF_S0 M56P RN22 SRN56J-2-GP RN93 MAB10 MAB9 MAB5 MAB0 SRN56J-2-GP RN92 MAB4 MAB6 MAB8 MAB11 SRN56J-2-GP B_BA0 R552 B_BA1 R551 MAB12_14 R550 K3 WE RASB0# K7 RAS CASB0# L7 CAS DQMB#2 DQMB#0 F3 B3 LDM UDM ODTB0 ODT RDQSB2 WDQSB2 F7 E8 LDQS LDQS RDQSB0 WDQSB0 B7 A8 UDQS UDQS VRAM_VREF1 J2 VREF A2 E2 L1 R3 R7 R8 NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 1D8V_S0 K9 1 R143 1KR2F-3-GP (SSTL-1.8) VREF = 5*VDDQ 2 R144 1KR2F-3-GP C181 SCD1U10V2KX-4GP A VDD1 VDD2 VDD3 VDD4 VDD5 A1 E1 J9 M9 R1 VDDL VSSDL J1 J7 1D8V_S0 R573 56R2J-4-GP R575 56R2J-4-GP C650 C183 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 VSS1 VSS2 VSS3 VSS4 VSS5 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 K8 J8 CK CK CKEB0 K2 CKE CSB0_0# L8 CS WEB0# K3 WE RASB0# K7 RAS CASB0# L7 CAS DQMB#1 DQMB#3 F3 B3 LDM UDM ODTB0 K9 ODT SCD1U10V2KX-4GP 1D8V_S0 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 R579 1KR2F-3-GP RDQSB1 WDQSB1 F7 E8 LDQS LDQS RDQSB3 WDQSB3 B7 A8 UDQS UDQS VRAM_VREF2 J2 VREF A2 E2 L1 R3 R7 R8 NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 (SSTL-1.8) VREF = 5*VDDQ R578 1KR2F-3-GP C653 A3 E3 J3 N1 P9 HY5PS561621A-25GP 72.55616.C0U SCD1U10V2KX-4GP B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 VDD1 VDD2 VDD3 VDD4 VDD5 A1 E1 J9 M9 R1 VDDL VSSDL J1 J7 MDB27 MDB28 MDB24 MDB31 MDB30 MDB25 MDB29 MDB26 MDB15 MDB9 MDB12 MDB8 MDB11 MDB13 MDB10 MDB14 47 47,51 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSS1 VSS2 VSS3 VSS4 VSS5 A3 E3 J3 N1 P9 47 47,51 RASB0# RASB1# 47 47,51 CASB0# CASB1# 47 47,51 WEB0# WEB1# 47 47,51 CSB0_0# CSB1_0# 47 47,51 CKEB0 CKEB1 47 47 CLKB0 CLKB0# SCD1U10V2KX-4GP 47,51 RDQSB[7 0] 47,51 DQMB#[7 0] 256R2J-4-GP 256R2J-4-GP 256R2J-4-GP ODTB0 ODTB1 R572 R82 256R2J-4-GP 256R2J-4-GP RASB0# RASB1# R574 R83 256R2J-4-GP 256R2J-4-GP CASB0# CASB1# R571 R81 256R2J-4-GP 256R2J-4-GP WEB0# WEB1# R577 R555 256R2J-4-GP 256R2J-4-GP CSB0_0# CSB1_0# R570 R84 256R2J-4-GP 256R2J-4-GP CKEB0 CKEB1 R576 R86 256R2J-4-GP 256R2J-4-GP C B CLKB0 CLKB0# RDQSB[7 0] DQMB#[7 0] MDB[63 0] 47,51 MDB[63 0] MAB[11 0] 47,51 MAB[11 0] 47,51 WDQSB[7 0] WDQSB[7 0] A HY5PS561621A-25GP 72.55616.C0U Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title VRAM 1/2 Size A3 Document Number Rev AG1 Date: Tuesday, January 10, 2006 FOR M56P AT DDR2 MEMORY SPEEDS ABOVE 350MHZ MEMORY CONTROL SIGNALS WE,CAS,RAS,CS,CKE,ODT AND MEMORY ADDRESS SIGNALS REQUIRE 55 OHM PULLUP TO A VTT RAIL (50% OF VDDQ) 72.55616.C0U IC VRAM HY5PS561621AFP-25 FBGA(16M*16, 350Mhz) Hynix-128M 72.18256.B0U IC VRAM HYB18T256161AFL25 BGA (16M*16, 350Mhz) Infineon-128M 72.18512.A0U IC VRAM HYB18T512161BF-25 BGA (32M*16, 400Mhz) Infineon-256M 1D8V_S0 C184 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 ODTB0 ODTB1 WEB0# MAB12_14 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 CS BA0 BA1 1 L8 2 CSB0_0# L2 L3 CLKB0# CLKB0 CLKB0# CLKB0 CKE 47 47 K2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 CLOSE TO MEM !! CKEB0 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 B_BA0 B_BA1 CK CK K8 J8 CLKB0# CLKB0 SC470P50V2KX-3GP A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MDB7 MDB0 MDB5 MDB2 MDB3 MDB4 MDB1 MDB6 MDB23 MDB18 MDB20 MDB16 MDB17 MDB21 MDB19 MDB22 BC857_1 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 B MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0 U69 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 MAB12_14 BA0 BA1 47,51 L2 L3 B_BA0 B_BA1 47,51 47,51 MAB2 MAB7 MAB3 MAB1 C655 SC1U6D3V2KX-GP U23 C C578 SCD1U10V2KX-4GP SC1U6D3V2KX-GP SC1U6D3V2KX-GP SCD1U10V2KX-4GP SCD1U10V2KX-4GP SC1U6D3V2KX-GP SCD1U10V2KX-4GP C652 1 C662 C191 C663 C654 C577 1D8V_S0 SC Sheet 50 of 53 D D SC10U6D3V5MX-3GP SC10U6D3V5MX-3GP C651 2 C84 2 1 2 1 2 C90 SCD1U10V2KX-4GP 2 C85 SCD1U10V2KX-4GP SC1U6D3V2KX-GP SCD1U10V2KX-4GP SC1U6D3V2KX-GP C633 C86 SCD1U10V2KX-4GP C632 C89 SCD1U10V2KX-4GP C634 C187 SC1U6D3V2KX-GP C88 SCD1U10V2KX-4GP C630 SC1U6D3V2KX-GP SC1KP16V2KX-GP C193 SC1U6D3V2KX-GP C635 C661 SC1U6D3V2KX-GP 1D8V_S0 C92 SC1KP16V2KX-GP 1D8V_S0 -1 Modify C C U21 L8 CS WEB1# K3 WE K7 RAS CASB1# L7 CAS F3 B3 LDM UDM LDQS LDQS F7 E8 ODT 1 R90 1KR2F-3-GP RDQSB4 WDQSB4 VRAM_VREF3 (SSTL-1.8) VREF = 5*VDDQ A 2 R89 1KR2F-3-GP C87 SCD1U10V2KX-4GP J1 J7 C83 B7 A8 UDQS UDQS J2 VREF A2 E2 L1 R3 R7 R8 NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSS1 VSS2 VSS3 VSS4 VSS5 A3 E3 J3 N1 P9 CK CK CKEB1 K2 CKE R556 56R2J-4-GP CSB1_0# L8 CS WEB1# K3 WE RASB1# K7 RAS CASB1# L7 CAS F3 B3 LDM UDM K9 ODT SCD1U10V2KX-4GP 1D8V_S0 RDQSB6 WDQSB6 F7 E8 LDQS LDQS RDQSB7 WDQSB7 B7 A8 UDQS UDQS J2 VREF A2 E2 L1 R3 R7 R8 NC#A2 NC#E2 NC#L1 NC#R3 NC#R7 NC#R8 C631 DQMB#6 DQMB#7 ODTB1 RDQSB5 WDQSB5 1D8V_S0 K9 K8 J8 SC470P50V2KX-3GP ODTB1 VDDL VSSDL A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CLKB1# CLKB1 R87 1KR2F-3-GP DQMB#5 DQMB#4 VDD1 VDD2 VDD3 VDD4 VDD5 A1 E1 J9 M9 R1 R554 56R2J-4-GP BC856_1 RASB1# 1D8V_S0 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 VRAM_VREF4 (SSTL-1.8) VREF = 5*VDDQ R85 1KR2F-3-GP C82 SCD1U10V2KX-4GP HY5PS561621A-25GP 72.55616.C0U MDB59 MDB60 MDB58 MDB62 MDB63 MDB56 MDB61 MDB57 MDB51 MDB53 MDB48 MDB55 MDB52 MDB49 MDB54 MDB50 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 47,50 RASB1# 47,50 CASB1# 47,50 WEB1# 47,50 CSB1_0# 47,50 CKEB1 47,50 ODTB1 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 VDD1 VDD2 VDD3 VDD4 VDD5 A1 E1 J9 M9 R1 47,50 DQMB#[7 0] J1 J7 47,50 WDQSB[7 0] VDDL VSSDL 47 47 1D8V_S0 A7 B2 B8 D2 D8 E7 F2 F8 H2 H8 VSS1 VSS2 VSS3 VSS4 VSS5 A3 E3 J3 N1 P9 CASB1# WEB1# CSB1_0# CKEB1 ODTB1 CLKB1 CLKB1# CLKB1 CLKB1# B 47,50 RDQSB[7 0] 47,50 MDB[63 0] 47,50 MAB[11 0] C629 VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VSSQ6 VSSQ7 VSSQ8 VSSQ9 VSSQ10 RASB1# RDQSB[7 0] DQMB#[7 0] MDB[63 0] MAB[11 0] WDQSB[7 0] CSB1_0# CLKB1# CLKB1 MAB12_14 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 SCD1U10V2KX-4GP CKE 47 47 B K2 A9 C1 C3 C7 C9 E9 G1 G3 G7 G9 CKEB1 VDDQ1 VDDQ2 VDDQ3 VDDQ4 VDDQ5 VDDQ6 VDDQ7 VDDQ8 VDDQ9 VDDQ10 BA0 BA1 CK CK L2 L3 K8 J8 B_BA0 B_BA1 1 CLKB1# CLKB1 U68 2 A12 A11 A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 MDB39 MDB32 MDB38 MDB34 MDB33 MDB37 MDB35 MDB36 MDB44 MDB43 MDB47 MDB40 MDB41 MDB46 MDB42 MDB45 R2 P7 M2 P3 P8 P2 N7 N3 N8 N2 M7 M3 M8 B9 B1 D9 D1 D3 D7 C2 C8 F9 F1 H9 H1 H3 H7 G2 G8 MAB12_14 MAB11 MAB10 MAB9 MAB8 MAB7 MAB6 MAB5 MAB4 MAB3 MAB2 MAB1 MAB0 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 CLOSE TO MEM !! BA0 BA1 MAB12_14 L2 L3 47,50 B_BA0 B_BA1 B_BA0 B_BA1 47,50 47,50 C628 SC1U10V3KX-3GP A Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C HY5PS561621A-25GP 72.55616.C0U Title VRAM 2/2 Size A3 Document Number Rev AG1 Date: Tuesday, January 10, 2006 -1 Sheet 51 of 53 VGA_CORE_S0 G2 DCBATOUT DCBATOUT_5234 G11 L1 SC10U35V0ZY-1GP SCD1U25V3ZY-1GP G7 GAP-CLOSE-PWR G8 GAP-CLOSE-PWR AO4430-1-GP C21 SCD1U25V3KX-GP SC Id=18A Qg=48nC Rdson=6.2~7.5mohm 442R2F-GP 1 R33 655R3F-GP C555 SCD1U25V3ZY-1GP TC18 SE330U2VDM-L2GP TC17 SE330U2VDM-L2GP Non-M52 M52P DY SC Panasonic V Size 330uF 2V ESR=9mohm, Iripple=3.0A USD:0.250 (Q3/05) R14 DUMMY-R3 PWM Mode: FPWM (High)=>Fixed PWM Mode FPWM (Low)=>Hysteretic Mode SC R11 C42 R13 10KR2J-3-GP 300KHz U64 TP67 TPAD30 C VGA_CORE_PWR Vosetting=1.0809V TAI-TECH M52:1.0V M54:1.1V M56: 1.1V Iomax=17A OCP>28A 5V_S0 74.05234.A7G L2 FAN5234MTCX-1GP DY 1 2 B R35 2KR2F-3-GP 5234_VSEN SC2200P50V2KX-2GP C44 R34 C41 SCD22U16V3ZY-GP PGOOD GAP-CLOSE-PWR Vout Setting: 0.9V/Rlow=(Vout-0.9V)/Rhigh 5234_HDRV 5234_LDRV L-D56UH-U 14 10 G6 1 HDRV LDRV GAP-CLOSE-PWR 2 VSEN VOUT VIN VCC GAP-CLOSE-PWR G5 G65 GAP-CLOSE-PWR 11 D G66 GAP-CLOSE-PWR Panasonic IND-1UH-48-GP S S S G 97K6R3F-GP 5234_VIN R36 1K2R3F-GP D D D D R12 0R0603-PAD C23 5234_ISEN 5234_SW G4 GAP-CLOSE-PWR 12 13 C556 SCD01U16V2KX-3GP ISNS SW GAP-CLOSE-PWRG60 GAP-CLOSE-PWR 2 SC 5234_SS 5234_ILIM 5234_EN Id=11A Qg=9.8nC Rdson=19.6~24mohm PGND AGND C22 U63 AO4422-1-GP SCD1U25V3KX-GP FPWM BOOT SS ILIM EN G3 G64 GAP-CLOSE-PWR 2 GAP-CLOSE-PWR 16 15 GAP-CLOSE-PWRG62 GAP-CLOSE-PWR 2 DCBATOUT_5234 U8 2 SSM5818SLPT-GP 10KR2J-3-GP DCBATOUT_5234 B GAP-CLOSE-PWR G13 C47 SCD1U16V2ZY-2GP 5234_BOOT R499 DUMMY-R2 R498 GAP-CLOSE-PWR G14 2 1 PM_SLP_S3# G1 S S S G 16,18,30,31,36,41,43 GAP-CLOSE-PWR G12 C46 D5 5V_S0 C GAP-CLOSE-PWR G9 VGA_CORE_S0 G61 GAP-CLOSE-PWRG63 GAP-CLOSE-PWR D D D D C45 SC10U10V5ZY-1GP 5V_S5 GAP-CLOSE-PWR G10 FAN5234 FOR VGA_Core SC10U35V0ZY-1GP D VGA_CORE_PWR 3D3V_S0 POWERPLAY: : 1.0V high (3.3V) = set lower core voltage (e.g VDDC = 1.0V) low (0V) = set higher core voltage (e.g VDDC = 1.2V) High :R35 + R31 set Vout to 0.9994V R32 5K9R2F-GP Low : R35 set Vout to 1.19925V Non-M52 2 Non-M52 Q35 B CHT2222APT-GPNon-M52 Non-M52 R485 1KR2J-1-GP M52 : 0.95V, but don't card it.(1.0V) don't mount Q9 R35 + R31 set Vout to 0.9994V 2 ATI M5x VGA Core A VGA Ver Normal PowerPlay M52 A12 1.0 0.95/1.0 M54 A12 1.1 0.95/0.95 1.2 0.95 1.1 0.95/0.95 M56 B24 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 VGA CORE 1D1V Document Number Rev AG1 Date: Tuesday, January 10, 2006 R483 100KR2J-1-GP Non-M52 A GPIO_PWRCNTL 46 C566 SC4D7U10V5ZY-3GP R497 20KR2J-L2-GP C G S Non-M52 1 E D 4K02R2F-GP R31 Non-M52 M54/M56 : 0.95V High :R35 + R31 set Vout to 1.0989V Low : R35 set Vout to 0.9503V R481 10KR2J-3-GP Q9 2N7002-8-GP M52P Rilim=(11.2/Iilim)*((100+Rsense)/Rdson) -1 Sheet 52 of 53 A B C D E EMI CAP 5V_S0 BT+ DCBATOUT SCD1U25V3ZY-1GP SCD1U25V3ZY-1GP EC48 EC45 EC46 EC43 EC44 SCD1U25V3ZY-1GP SCD1U25V3ZY-1GP SCD1U25V3ZY-1GP 1 EC47 EC40 SCD1U25V3ZY-1GP SCD1U25V3ZY-1GP EC39 SCD1U25V3ZY-1GP EC38 SCD1U25V3ZY-1GP SCD1U25V3ZY-1GP EC37 EC22 11 TSAHCT125PW-GP SCD1U25V3ZY-1GP 13 12 TSAHCT125PW-GP U59D 14 U59C 10 14 5V_S0 H7 H12 K1 K3 1 1 1 SCD1U16V2ZY-2GP EC64 SCD1U16V2ZY-2GP EC65 SCD1U16V2ZY-2GP EC57 EC59 2 EC60 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP EC62 SCD1U16V2ZY-2GP EC63 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP 2 EC58 FOR MDC 34.40U07.001 IO Bracket H26 SPRING-9-GP DY 34.49U23.001 IO Bracket H31 SPRING-9-GP DY 34.4A908.001 H24 EC41 K4 SPRING-U3 BOTTOM SIDE: EC66 H13 34.4A901.001 EC61 SCD1U16V2ZY-2GP CPU Thermal Module H17 EC42 SCD1U16V2ZY-2GP New Card TOP SIDE: SCD1U16V2ZY-2GP EC67 SCD1U16V2ZY-2GP 3D3V_S0 VGA H34 UMA H27 H32 FOR MINIC MINIC MINIC H30 H28 H29 K2 34.4A902.001 34.4A903.001 34.4A904.001 34.4A905.001 34.4A906.001 1 1 1 1 SPRING-23-GP 34.4A907.001 34.39S07.001 H11 HOLE H14 HOLE H8 HOLE H5 HOLE H18 HOLE H15 HOLE 1 1 1 1 H3 HOLE H19 HOLE H36 HOLE H22 HOLE H21 HOLE H9 HOLE H6 HOLE H1 HOLE H2 HOLE H4 HOLE 1 H33 HOLE H20 HOLE 1 H35 HOLE H16 HOLE 1 H10 HOLE 2 AUD_AGND 1 Wistron Corporation 21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C Title Size A3 SPRING & BOSS Document Number A B C D Rev AG1 Date: Tuesday, January 10, 2006 -1 Sheet E 53 of 53 ... IDE_PDD12 IDE_PDD11 IDE_PDD10 IDE_PDD9 IDE_PDD8 IDE_PDD7 IDE_PDD6 IDE_PDD5 IDE_PDD4 IDE_PDD3 IDE_PDD2 IDE_PDD1 IDE_PDD0 18 16 14 12 10 11 13 15 17 DD15 DD14 DD13 DD12 DD11 DD10 DD9 DD8 DD7 DD6... AF26 DD0 DD1 DD2 DD3 DD4 DD5 DD6 DD7 DD8 DD9 DD10 DD11 DD12 DD13 DD14 DD15 AB15 AE14 AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12 AB13 AC14 AF14 AH13 AH14 AC15 IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4... IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 DA0 DA1 DA2 AH17 AE17 AF17 IDE_PDA0 20 IDE_PDA1 20 IDE_PDA2 20 DCS1# DCS3# AE16 AD16