A B C D E 1 Compal Confidential 2 JE50/HM50/SJV50_BZ P5WE6/P5WH6/P5WS6 Schematics Document AMD Brazos Brazos with Zacate / Hudson M1 / Seymour XT DIS only / UMA only / PX Muxless / PX Muxless with BACO 2010-11-16 LA-7092P REV: 1.0 ZZZ PCB Part Number = DAZ0IC00100 4 2010/08/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/08/20 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Cover Page Document Number Rev 1.0 LA-7092P P5WE6/H6/S6 Tuesday, November 16, 2010 Sheet E of 47 A B C D E Compal Confidential Model Name : P5WE6/P5WH6/P5WS6 JE50/HM50/SJV50_BZ PCB PN : DAZ0IC00100 VRAM 512M/1G 64M16/128M16 x Brazos page 23 DDR3 Memory BUS(DDR3) ATI Vancuver Seymour uFCBGA-962 Thermal Sensor Page 18,19,20,21,22 PCI-Express x Gen2 ADM1032 page 19 DP0 LVDS 204pin DDRIII-SO-DIMM X2 Single Channel AMD Brazos APU BANK 0, 1, 2, page 8,9 1.5V DDRIII 800~1066MHz FT1 BGA 413-Ball 19mm x 19mm page 10 DP1 page 5,6,7 CRT page 12 HDMI Conn page UMI Gen.1 x4 PCI-Express 2.5GT/s per lane USB port 0,1,2 USB port USB Conn x CMOS Camera 11 page 33 USB port USB port6 Bluetooth Conn page 10 page 33 USB port Card Reader RT5137 Mini card (WL)X1 page 29 page 29 FCH 3.3V 48MHz Hudson-M1 BGA 605-Ball 23mm x 23mm S-ATA page 29 GPP3 HDA Codec CX20584 page 27 page 26 GPP2 RTC CKT LPC BUS RJ45 page 13 page 26 Power On/Off CKT Power sequence DC/DC DC/DC Interface CKT SATA ODD Sub/B page port port MIC Jack x HP Jack x Int MIC x Int SPK x page 32 page 32 EC I/O Buffer page 34 page 28 Int.KBD Touch Pad Fan Control 30 page 31 page 24,25 SATA HDD Conn page 30 ENE KB930 page 34 VGA Gen2 Atheros AR8151 WLAN page 32 HD Audio page 13,14,15,16,17 LAN(GbE) MINI Card LED USB 3.3V 24.576MHz/48Mhz BIOS page 32 page 32 page 35 Power Circuit page 36,37,38,39,40,41 42,43,44,45 Extend Card/B USB X2 ODD X1 2010/08/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/08/20 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Block Diagrams Document Number Rev 1.0 LA-7092P P5WE6/H6/S6 Monday, November 15, 2010 Sheet E of 47 A B C D E Voltage Rails Power Plane Description S1 S3 S5 VIN Adapter power supply (19V) N/A N/A N/A B+ AC or battery power rail for power circuit N/A N/A N/A +VSB VSB always on power rail ON ON ON* +3VALW 3.3V always on power rail ON ON ON* +5VALW 5V always on power rail ON ON ON* +1.1VALW 1.1V always on power rail ON ON ON* +APU_CORE Core voltage for CPU (0.7-1.2V) ON OFF OFF +APU_CORE_NB 1.0V switched power rail ON OFF OFF ON ON ON ON S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF Board ID / SKU ID Table for AD channel ON ON OFF OFF OFF +1.05VS 1.05V switched power rail for APU VDD10 ON OFF OFF Vcc Ra/Rc/Re +1.1VS 1.1VS switched power rail ON OFF OFF Board ID +1.8VS 1.8V switched power rail ON OFF OFF +3VS 3.3V switched power rail ON OFF OFF ON OFF OFF OFF OFF +3VSG 3.3V switched power rail for GPU ON OFF OFF +1.8VSG 1.8V switched power rail for GPU ON OFF OFF +1.5VSG 1.5V switched power rail for GPU ON OFF OFF +1.0VSG 1.0V switched power rail for GPU ON OFF OFF +3V_LAN 3.3V power rail for LAN ON ON ON +RTCVCC RTC power ON ON ON Clock HIGH ON ON +VS HIGH 1.5V power rail for CPU VDDIO and DDRIII 5V switched power rail +V HIGH 0.75VS switched power rail for DDR terminator Core voltage for GPU +VALW HIGH +0.75VS +5VS BOARD ID Table SLP_S1# SLP_S3# SLP_S4# SLP_S5# Full ON +1.5V +VGA_CORE SIGNAL STATE 3.3V +/- 5% 100K +/- 5% Rb / Rd / Rf 8.2K +/- 5% 18K +/- 5% 33K +/- 5% 56K +/- 5% 100K +/- 5% 200K +/- 5% NC Board ID PCB Revision Project ID Table V AD_BID V 0.216 V 0.436 V 0.712 V 1.036 V 1.453 V 1.935 V 2.500 V V AD_BID typ V 0.250 V 0.503 V 0.819 V 1.185 V 1.650 V 2.200 V 3.300 V V AD_BID max V 0.289 V 0.538 V 0.875 V 1.264 V 1.759 V 2.341 V 3.300 V Board ID PCB Revision Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF BOARD ID Table EC SM Bus1 address Device Address EC SM Bus2 address HEX Device ADM1032 (GPU) SM Bus Controller Device Address HEX 1001-101xb 9AH (FCH_SMB1 ~ FCH_SMB4, SMB_ALERT#) Address BTO Option Table PCB Revision BTO Item BOM Structure Display from APU UMA@ Display from VGA DISO@ Use VGA VGA@ Muxless w/BACO BACO@ Muxless wo/BACO WOBACO@ Muxless PX@ w/Vancouver Serise VAN@ w/Manhttan Serise MAN@ Bluetooth BT@ AR8151 8151@ Seymour Seymour@ wo/Muxless WOPX@ wo/VGA WOVGA@ APU 1.5G 15G@ APU 1.6G 16G@ w/ X'tal X1 wo/ X'tal X1 HEX APU SIC/SID (FCH_SMB3) Project ID Table H_THERMTRIP# (FCH_ALERT#) SM Bus Controller Device Board ID Board ID (FCH_SMB0) Address HEX DDR DIMM1 (FCH_SMB0) 1001-000xb 90 DDR DIMM2 (FCH_SMB0) 1001-001xb 92 WLAN (FCH_SMB0) PCB Revision *UMA only : UMA@ BT@ 8151@ WOVGA@ WOPX@ VGA Chip SEL: Seymour@ + Van@ Robson@ + Man@ APU Chip SEL: 16G@ 15G@ *DIS only : VGA@ DISO@ WOBACO@ BT@ 8151@ WOPX@ *Muxless w/BACO : UMA@ VGA@ PX@ BACO@ BT@ 8151@ Muxless wo/BACO : UMA@ VGA@ PX@ WOBACO@ BT@ 8151@ 2010/08/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/08/20 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C D Notes List Document Number Rev 1.0 LA-7092P P5WE6/H6/S6 Tuesday, November 16, 2010 Sheet E of 47 Power-Up/Down Sequence BACO option : VDDR3 should ramp-up before or simultaneously with VDDC PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode) PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High) For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before DPx_VDD18 For power-down, DPx_VDD18 should ramp-down before DPx_VDD10 The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up 5.VDDC and VDD_CT should not ramp-up simultaneously (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).) VDDR3(3.3VSG) Note: Do not drive any IOs before VDDR3 is ramped up PCIE_VDDC(1.0V) C PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred D Without BACO option : VDDR1(1.5VSG) dGPU Power Pins Voltage PX 3.0 BACO Mode Max current PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT, DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD, DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI, DPLL_PVDD, MPV18, and SPV18 1.8V OFF ON 1679mA DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and SPV10 1.0V OFF ON 575mA PCIE_VDDC 1.0V OFF ON 2A VDDR3 , and A2VDD 3.3V OFF ON 190mA BIF_VDDC (current consumption = 55mA@1.0V, in BACO mode) Same as VDDC OFF ON Same as PCIE_VDDC 70mA VDDR1 1.5V OFF OFF 2.8A VDDC/VDDCI 1.12V OFF OFF 12.9A D C VDDC/VDDCI(1.12V) VDD_CT(1.8V) iGPU PE_GPIO0 PE_EN dGPU PERSTb BACO Switch BIF_VDDC PE_GPIO1 REFCLK PX_mode +3.3VALW B Straps Reset +1.0V Straps Valid MOS Regulator +3.3VSG B +1.0VSG +1.5V +1.5VSG SI4800 Regulator Global ASIC Reset +1.8V T4+16clock SI4800 +B +1.8VSG +VGA_CORE PWRGOOD A A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/08/20 Deciphered Date 2011/08/20 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: dGPU Block Diagram Document Number Rev 1.0 LA-7092P P5WE6/H6/S6 Monday, November 15, 2010 Sheet of 47 +1.8VS D10 C10 TDP1_TXP2 TDP1_TXN2 APU_HDMI_CLKP APU_HDMI_CLKN A10 B10 TDP1_TXP3 TDP1_TXN3 APU_TXOUT2+ APU_TXOUT2- B5 A5 LTDP0_TXP0 LTDP0_TXN0 APU_TXOUT1+ APU_TXOUT1- D6 C6 LTDP0_TXP1 LTDP0_TXN1 APU_PROCHOT# 1K_0402_5% R109 UMA@ 4.7K_0402_5% APU_CRT_DDC_SCL R155 UMA@ 4.7K_0402_5% APU_CRT_DDC_SDA R411 1K_0402_5% APU_ALERT#_R R143 1K_0402_5% APU_SIC R414 1K_0402_5% APU_SID A6 B6 APU_TXCLK+ APU_TXCLK- D8 C8 V2 V1 APU_CLKP APU_CLKN For DVT 1011 APU_SVC APU_SVD J1 J2 SVC SVD P3 P4 SIC SID T3 T4 RESET_L PWROK APU_RST# APU_PWRGD R169 R168 APU_PROCHOT# U1 APU_THERMTRIP# U2 APU_ALERT#_R T2 0_0402_5% 0_0402_5% @ APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ# T93PAD T94PAD Close to APU APU_VDDNB_RUN_FB_H APU_VDD0_RUN_FB_H T77PAD F4 G1 F3 VDDCR_NB_SENSE VDDCR_CPU_SENSE VDDIO_MEM_S_SENSE A3 B3 LTDP0_HPD D3 DAC_RED DAC_REDB DAC_GREEN DAC_GREENB DAC_BLUE DAC_BLUEB DAC_HSYNC DAC_VSYNC C12 D13 A12 B12 A13 B13 F2 D4 DAC_ZVSS D12 TEST4 TEST5 TEST6 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 TEST25_H TEST25_L TEST28_H TEST28_L TEST31 TEST33_H TEST33_L TEST34_H TEST34_L TEST35 TEST36 TEST37 R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5 APU_HDMI_HPD APU_LCD_CLK APU_LCD_DATA R406 150_0402_1% R408 150_0402_1% R409 150_0402_1% APU_CRT_B APU_CRT_DDC_SCL APU_CRT_DDC_SDA R144 499_0402_1% PAD T66 PAD T67 PAD T68 TEST15 R415 TEST18 TEST19 TEST25_H TEST_25_L @ R416 R417 R418 1K_0402_5% C 1K_0402_5% 1K_0402_5% 510_0402_1% TEST31 PAD T73 TEST33_H C5161 R420 0.1U_0402_16V4Z TEST33_L C5171 R421 0.1U_0402_16V4Z Delete Test point for layout limitation 20100917 TEST35 R422 @ 1K_0402_5% TEST36 TEST37 R958 1K_0402_5% PAD T76 +1.8VS K3 T1 51_0402_1% 51_0402_1% ALLOW_STOP# R423 1K_0402_5% +1.8VS B Zacate FT1 B0 +1.8VS +1.8VS JHDT1 0_0402_5% R842 APU_TRST# FDV301N, the Vgs is: = 0.65V Typ = 0.85V Max = 1.5V BSH111, the Vgs is: = 0.4V Typ = 1.0V Max = 1.3V 1 2 APU_TCK R843 1K_0402_5% 3 4 APU_TMS R840 1K_0402_5% 5 6 APU_TDI R798 1K_0402_5% 8 APU_TDO 10 10 APU_PWRGD 11 12 12 APU_RST# 14 APU_DBRDY 16 APU_DBREQ# R178 300_0402_5% 18 J108_PLLTST0 R799 0_0402_5% TEST19 20 J108_PLLTST1 R863 0_0402_5% TEST18 0_0402_5% R846 APU_TRST#_R R847 10K_0402_5% 11 R176 10K_0402_5% 13 R177 10K_0402_5% 15 30K_0402_1% 17 G 1.607V for Gate EC_SMB_DA D S @ Q22 BSH111 1N_SOT23-3 G APU_CRT_G APU_CRT_HSYNC APU_CRT_VSYNC C H_THERMTRIP# R431 APU_CRT_R AMD Debug Q79 0.1U_0402_10V7K APU_SID 100K_0402_5% R407 APU : SA000046G80 (S IC ZACATE 2M161232B2240 1.6G BGA ) @ @ R160 APU_LCD_CLK APU_LCD_DATA U22 16G@ CPU TSI interface level shift C236 D APU_HDMI_CLK APU_HDMI_DATA E1 E2 DAC_SCL DAC_SDA TEST38 DMAACTIVE_L RSVD_1 RSVD_2 RSVD_3 If FCH internal pull-up disabled, level-shifter could be deleted Need BIOS to disable internal pull-up!! A LTDP0_AUXP LTDP0_AUXN APU_HDMI_CLK APU_HDMI_DATA APU : SA00004DO60 (S IC ZACATE 2M151132B1240 1.5G BGA) E R427 @ 31.6K_0402_1% C1 VSS_SENSE MMBT3904_NL_SOT23-3 TDP1_HPD 150_0402_1% APU_ENBKL APU_ENVDD APU_BLPWM B APU_THERMTRIP# @ R428 TDP1_AUXP TDP1_AUXN B2 C2 R398 ONTARIO-2M161000-1.6G_BGA413 15G@ R424 10K_0402_5% 1K_0402_5% PROCHOT_L THERMTRIP_L ALERT_L TDI TDO TCK TMS TRST_L DBRDY DBREQ_L B4 W11 V5 +3VS DISP_CLKIN_H DISP_CLKIN_L N2 N1 P1 P2 M4 M3 M1 F1 APU_VDD0_RUN_FB_L R425 CLKIN_H CLKIN_L D2 D1 C B LTDP0_TXP3 LTDP0_TXN3 APU_DISP_CLKP APU_DISP_CLKN APU_SIC APU_SID EC_THERM# FCH_PROCHOT# LTDP0_TXP2 LTDP0_TXN2 G2 H2 H1 SER R410 APU_TXOUT0+ APU_TXOUT0- H3 TEST +3VS CLK C237 0.01U_0402_25V7K APU_RST# @ C238 0.01U_0402_25V7K APU_PWRGD @ DP_ZVSS DP_BLON DP_DIGON DP_VARY_BL DP MISC APU_HDMI_TX0P APU_HDMI_TX0N VGA DAC TDP1_TXP1 TDP1_TXN1 DISPLAYPORT B9 A9 DISPLAYPORT APU_HDMI_TX1P APU_HDMI_TX1N CTRL 2 1 2 TDP1_TXP0 TDP1_TXN0 JTAG 1 2 1 APU_SVC APU_SVD APU_RST# APU_PWRGD TEST_25_L TEST36 1K_0402_5% 1K_0402_5% 300_0402_5% 300_0402_5% 510_0402_1% 1K_0402_5% 1K_0402_5% R399 R400 R142 R401 R402 R141 +3VS U22B A8 B8 APU_HDMI_TX2P APU_HDMI_TX2N D R429 R430 @ If use level shift, EC_SMB need pull up (pop R747 & R748) FCH_SID 0_0402_5% EC_SMB_DA2 0_0402_5% FCH_SID 19 14 15 16 17 18 19 20 Please be noted about TEST_18 and TEST_19 T0 FCH EC_SMB_DA2 13 +1.8VS A SAMTE_ASP-136446-07-B CONN@ TO EC 0_0402_5% APU_SIC D S EC_SMB_CK @ Q23 BSH111 1N_SOT23-3 R434 @ R432 R433 FCH_SIC 0_0402_5% EC_SMB_CK2 0_0402_5% FCH_SIC T0 FCH EC_SMB_CK2 TO EC Compal Secret Data Security Classification 2010/08/20 Issued Date 2011/08/20 Deciphered Date Title FT1 CTRL/DP/CRT THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC 0_0402_5% Rev 1.0 LA-7092P P5WE6/H6/S6 Date: Compal Electronics, Inc Wednesday, November 24, 2010 Sheet of 47 A B C D E U22E DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3 DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7 A16 B16 B20 A20 E23 E22 J22 J23 R22 P22 W22 V22 AC20 AC21 AB16 AC16 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3 M17 M16 M19 M18 N18 N19 L18 L17 DDR_CKE0 DDR_CKE1 DDR_CKE0 DDR_CKE1 D15 B19 D21 H22 P23 V23 AB20 AA16 DDR_RST# DDR_EVENT# DDR_RST# DDR_EVENT# DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7 DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB# F15 E15 DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1 W19 V15 U19 W15 DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB# T17 W16 U17 V16 DDR_A_RAS# DDR_A_CAS# DDR_A_WE# DDR_A_RAS# DDR_A_CAS# DDR_A_WE# L23 N17 U18 V19 V17 M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7 M_DATA8 M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15 DDR SYSTEM MEMORY R18 T18 F16 DDR_A_BS0 DDR_A_BS1 DDR_A_BS2 M_ADD0 M_ADD1 M_ADD2 M_ADD3 M_ADD4 M_ADD5 M_ADD6 M_ADD7 M_ADD8 M_ADD9 M_ADD10 M_ADD11 M_ADD12 M_ADD13 M_ADD14 M_ADD15 M_BANK0 M_BANK1 M_BANK2 M_DM0 M_DM1 M_DM2 M_DM3 M_DM4 M_DM5 M_DM6 M_DM7 M_DQS_H0 M_DQS_L0 M_DQS_H1 M_DQS_L1 M_DQS_H2 M_DQS_L2 M_DQS_H3 M_DQS_L3 M_DQS_H4 M_DQS_L4 M_DQS_H5 M_DQS_L5 M_DQS_H6 M_DQS_L6 M_DQS_H7 M_DQS_L7 M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23 M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31 M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39 M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47 M_CLK_H0 M_CLK_L0 M_CLK_H1 M_CLK_L1 M_CLK_H2 M_CLK_L2 M_CLK_H3 M_CLK_L3 M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55 M_RESET_L M_EVENT_L M_CKE0 M_CKE1 M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63 M0_ODT0 M0_ODT1 M1_ODT0 M1_ODT1 M0_CS_L0 M0_CS_L1 M1_CS_L0 M1_CS_L1 B14 A15 A17 D18 A14 C14 C16 D16 DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7 C18 A19 B21 D20 A18 B18 A21 C20 DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15 C23 D23 F23 F22 C22 D22 F20 F21 DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23 H21 H23 K22 K21 G23 H20 K20 K23 DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31 N23 P21 T20 T23 M20 P20 R23 T22 DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39 V20 V21 Y23 Y22 T21 U23 W23 Y21 DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47 Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18 DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55 AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15 DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63 M23 +MEM_VREF M22 R437 DDR_A_D[0 63] DDR_A_MA[0 15] DDR_A_DM[0 7] DDR_A_D[0 63] DDR_A_MA[0 15] DDR_A_DM[0 7] U22A PCIE_GTX_C_FRX_P0 PCIE_GTX_C_FRX_N0 PCIE_GTX_C_FRX_P0 PCIE_GTX_C_FRX_N0 AA6 Y6 PCIE_GTX_C_FRX_P1 PCIE_GTX_C_FRX_N1 PCIE_GTX_C_FRX_P1 PCIE_GTX_C_FRX_N1 AB4 AC4 PCIE_GTX_C_FRX_P2 PCIE_GTX_C_FRX_N2 PCIE_GTX_C_FRX_P2 PCIE_GTX_C_FRX_N2 AA1 AA2 PCIE_GTX_C_FRX_P3 PCIE_GTX_C_FRX_N3 PCIE_GTX_C_FRX_P3 PCIE_GTX_C_FRX_N3 Y4 Y3 +1.05VS R435 2K_0402_1% P_ZVDD_10 Y14 P_GPP_RXP0 P_GPP_RXN0 P_GPP_RXP1 P_GPP_RXN1 P_GPP_RXP2 P_GPP_RXN2 P_GPP_RXP3 P_GPP_RXN3 P_GPP_TXP0 P_GPP_TXN0 PCIE I/F R17 H19 J17 H18 H17 G17 H15 G18 F19 E19 T19 F17 E18 W17 E16 G15 P_GPP_TXP1 P_GPP_TXN1 P_GPP_TXP2 P_GPP_TXN2 P_GPP_TXP3 P_GPP_TXN3 P_ZVDD_10 P_ZVSS AB6 PCIE_FTX_GRX_P0 AC6 PCIE_FTX_GRX_N0 C518 1VGA@2 0.1U_0402_16V7K C519 1VGA@2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P0 PCIE_FTX_C_GRX_N0 AB3 PCIE_FTX_GRX_P1 AC3 PCIE_FTX_GRX_N1 C520 1VGA@2 0.1U_0402_16V7K C521 1VGA@2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P1 PCIE_FTX_C_GRX_N1 Y1 Y2 PCIE_FTX_GRX_P2 PCIE_FTX_GRX_N2 C522 1VGA@2 0.1U_0402_16V7K C523 1VGA@2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P2 PCIE_FTX_C_GRX_N2 V3 V4 PCIE_FTX_GRX_P3 PCIE_FTX_GRX_N3 C524 1VGA@2 0.1U_0402_16V7K C525 1VGA@2 0.1U_0402_16V7K PCIE_FTX_C_GRX_P3 PCIE_FTX_C_GRX_N3 AA14 P_ZVSS R436 1.27K_0402_1% Less than 1" Less than 1" UMI_RX0P UMI_RX0N AA12 Y12 UMI_RX1P UMI_RX1N AA10 Y10 UMI_RX2P UMI_RX2N AB10 AC10 UMI_RX3P UMI_RX3N AC7 AB7 P_UMI_RXP0 P_UMI_RXN0 P_UMI_RXP1 P_UMI_RXN1 P_UMI_RXP2 P_UMI_RXN2 P_UMI_RXP3 P_UMI_RXN3 P_UMI_TXP0 P_UMI_TXN0 UMI I/F DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6 DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15 P_UMI_TXP1 P_UMI_TXN1 P_UMI_TXP2 P_UMI_TXN2 P_UMI_TXP3 P_UMI_TXN3 AB12 AC12 UMI_TX0P_C UMI_TX0N_C C526 C527 2 0.1U_0402_16V7K 0.1U_0402_16V7K AC11 AB11 UMI_TX1P_C UMI_TX1N_C C528 C529 2 0.1U_0402_16V7K 0.1U_0402_16V7K AA8 Y8 UMI_TX2P_C UMI_TX2N_C C530 C531 2 0.1U_0402_16V7K 0.1U_0402_16V7K AB8 AC8 UMI_TX3P_C UMI_TX3N_C C532 C533 2 0.1U_0402_16V7K 0.1U_0402_16V7K UMI_TX0P UMI_TX0N UMI_TX1P UMI_TX1N UMI_TX2P UMI_TX2N UMI_TX3P UMI_TX3N ONTARIO-2M161000-1.6G_BGA413 15G@ M_VREF M_RAS_L M_CAS_L M_WE_L M_ZVDDIO_MEM_S ONTARIO-2M161000-1.6G_BGA413 15G@ 15 mils +1.5V 39.2_0402_1% +1.5V +1.5V R438 1K_0402_1% DDR_EVENT# 1K_0402_5% +MEM_VREF R149 1 R439 1K_0402_1% C535 1 1 C534 1000P_0402_50V7K 0.1U_0402_16V4Z Place within 1000 mils to APU 20100526 Compal Secret Data Security Classification Issued Date 2010/08/20 2011/08/20 Deciphered Date Title Compal Electronics, Inc FT1 DDRIII/UMI/PCIE THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 LA-7092P P5WE6/H6/S6 Date: A B C D Wednesday, November 24, 2010 E Sheet of 47 +APU_CORE +1.8VS 10U_0603_6.3V6M C577 10U_0603_6.3V6M C578 10U_0603_6.3V6M C579 10U_0603_6.3V6M 2 10U_0603_6.3V6M 1U_0402_6.3V6K C583 C584 1U_0402_6.3V6K C585 1U_0402_6.3V6K 1U_0402_6.3V6K C586 1U_0402_6.3V6K C587 180P_0402_50V8J C588 2 @ 10U_0603_6.3V6M 1U_0402_6.3V6K C548 1U_0402_6.3V6K C547 1U_0402_6.3V6K C538 0.1U_0402_16V7K C546 1U_0402_6.3V6K C549 FBMA-L11-201209-221LMA30T_0805 Change from SM010014520 to SD002000080 20100816 +1.05VS VDDPL_10 L31 +VDDL_10 U11 2 VDDIO_MEM_S_1 VDDIO_MEM_S_2 VDDIO_MEM_S_3 VDDIO_MEM_S_4 VDDIO_MEM_S_5 VDDIO_MEM_S_6 VDDIO_MEM_S_7 VDDIO_MEM_S_8 VDDIO_MEM_S_9 VDDIO_MEM_S_10 VDDIO_MEM_S_11 1 0.2A 5.5A VDD_10_1 VDD_10_2 VDD_10_3 VDD_10_4 U13 W13 V12 T12 2 FBMA-L11-201209-221LMA30T_0805 L32 2 0.5A VDD_33 +VDD_10 2 2 FBMA-L11-201209-221LMA30T_0805 Change from SM010014520 to SD002000080 20100816 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97 VSSBG_DAC C580 1 180P_0402_50V8J 2 S POLY C 330U 2.5V M D2E TPE LESR9M H1.8 ->+APU_CORE(Qty : 3) Unpop:2 +APU_CORE +APU_CORE_NB S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+APU_CORE_NB(Qty : 1) C591 0.1U_0402_16V7K C592 C593 0.1U_0402_16V7K C594 0.1U_0402_16V7K 10U_0603_6.3V6M 0.1U_0402_16V7K C595 B POWER C590 10U_0603_6.3V6M C Power Cap Summary APU S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 ->+APU_CORE_NB(Qty : 1) C589 D ONTARIO-2M161000-1.6G_BGA413 15G@ S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+APU_CORE(Qty : 2) +1.5V N13 N20 N22 P10 P14 R4 R7 R20 T6 T9 T11 T13 U4 U5 U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11 +3VS A4 ONTARIO-2M161000-1.6G_BGA413 15G@ C582 180P_0402_50V8J C537 C545 POWER 10U_0603_6.3V6M VDD_18_DAC 10U_0603_6.3V6M C684 VDDCR_NB_1 VDDCR_NB_2 VDDCR_NB_3 VDDCR_NB_4 VDDCR_NB_5 VDDCR_NB_6 VDDCR_NB_7 VDDCR_NB_8 VDDCR_NB_9 VDDCR_NB_10 VDDCR_NB_11 VDDCR_NB_12 VDDCR_NB_13 VDDCR_NB_14 VDDCR_NB_15 VDDCR_NB_16 VDDCR_NB_17 VDDCR_NB_18 VDDCR_NB_19 VDDCR_NB_20 VDDCR_NB_21 VDDCR_NB_22 DP Phy/IO G16 G19 E17 J16 L16 L19 N16 R16 R19 W18 U16 Change from SM010014520 to SD002000080 20100816 10U_0603_6.3V6M C576 U22D A7 B7 B11 B17 B22 C4 D5 D7 D9 D11 D14 B15 D17 D19 E7 E9 E12 E20 F8 F11 F13 G4 G5 G7 G9 G12 G20 G22 H6 H11 H13 J4 J5 J7 J20 K10 K14 L4 L6 L8 L11 L13 L20 L22 M7 N4 N6 N8 N11 L30 add Cap for CRT DVT +VDD_18_DAC W9 DDR3 C575 2A +1.8VS 0.15A PCIE/IO/DDR3 Phy +1.5V C 10U_0603_6.3V6M C574 +APU_CORE_NB 1U_0402_6.3V6K C573 0.1U_0402_16V7K 2 10U_0603_6.3V6M 0.1U_0402_16V7K 2 0.1U_0402_16V7K E8 E11 E13 F9 F12 G11 G13 H9 H12 K11 K13 L10 L12 L14 M11 M12 M13 N10 N12 N14 P11 P13 1U_0402_6.3V6K C572 C563 10A 10U_0603_6.3V6M C604 +APU_CORE_NB 1U_0402_6.3V6K C567 C562 0.1U_0402_16V7K C571 C555 180P_0402_50V8J 2 1U_0402_6.3V6K C558 C554 180P_0402_50V8J 0.1U_0402_16V7K C566 U8 W8 U6 U9 W6 T7 V7 0.1U_0402_16V7K C570 C553 1U_0402_6.3V6K VDD_18_1 VDD_18_2 VDD_18_3 VDD_18_4 VDD_18_5 VDD_18_6 VDD_18_7 1U_0402_6.3V6K 10U_0603_6.3V6M VDDCR_CPU_1 VDDCR_CPU_2 VDDCR_CPU_3 VDDCR_CPU_4 VDDCR_CPU_5 VDDCR_CPU_6 VDDCR_CPU_7 VDDCR_CPU_8 VDDCR_CPU_9 VDDCR_CPU_10 VDDCR_CPU_11 VDDCR_CPU_12 VDDCR_CPU_13 VDDCR_CPU_14 VDDCR_CPU_15 DIS PLL 0.1U_0402_16V7K 10U_0603_6.3V6M 2 10U_0603_6.3V6M 10U_0603_6.3V6M E5 E6 F5 F7 G6 G8 H5 H7 J6 J8 L7 M6 M8 N7 R8 L29 FBMA-L11-201209-221LMA30T_0805 GND C561 C540 GPU AND NB CORE 1 C544 DAC C560 C556 C552 1U_0402_6.3V6K 2 1U_0402_6.3V6K C559 0.1U_0402_16V7K C543 180P_0402_50V8J C557 C551 1U_0402_6.3V6K 10U_0603_6.3V6M C564 C550 C542 CPU CORE 10U_0603_6.3V6M 2 10U_0603_6.3V6M 180P_0402_50V8J C565 C541 C568 180P_0402_50V8J C569 C536 +VDD_18 0.1U_0402_16V7K C581 C539 2A TSense/PLL/DP/PCIE/IO D U22C 11A +APU_CORE 1 C596 1U_0402_6.3V6K C597 1U_0402_6.3V6K C598 1U_0402_6.3V6K S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+1.5V(Qty : 1) +1.5V S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->1.05VS(Qty : 1) +1.05VS S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+1.8VS(Qty : 1) +1.8VS DDR3 Socket 1U_0402_6.3V6K B S POLY C 330U 2V M X LESR6M SX H1.9 ->1.5V(Qty : 1) +1.5V +1.05VS FCH S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 ->1.1VS(Qty : 1) UMA unpop C621 + @ 390U_2.5V_10M C599 1 C600 0.1U_0402_16V7K C601 0.1U_0402_16V7K C602 0.1U_0402_16V7K C603 180P_0402_50V8J +1.1VS GPU 180P_0402_50V8J S POLY C 330U 2V M X LESR6M SX H1.9 ->VGA_CORE(Qty : 2) Unpop:1 +GPU_CORE S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+VGA_CORE(Qty : 1) S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU ->+1.5VSG(Qty : 1) +1.5V POWER 10U_0603_6.3V6M 1 1 330U_D2E_2.5VM_R9M 390U_2.5V_10M C605 + C606 + C607 + C1104+ C1105+ C616 @ @ @ 330U_D2E_2.5VM_R9M 330U_D2E_2.5VM_R9M 390U_2.5V_10M 2 2 2 C101 0.1U_0402_16V7K C102 0.1U_0402_16V7K 1 USB C103 180P_0402_50V8J By case (Along split) C617 + 390U_2.5V_10M C622 + C618 + C619 330U_D2_2.5VY_R9M 10U_0603_6.3V6M 2 390U_2.5V_10M 10U_0603_6.3V6M 390U_2.5V_10M C625 @ 10U_0603_6.3V6M 2 2 2 2 C615 C614 C613 A 10U_0603_6.3V6M Near CPU Socket Near CPU Socket Compal Secret Data Security Classification Near CPU Socket Issued Date 2010/08/20 Deciphered Date 2011/08/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC (390uF_2.5V_6.3x5.7_ESR10m)*1=(SF000002O00) Title Compal Electronics, Inc P07-FT1 PWR/VSS Size C Date: C612 C611 C610 180P_0402_50V8J C624 + 180P_0402_50V8J C685 180P_0402_50V8J C623 0.1U_0402_16V7K 1 C609 A 0.1U_0402_16V7K POWER C608 +1.8VS change 0603 for DVT 0.1U_0402_16V7K POWER +1.5V Near CPU Socket +USB_VCCA C104 180P_0402_50V8J +1.5V +APU_CORE_NB +1.5VSG S_A-P_CAP 220U 6.3V M C45 R17M SVPE H4.4 ->+USB_VCCA(Qty : 1) 0.1U_0402_16V7K +APU_CORE 180PF Qt'y follow the distance between CPU socket and DIMM0 180P_0402_50V8J C620 @ 10U_0603_6.3V6M Document Number Rev 1.0 LA-7092P P5WE6/H6/S6 Monday, November 15, 2010 Sheet of 47 +1.5V +1.5V JDIMM1 D DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 DDR_A_D[0 63] DDR_A_MA[0 15] DDR_A_DQS#0 DDR_A_DQS0 +1.5V DDR_A_D[0 63] DDR_A_MA[0 15] DDR_A_DM[0 7] R145 1K_0402_1% DDR_A_DM[0 7] DDR_A_D6 DDR_A_D7 R146 1K_0402_1% 15mil 15mil DDR_A_D2 DDR_A_D3 +1.5V DDR_A_D4 DDR_A_D5 +VREF_DQ DDR_A_D12 DDR_A_D13 +VREF_CA D 1000P_0402_50V7K VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 DDR_A_DM1 R147 1K_0402_1% DDR_RST# DDR_A_D14 DDR_A_D15 R148 1K_0402_1% DDR_A_DM0 0.1U_0402_16V4Z VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 DDR_A_D0 DDR_A_D1 1 C627 C626 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 +VREF_DQ 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 DDR_A_D30 DDR_A_D31 +1.5V DDR_CKE0 C DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_A_CLK0 DDR_A_CLK#0 DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMA# DDR_A_D32 DDR_A_D33 B DDR_A_DQS#4 DDR_A_DQS4 DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 DDR_A_D58 DDR_A_D59 A +3VS C646 C647 1 R150 10K_0402_5% R151 0.1U_0402_16V4Z 10K_0402_5% 2.2U_0603_6.3V4Z 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 205 G1 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 G2 206 FOX_AS0A626-U8SN-7F CONN@ DDR_CKE1 DDR_A_MA15 DDR_A_MA14 0.1U_0402_16V4Z C628 DDR_A_MA11 DDR_A_MA7 0.1U_0402_16V4Z C629 0.1U_0402_16V4Z C630 C631 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C632 0.1U_0402_16V4Z C633 0.1U_0402_16V4Z 2 C634 0.1U_0402_16V4Z C635 C636 C637 0.1U_0402_16V4Z C 0.1U_0402_16V4Z C638 0.1U_0402_16V4Z C110 DDR_A_MA6 DDR_A_MA4 DDR_A_MA2 DDR_A_MA0 DDR_A_CLK1 DDR_A_CLK#1 DDR_A_BS1 DDR_A_RAS# CRB 0.1u X1 DDR_CS0_DIMMA# DDR_A_ODT0 DDR_A_ODT1 4.7u X1 CRB DDR_A_D36 DDR_A_D37 C645 X2 +1.5V 2 C640 C641 @ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 1 C644 DDR_A_DM4 DDR_A_D38 DDR_A_D39 100U +0.75VS +VREF_CA 1000P_0402_50V7K 0.1U_0402_16V4Z 2 C642 + 4.7U_0603_6.3V6K C1102 330U_D2E_2.5VM_R9M B DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 330U ESR:9m H:2 P/N:SGA20331E10 Place near JDIMM1 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 EMI For DVT 10/20 DDR_A_D60 DDR_A_D61 +1.5V 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 2 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 C643 C675 C676 C678 A DDR_EVENT# FCH_SMDAT0 FCH_SMCLK0 +0.75VS DDR3 SO-DIMM A H:8mm Standard Type P/N:SP07000HA00 F/P:FOX_AS0A626-U8SN-7F_204P Compal Secret Data Security Classification Issued Date 2010/08/20 2011/08/20 Deciphered Date Title Compal Electronics, Inc DDR3 SODIMM-I Socket THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 LA-7092P P5WE6/H6/S6 Date: 0.1U_0402_16V4Z 2 Wednesday, November 24, 2010 Sheet of 47 +1.5V +1.5V JDIMM2 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 +VREF_DQ C680 DDR_A_D0 DDR_A_D1 C681 DDR_A_DM0 1000P_0402_50V7K DDR_A_D2 DDR_A_D3 0.1U_0402_16V4Z D DDR_A_D8 DDR_A_D9 DDR_A_DQS#1 DDR_A_DQS1 DDR_A_D10 DDR_A_D11 DDR_A_D16 DDR_A_D17 DDR_A_DQS#2 DDR_A_DQS2 DDR_A_D18 DDR_A_D19 DDR_A_D24 DDR_A_D25 DDR_A_DM3 DDR_A_D26 DDR_A_D27 VREF_DQ VSS2 DQ0 DQ1 VSS4 DM0 VSS5 DQ2 DQ3 VSS7 DQ8 DQ9 VSS9 DQS#1 DQS1 VSS11 DQ10 DQ11 VSS13 DQ16 DQ17 VSS15 DQS#2 DQS2 VSS18 DQ18 DQ19 VSS20 DQ24 DQ25 VSS22 DM3 VSS23 DQ26 DQ27 VSS25 VSS1 DQ4 DQ5 VSS3 DQS#0 DQS0 VSS6 DQ6 DQ7 VSS8 DQ12 DQ13 VSS10 DM1 RESET# VSS12 DQ14 DQ15 VSS14 DQ20 DQ21 VSS16 DM2 VSS17 DQ22 DQ23 VSS19 DQ28 DQ29 VSS21 DQS#3 DQS3 VSS24 DQ30 DQ31 VSS26 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 DDR_A_D4 DDR_A_D5 DDR_A_DQS#0 DDR_A_DQS0 DDR_A_D[0 63] 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 201 203 DDR_CKE0 DDR_A_BS2 DDR_A_MA12 DDR_A_MA9 DDR_A_MA8 DDR_A_MA5 DDR_A_MA3 DDR_A_MA1 DDR_B_CLK2 DDR_B_CLK#2 DDR_A_MA10 DDR_A_BS0 DDR_A_WE# DDR_A_CAS# DDR_A_MA13 DDR_CS1_DIMMB# DDR_A_D32 DDR_A_D33 DDR_A_DQS#4 DDR_A_DQS4 B DDR_A_D34 DDR_A_D35 DDR_A_D40 DDR_A_D41 DDR_A_DM5 DDR_A_D42 DDR_A_D43 DDR_A_D48 DDR_A_D49 DDR_A_DQS#6 DDR_A_DQS6 DDR_A_D50 DDR_A_D51 DDR_A_D56 DDR_A_D57 DDR_A_DM7 For DRAM strap pin reservation 20100817 R961 R153 @ DDR_A_D58 DDR_A_D59 10K_0402_5% 10K_0402_5% +3VS A 1 C667 @ R154 10K_0402_5% 0.1U_0402_16V4Z 2 2.2U_0603_6.3V4Z C668 DDR_A_DM[0 7] only one 4.7k G1 CKE1 VDD2 A15 A14 VDD4 A11 A7 VDD6 A6 A4 VDD8 A2 A0 VDD10 CK1 CK1# VDD12 BA1 RAS# VDD14 S0# ODT0 VDD16 ODT1 NC2 VDD18 VREF_CA VSS28 DQ36 DQ37 VSS30 DM4 VSS31 DQ38 DQ39 VSS33 DQ44 DQ45 VSS35 DQS#5 DQS5 VSS38 DQ46 DQ47 VSS40 DQ52 DQ53 VSS42 DM6 VSS43 DQ54 DQ55 VSS45 DQ60 DQ61 VSS47 DQS#7 DQS7 VSS50 DQ62 DQ63 VSS52 EVENT# SDA SCL VTT2 G2 D DDR_A_DM[0 7] DDR_A_DM1 DDR_RST# DDR_A_D14 DDR_A_D15 DDR_A_D20 DDR_A_D21 DDR_A_DM2 DDR_A_D22 DDR_A_D23 DDR_A_D28 DDR_A_D29 DDR_A_DQS#3 DDR_A_DQS3 +1.5V DDR_A_D30 DDR_A_D31 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204 0.1U_0402_16V4Z 0.1U_0402_16V4Z DDR_CKE1 C45 0.1U_0402_16V4Z 2 C652 C653 1 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C654 C655 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C682 1 0.1U_0402_16V4Z C46 C683 C47 0.1U_0402_16V4Z C48 0.1U_0402_16V4Z C49 0.1U_0402_16V4Z C DDR_A_MA11 DDR_A_MA7 DDR_A_MA6 DDR_A_MA4 CRB 0.1u X1 4,7uX1 DDR_A_MA2 DDR_A_MA0 +0.75VS DDR_B_CLK3 DDR_B_CLK#3 C50 @ 0.1U_0402_16V4Z DDR_A_BS1 DDR_A_RAS# DDR_CS0_DIMMB# DDR_B_ODT0 C51 C664 0.1U_0402_16V4Z 4.7U_0603_6.3V6K DDR_B_ODT1 +VREF_CA DDR_A_D36 DDR_A_D37 C665 Place near JDIMM2 C666 DDR_A_DM4 DDR_A_D38 DDR_A_D39 0.1U_0402_16V4Z 1000P_0402_50V7K B DDR_A_D44 DDR_A_D45 DDR_A_DQS#5 DDR_A_DQS5 DDR_A_D46 DDR_A_D47 DDR_A_D52 DDR_A_D53 DDR_A_DM6 DDR_A_D54 DDR_A_D55 DDR_A_D60 DDR_A_D61 DDR_A_DQS#7 DDR_A_DQS7 DDR_A_D62 DDR_A_D63 DDR_EVENT# FCH_SMDAT0 FCH_SMCLK0 A +0.75VS 206 FOX_AS0A626-U4SN-7F CONN@ R962 10K_0402_5% Compal Secret Data Security Classification DDR3 SO-DIMM B H:4mm Standard Type P/N:SP07000H800 F/P:FOX_AS0A626-U4SN-7F_204P For DRAM strap pin reservation 20100817 2010/08/20 Issued Date 2011/08/20 Deciphered Date Title Compal Electronics, Inc DDR3 SODIMM-II Socket THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 1.0 LA-7092P P5WE6/H6/S6 Date: 0.1U_0402_16V4Z 2 DDR_A_MA15 DDR_A_MA14 CRB 205 CKE0 VDD1 NC1 BA2 VDD3 A12/BC# A9 VDD5 A8 A5 VDD7 A3 A1 VDD9 CK0 CK0# VDD11 A10/AP BA0 VDD13 WE# CAS# VDD15 A13 S1# VDD17 NCTEST VSS27 DQ32 DQ33 VSS29 DQS#4 DQS4 VSS32 DQ34 DQ35 VSS34 DQ40 DQ41 VSS36 DM5 VSS37 DQ42 DQ43 VSS39 DQ48 DQ49 VSS41 DQS#6 DQS6 VSS44 DQ50 DQ51 VSS46 DQ56 DQ57 VSS48 DM7 VSS49 DQ58 DQ59 VSS51 SA0 VDDSPD SA1 VTT1 DDR_A_MA[0 15] DDR_A_D12 DDR_A_D13 C44 C DDR_A_D[0 63] DDR_A_MA[0 15] DDR_A_D6 DDR_A_D7 Wednesday, November 24, 2010 Sheet of 47 LCD/LED PANEL Conn LCD POWER CIRCUIT JLVDS1 41 42 43 44 45 46 +LCDVDD +3VS +3VALW For LCD flash Change as 10k ohm D R396 300_0603_5% W=60mils R393 10K_0402_5% C669 4.7U_0603_6.3V6K Change 0603 size For DVT Q81 SSM3K7002F_SC59-3 G R397 1K_0402_5% S S UMA@ LCDVDD_ON R963 0_0402_5% G D W=60mils C1005 4.7U_0603_6.3V6K S R395 1 2 C1006 0.1U_0402_16V4Z Change 0603 size For DVT 100K_0402_5% +LCDVDD Q83 SSM3K7002F_SC59-3 1 DISO@ R964 0_0402_5% VGA_ENVDD D G APU_ENVDD C670 0.047U_0402_16V7K AO3413L_SOT23-3 Q82 1 2 D 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 G1 G2 G3 G4 G5 G6 SM010014520 3000ma 220ohm@100mhz DCR 0.04 W=60mils 1 2 APU_ENBKL R156 UMA@ 0_0402_5% B+ L113 1.2UH_1127AS-1R2N_2.4A_30% R419 @ 0_0805_5% ENBKL R426 @ R157 100K_0402_1% +3VS 0_0805_5% C674 68P_0402_50V8J EMI request for MP R484 C1007 220P_0402_50V7K INVT_PWM C679 220P_0402_50V7K DISPOFF# 10K_0402_5% R485 INVT_PWM DISPOFF# I2CC_SCL I2CC_SDA @ +LCDVDD R841 0_0603_5% +LCDVDD D W=60mils +3VS DAC_BRIG TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+ TXCLKTXCLK+ R862 @ 0_0402_5% LOCAL_DIM R860 @ 0_0402_5% COLOY_ENG_EN +3VS USB20_N5 USB20_P5 C D15 @ +LCDVDD Place closed to JLVDS1 0_0402_5% BKOFF# +LCDVDD_L @ R483 10K_0402_5% +3VS 220P_0402_50V7K DAC_BRIG C677 +INVPWR_B+ IPEX_20143-040E-20F CONN@ C673 680P_0402_50V7K +INVPWR_B+ L2 FBMA-L11-201209-221LMA30T_0805 L1 FBMA-L11-201209-221LMA30T_0805 0_0402_5% C VGA_ENBKL R1097 DISO@ W=60mils 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 DISPOFF# C671 10U_0603_6.3V6M CH2 Vp Vn USB20_N5 C672 USB20_P5 RB751V_SOD323 D4 @ CH3 0.1U_0402_16V4Z CH4 CH1 CM1293-04SO_SOT23-6 Change P/N as SC300000B00 Change 0603 size For DVT VGA ONLY 4 4 B VGA_TXCLK+ VGA_TXCLK0_0404_4P2R_5% VGA_TXOUT2+ VGA_TXOUT20_0404_4P2R_5% VGA_TXOUT1+ VGA_TXOUT10_0404_4P2R_5% VGA_TXOUT0+ VGA_TXOUT00_0404_4P2R_5% DISO@RP2 DISO@ RP2 TXOUT2+ TXOUT2DISO@RP4 DISO@ RP4 TXOUT1+ TXOUT1DISO@RP6 DISO@ RP6 TXOUT0+ TXOUT0DISO@RP8 DISO@ RP8 I2CC_SCL I2CC_SDA 0_0402_5% DISO@ R270 0_0402_5% R272 DISO@ VGA_LCD_CLK VGA_LCD_DAT VGA_TXCLK+ VGA_TXCLK- VGA_TXOUT2+ VGA_TXOUT2- APU_BLPWM VGA_TXOUT1+ VGA_TXOUT1- EC_INVT_PWM VGA_INVT_PWM VGA_TXOUT0+ VGA_TXOUT0- INVT_PWM R1098 UMA@ 0_0402_5% R158 DISO@ 0_0402_5% R1099 @ 0_0402_5% TXCLK+ TXCLK- R1100 100K_0402_5% B VGA_LCD_CLK VGA_LCD_DAT UMA ONLY TXCLK+ TXCLK- 4 4 UMA@RP1 UMA@ RP1 TXOUT2+ TXOUT2UMA@RP3 UMA@ RP3 TXOUT1+ TXOUT1UMA@RP5 UMA@ RP5 TXOUT0+ TXOUT0UMA@RP7 UMA@ RP7 A I2CC_SCL I2CC_SDA APU_TXCLK+ APU_TXCLK0_0404_4P2R_5% APU_TXOUT2+ APU_TXOUT20_0404_4P2R_5% APU_TXOUT1+ APU_TXOUT10_0404_4P2R_5% APU_TXOUT0+ APU_TXOUT00_0404_4P2R_5% 0_0402_5% UMA@ R269 0_0402_5% R271 UMA@ APU_LCD_CLK APU_LCD_DATA APU_TXCLK+ APU_TXCLK- APU_TXOUT2+ APU_TXOUT2- APU_TXOUT1+ APU_TXOUT1- APU_TXOUT0+ APU_TXOUT0- A APU_LCD_CLK APU_LCD_DATA Compal Secret Data Security Classification 2010/08/20 Issued Date 2011/08/20 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D B DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Compal Electronics, Inc LVDS/CAMERA Document Number Rev 1.0 LA-7092P P5WE6/H6/S6 Wednesday, November 24, 2010 Sheet 10 of 47 A B C D E +USB_VCCA +3VALW SVPE, 4.2m, 18mohm Change P/N SF000002Y00 +USB_VCCA R447 4.7U_0603_6.3V6K VOUT VOUT VOUT FLG Change 0603 size For DVT C713 GND VIN VIN EN + R446 100K_0402_5% 80mil C712 10K_0402_5% C714 0.1U_0402_16V4Z AP2301MPG-13_MSOP8 C711 470P_0402_50V7K USB_OC0# R448 SYSON# 220U_6.3V_M W=80mils 1 EPAD U24 +5VALW 1 +USB_VCCA @ 0_0402_5% L83 USB20_N0 USB20_N0 JUSB1 2 USB20_P0 VOUT VOUT VOUT FLG 80mil R450 100K_0402_5% 3 AP2301MPG-13_MSOP8 WCM2012F2S-900T04_0805 USB_OC2# R451 R452 10K_0402_5% @ 2 GND GND GND GND SUYIN_020133MB004S580ZL-C CONN@ 0_0402_5% USB_OC1# 4.7U_0603_6.3V6K GND VIN VIN EN R449 @ 0_0402_5% 2 Change 0603 size For DVT C715 EPAD U25 USB20_P0 +USB_VCCB 4 USB20_N0_R USB20_P0_R +3VALW +5VALW C716 0.1U_0402_16V4Z SYSON# D10 USB20_N0_R SA00003XM00 S IC AP2301MPG-13 MSOP 8P PWR SW USB20_P0_R 2 +USB_VCCA To USB/B Connector PJUSB208_SOT23-6 Change P/N SC300000O00 for ESD +USB_VCCB USB20_N2 USB20_P2 USB20_N1 USB20_P1 S BT@ R453 10K_0402_5% BT_ON# USB20_N2 USB20_P2 +BT_VCC C721 +BT_VCC Change 0603 size For DVT 10 GND GND AO3413L_SOT23-3 W=40mils BT@ 0.1U_0402_16V4Z JBT1 1U_0402_6.3V4Z C720 G D ACES_85201-1205N CONN@ BT@ Q24 BT@ C719 BT@ C722 BT@ GND GND USB20_N1 USB20_P1 BT@ 0.1U_0402_16V4Z BT@ R454 300_0603_5% 4.7U_0603_6.3V6K 0.1U_0402_16V4Z 13 14 C718 USB20_P7 USB20_N7 +3VS 1 10 11 12 10 11 12 +3VALW Bluetooth Conn JUSB2 D (Port 1,2) S BT@ Q25 2N7002_SOT23 G ACES_87213-0800G CONN@ 4 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/08/20 Deciphered Date 2011/08/20 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC USB/BT/USBsub Rev 1.0 LA-7092P P5WE6/H6/S6 Date: A B C D Monday, November 29, 2010 Sheet E 33 of 47 FAN1 Conn Power Button Change 0603 size For DVT +5VS +VCC_FAN1 ON/OFF 51_ON# C824 1000P_0402_50V7K R568 10K_0402_5% 1000P_0402_50V7K 40mil S 2N7002_SOT23 10K_0402_5% C825 1000P_0402_50V7K G1 G2 CONN@ ACES_85204-03001 H4 H_3P0 1 H12 H_3P0 H3 H_4P0 H19 H_3P0 H24 H_3P0 1 H11 H_3P0 H2 H_4P0 1 H1 H_3P0 H18 H_3P4 H14 H_3P0 2010/08/20 Deciphered Date H7 H_3P0 H8 H_3P0 H20 H_4P2 H21 H_4P2 H17 H_3P0X3P5N H10 H_3P0 H22 H_4P2 H23 H_4P2 H13 H_3P0N FD4 FD3 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 Compal Electronics, Inc Compal Secret Data Security Classification Issued Date FD2 H5 H_3P0 FD1 R496 Q27 G EC_ON EC_ON FAN_SPEED1 SMT1-05-A_4P JFAN1 +VCC_FAN1 D 1 Bottom Side @ SW C773 +3VS 0.01U_0402_25V4Z Change to SC600000B00 Change 0603 size For DVT C823 10U_0603_6.3V6M APL5607KI-TRG_SO8 @ DAN202UT106_SC70-3 ON/OFFBTN# C822 0_0402_5% 1 R567 @ D26 BAS16_SOT23-3 EN_DFAN1 GND GND GND GND D12 EN VIN VOUT VSET ON/OFFBTN# Bottom Side @ SW SMT1-05-A_4P U37 100K_0402_5% R495 @ 10K_0603_5% D25 1SS355_SOD323-2 @ R566 0_0603_5% @ 1 @ 10K_0603_5% +5VS 10U_0603_6.3V6M R494 R493 C821 1 +3VALW TOP Side ON/OFF switch 2011/08/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Other IO/USB (right) Size Document Number Custom Rev 1.0 LA-7092P P5WE6/H6/S6 Date: W ednesday, November 24, 2010 Sheet 34 of 47 C +3VALW TO +3VS ACIN Change P/N SB548000210 2 3 S VGA_PWR_ON S SSM3K7002FU_SC70-3 D S Q68 2N7002_SOT23 G R1123 100K_0402_5% 2 VGA_PWR_ON# VGA_PWR_ON# SUSP G Q65 2N7002_SOT23 Q67 G R1119 100K_0402_5% C1463 0.1U_0603_25V7K D 200K_0402_5% 1 +5VALW R1120 470_0603_5% S R1134 10K_0402_5% Change 0603 size For DVT R1122 2 1 Q77 2N7002_SOT23 S Q62 2N7002_SOT23 R1118 100K_0402_5% D G D G 2 PE_GPIO1 D SUSP# PE_GPIO1# PE_GPIO1# C1461 R1117 100K_0402_5% 1 R1115 10K_0402_5% 1.5_VDDC_PWREN# +1.5VS 10U_0603_6.3V6M Q59 2N7002_SOT23 +5VALW 1.5_VDDC_PWREN 2 G R1121 S S R1131 100K_0402_5% D S 100K_0402_5% 1 1 S 0.1U_0603_25V7K D G +5VALW SUSP G Q60 2N7002_SOT23 C1456 Q63 SI2301CDS-T1-GE3_SOT23-3 SUSP# D +1.5VS Q58 2N7002_SOT23 R1113 10K_0402_5% 1.5_VDDC_PWREN# +1.5V D G R1110 470_0603_5% SUSP SUSP S VGA_ON# 1 Q57 2N7002_SOT23 D R1116 100K_0402_5% R1114 100K_0402_5% Change 0603 size For DVT SUSP Q61 G 2N7002_SOT23 10U_0603_6.3V6M C1455 2 1U_0402_6.3V4Z 3VS_GATE 120K_0402_5% R1112 +VSB 0.1U_0603_25V7K 10U_0603_6.3V6M 2 10U_0603_6.3V6M Audio issue For DVT C1452 +5VALW 1 Q52 2N7002_SOT23 1 C1454 S +5VALW C1451 VGA_ON S D G R1109 100K_0402_5% S R1107 10K_0402_5% U41 SI4800BDY-T1-GE3_SO8 C1453 D ACIN G +3VALW S 2N7002_SOT23 VLDT_EN# G Q54 SYSON S +3VS Change 0603 size For DVT D Q51 2N7002_SOT23 G 2 Q56 G 2N7002_SOT23 D VLDT_EN# R1106 0.1U_0603_25V7K 300K_0402_5% Q55 G 2N7002_SOT23 1.1VS_GATE VLDT_EN SYSON# SYSON# D 47K_0402_5% 470_0603_5% 1 R1105 VLDT_EN# R1102 +VSB C1450 SUSP 2 Change 0603 size For DVT S 10U_0603_6.3V6M 1 10U_0603_6.3V6M C1449 2 1U_0402_6.3V4Z D C1447 2 SUSP G Q53 2N7002_SOT23 S 5VS_GATE 100K_0402_5% R1103 R1104 C1448 1K_0402_5% D Change 0603 size For DVT +VSB R1101 470_0603_5% R1108 100K_0402_5% R1111 100K_0402_5% 10U_0603_6.3V6M C1444 2 1U_0402_6.3V4Z 10U_0603_6.3V6M 2 10U_0603_6.3V6M C1446 1 C1445 +1.1VS U39 SI4800BDY-T1-GE3_SO8 Change 0603 size For DVT +5VALW Change P/N SB548000210 +1.1VALW 1 +5VS C1443 +5VALW +1.1VALW TO +1.1VS Change P/N SB548000210 U38 SI4800BDY-T1-GE3_SO8 Change 0603 size For DVT E +5VALW TO +5VS +5VALW D B A 1 D D D SUSP G Q80 2N7002_SOT23 S S VLDT_EN# G Q74 2N7002_SOT23 S SYSON# G Q78 2N7002_SOT23 3 S D 1 R1126 470_0603_5% VGA@ R1128 470_0603_5% R1137 470_0603_5% 2 +VGA_CORE R1135 470_0603_5% +1.1VS +0.75VS +1.5V 1.5_VDDC_PWREN# G Q28 2N7002_SOT23 VGA@ 2010/08/20 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2011/08/20 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC DC Interface Rev 1.0 LA-7092P P5WE6/H6/S6 Date: A B C D Monday, November 29, 2010 Sheet E 35 of 47 1 PC3 100P_0402_50V8J PC2 100P_0402_50V8J 2 PC1 1000P_0402_50V7K VIN PL1 SMB3025500YA_2P 2 GND GND @ PJP1 ACES_50305-00441-001 PC4 1000P_0402_50V7K D D VIN PD2 LL4148_LL34-2 BATT+ 1 PD1 LL4148_LL34-2 51_ON# VS PJ1 PC6 0.1U_0603_25V7K +3VALWP 1 PJ2 +3VALW +1.8VSP (4.73A,200mils ,Via NO.= 10) +1.8VS C (3A,120mils ,Via NO.=6) PJ3 PR4 22K_0402_5% +5VALWP 1 PJ4 +5VALW +1.1VALWP PreCHG @ (3.15A,140mils ,Via NO.=7) 1 PJ6 +VSB +0.75VSP 2 +0.75VS (3A,120mils ,Via NO.=6) (120mA,40mils ,Via NO.= 2) @PJP3 @ PJP3 JUMP_43X118 2 +VGA_COREP @PJP4 @ PJP4 JUMP_43X118 2 +VGA_CORE B (13A,520mils ,Via NO.= 26) 12 @ PR13 100K_0402_5% @ PD4 PJ11 +1.05VSP 3 BAS40CW_SOT323-3 @PQ3 @ PQ3 PDTC115EU_SOT323-3 @ PQ4 PDTC115EU_SOT323-3 1 +1.05VS JUMP_43X118 PJ7 (6A,240mils ,Via NO.=12) +1.5VP +5VALWP JUMP_43X79 @ PR12 1K_1206_5% ACOFF +1.1VALW (5A,200mils ,Via NO.= 10) B+ PR9 @ @ PR11 1K_1206_5% B PR10 1 @ PR8 1K_1206_5% 100K_0402_5% @PQ2 @ PQ2 TP0610K-T1-E3_SOT23-3 +3VLP @PD3 @ PD3 LL4148_LL34-2 100K_0402_5% PR7 0_1206_5% VIN 2 JUMP_43X118 JUMP_43X39 PR5 0_0603_5% JUMP_43X118 PJ5 +VSBP +CHGRTC 2 JUMP_43X118 JUMP_43X118 PR2 68_1206_5% PR3 100K_0402_5% C PC5 0.22U_0603_25V7K N1 PR1 68_1206_5% PQ1 TP0610K-T1-E3_SOT23-3 +1.5V JUMP_43X118 PJ13 1 2 JUMP_43X118 (7A,280mils ,Via NO.=14) PJ16 +1.5VSP 1 +1.5VS1 JUMP_43X118 (1A,40mils ,Via NO.= 2) A Compal Secret Data Security Classification Issued Date 2010/07/13 2011/07/13 Deciphered Date Title A Compal Electronics, Inc PWR DCIN / Pre-charge THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Wednesday, November 24, 2010 Sheet 36 of 47 B C UGATE 17 DH_CHG PC23 0.1U_0603_25V7K BST_CHGA 12 15 VADJ LGATE 14 GND PGND 13 6251VDDP VDDP ACLIM PD8 RB751V-40_SOD323-2 DL_CHG PC28 4.7U_0603_6.3V6M 1 @ @ PR44 15.4K_0402_1% CALIBRATE# PR45 31.6K_0402_1% 6251VDD CC=0.6~4.48A IREF=0.43V~3.24V PR48 10K_0402_1% PR47 10K_0402_1% PR46 47K_0402_5% ACIN PACIN PR49 14.3K_0402_1% ACPRN PQ19 PDTC115EU_SOT323-3 Kv Rinternal ic=514K Rec=3K R1=PR379=15.4K R2=PR381=31.6K R=514K//31.6K//(15.4K+3k)=11.372K r=514K//514K//31.6K=28.14K Vcell=0.175*Vadj+3.99v 4.2V=0.175*Vadj+3.99V =>Vadj=1.2V Vadj=Vref*(R/(R+514K))+CALIBRATE*(r/(r=514K)) 1.1483=CALIBRATE*0.6046 =>CALIBRATE=1.899 1.899=(4.2-(Vcell+A*0.175))*Kv=(4.2-(4.2+A*0.175))*Kv A=Vref*(R/(R+514K))=0.052 Kv=9.451 Compal Secret Data Security Classification Issued Date 2010/07/13 Deciphered Date 2011/07/13 Title Compal Electronics, Inc PWR-CHARGER THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A PC253 0.1U_0603_25V7K BATT+ PR34 0.02_1206_1% S Ki Vchlim=Iref*(PR374/(PR372+PR374)) =Iref*(100K/(80.6K+100K)) =Iref*0.5537 Ichanrge=(165mV/PR369)*(Vchlim/3.3V) =(165m/20m)*(1/3.3V)*Iref*0.5537 =1.3842*Iref Iref=0.7224*Ichanrge =>Ki=0.7224 12.60V PC16 10U_1206_25V6M PR41 4.7_0603_5% 12600mV PQ16 AO4466_SO8 26251VDD 11 TCR=50ppm / C PL2 10UH_PCMB104T-100MS_6A_20% CHG 2 PR37 0_0603_5% BST_CHG 1 PR43 20K_0402_1% 10 @ PC17 2200P_0402_25V7K @ PQ12 2N7002W -T/R7_SOT323-3 16 BOOT G CHLIM S VREF PQ61 2N7002W -T/R7_SOT323-3 PACIN G PC26 10U_1206_25V6M S D PHASE ICM 18 19 CSIP VCOMP PQ15 AO4466_SO8 PC25 10U_1206_25V6M ACPRN 2 1 CSOP D 20 IREF=0.7224*Icharge Normal 3S LI-ON Cells PC11 2200P_0402_25V7K 1 CSIN CSON ICOMP @ PR21 100K_0402_5% ACPRN CV mode PC10 0.1U_0603_25V7K 2 PC14 1000P_0402_25V8J 2 V1 PR28 20_0402_5% PC18 0.047U_0402_16V7K PR29 20_0402_5% PR30 PC21 20_0402_5% 0.1U_0603_25V7K PR32 2_0402_5% LX_CHG PR31 PC15 DCIN 1 Charging Voltage (0x15) BATT Type PQ9 PDTC115EU_SOT323-3 PR35 4.7_1206_5% PC19 6800P_0402_25V7K VIN ISL6251AHAZ-T_QSOP24 65W/90W# CP mode Iinput=(1/0.02)(0.05*Vaclm/2.39+0.05) where Vaclm=1.502V, Iinput=4.07A PC27 680P_0402_50V7K 21 6251aclim D G PQ18 2N7002W -T/R7_SOT323-3 PR357 200K_0402_1% CSOP ACOFF PD12 1SS355_SOD323-2 CELLS PQ17 PDTC115EU_SOT323-3 PC9 10U_1206_25V6M 1 0.01U_0402_25V7K 10K_0402_1% PR33 100_0402_1% 6251VREF PC22 1U_0402_16V7K 12.1K_0402_1% PR23 14.3K_0402_1% PR40 6251VREF PR15 10K_0402_1% ACSETIN 2 ACOFF PR22 10_1206_5% 1 CSON PR42 2.55K_0402_1% PR39 100K_0402_1% ACOFF VIN PR26 EN 22 6251_EN PC24 0.01U_0402_25V7K IREF PR36 80.6K_0402_1% 1 PR38 47K_0402_5% PR16 47K_0402_1% PD9 1SS355_SOD323-2 @ S ADP_I 23 PC20 G PACIN 24 DCIN ACSET ACPRN PQ14B DMN66D0LDW -7_SOT363-6 3 D 0.1U_0603_25V7K ACSETIN S PQ14A DMN66D0LDW -7_SOT363-6 VDD 3S/4S# PQ13 PDTC115EU_SOT323-3 G PD5 RB751V-40_SOD323-2 PU1 1 PR27 150K_0402_1% PQ10 PDTC115EU_SOT323-3 PR18 191K_0402_1% 6251VDD PR24 0_0402_5% CSIN VIN PreCHG FSTCHG PR25 47K_0402_5% 6251VDD D 2 CHG_B+ PL22 HCB4532KF-800T90_1812 CSIP 47K PQ8 PDTA144EU_SOT323-3 PC13 2.2U_0603_6.3V6K PR17 200K_0402_1% V1 47K PR14 0.02_2512_1% PC7 5600P_0402_25V7K 2 PR19 200K_0402_1% PC12 0.1U_0603_25V7K 1 P3 PQ7 SI4459ADY-T1-GE3_SO8 4 100K_0402_1% P2 PQ6 AO4407A_SO8 VIN PL17 1.2UH_1231AS-H-1R2N=P3_2.9A_30% B+ CP = 85%*Iada ; CP = 4.07A ADP_I = 19.9*Iadapter*Rsense D PQ5 AO4407A_SO8 @ PC30 10U_1206_25V6M @ PC56 10U_1206_25V6M PC8 10U_1206_25V6M A Iada=0~4.74A(90W/19V=4.736A) B C Rev 0.1 P5WE0 M/B LA-6901P Schematic W ednesday, November 24, 2010 D Sheet 37 of 47 PC29 1U_0603_10V6K 2VREF_8205 1 12 LGATE2 LGATE1 19 LG_5V PL5 4.7UH_PCMC063T-4R7MN_5.5A_20% 2 RT8205EGQW _W QFN24_4X4 NC PC38 0.1U_0603_25V7K PC37 2200P_0402_50V7K LX_5V 18 VIN VREG5 17 16 GND SKIPSEL EN 13 PC36 4.7U_0805_25V6-K UG_5V 20 LG_3V 2 AO4712_SO8 PQ23 PC46 1U_0603_10V6K RT8205_B+ 2VREF_8205 S PC47 4.7U_0805_10V6K VL Typ: 175mA +5VALWP + PC43 220U_6.3V_M B TONSEL=VREF (1)SMPS1=300KHZ (+5VALWP) (2)SMPS2=375KHZ(+3VALWP) +3.3VALWP Ipeak=6.768A ; 1.2Ipeak=8.12A; Imax=4.738A f=375KHz, L=4.7UH,Rentrip=162k ohm Rdson=15~18m ohm 1/2Delta I = 1/2 *(19-3)*(3/19)/(375KHz*4.7UH)=0.774A Vlimit=10*10^-6*162Kohm/10=0.162V Ilimit=0.162/(18m*1.2)~0.162/(15m*1.2)=7.5A~9A Iocp=8.274A~9.774A +5VALWP Ipeak=7A ; 1.2Ipeak=8.4A; Imax=4.9A f=300KHz, L=4.7UH,Rentrip=154k ohm Rdson=15~18m ohm 1/2Delta I = 1/2 *(19-5)*(5/19)/(300KHz*4.7UH)=1.306A Vlimit=10*10^-6*154Kohm/10=0.15V Ilimit=0.15/(18m*1.2)~0.15/(15m)=7.13~10.26A Iocp=8.44~9.86A Compal Secret Data Security Classification 2010/07/13 Issued Date 21 @ PR60 4.7_1206_5% PHASE1 @ PC45 680P_0402_50V7K PHASE2 11 SPOK A PC49 2.2U_0603_6.3V6K 2 PR66 100K_0402_1% VS PR67 40.2K_0402_1% PQ24A DMN66D0LDW -7_SOT363-6 PQ25 PDTC115EU_SOT323-3 PQ27 PDTC115EU_SOT323-3 D G EC_ON S G 22 UGATE1 VFB=2.0V 2N7002W -T/R7_SOT323-3 PQ26 ACPRN BOOT1 PR57 PC41 0_0603_5% 0.1U_0603_25V7K BST_5V 2 PR64 100K_0402_1% VL A 23 LX_3V PC35 4.7U_0805_25V6-K ENTRIP1 UGATE2 PC48 0.1U_0603_25V7K G S D 24 PR62 100K_0402_1% ENTRIP2 D PQ24B DMN66D0LDW -7_SOT363-6 PR65 200K_0402_5% VO1 PGOOD C PQ21 AO4466_SO8 B+ ENTRIP1 PR63 0_0402_5% 1 BOOT2 10 PR61 499K_0402_1% B MAINPWON ENTRIP1 FB1 REF UG_3V FB2 BST_3V PR59 @ 0_0402_5% MAINPW ON TONSEL VREG3 15 PQ22 AO4712_SO8 ENTRIP2 VO2 14 2 0_0603_5% PC40 0.1U_0603_25V7K @ PR58 4.7_1206_5% 2 P PAD RT8205_B+ PR55 154K_0402_1% PR56 + @ PC44 680P_0402_50V7K PC42 220U_6.3V_M 25 +3VLP 1 PR53 20K_0402_1% PU2 4.7UH_PCMC063T-4R7MN_5.5A_20% PL4 +3VALWP PR52 20K_0402_1% 2 PQ20 AO4466_SO8 PR51 30K_0402_1% PR54 137K_0402_1% PC39 4.7U_0805_10V6K PC34 2200P_0402_50V7K PC33 4.7U_0805_25V6-K C Typ: 175mA PC32 4.7U_0805_25V6-K PC31 0.1U_0603_25V7K B+ PL3 HCB4532KF-800T90_1812 PR50 13K_0402_1% ENTRIP2 RT8205_B+ D D Deciphered Date 2011/07/13 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Title Compal Electronics, Inc 3VALWP/5VALWP Size Document Number Custom Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: W ednesday, November 24, 2010 Sheet 38 of 47 PJP2 SUYIN_200275GR008G13GZR D 10 2 EC_SMDA EC_SMCA TH PI PR68 100_0402_1% PH1 under CPU botten side : CPU thermal protection at 92 degree C Recovery at 56 degree C GND GND 1 D PR69 100_0402_1% EC_SMB_DA1 VL 1 VMB BATT+ PC50 0.1U_0603_25V7K PR72 21K_0402_1% VCC TMSNS1 GND RHYST1 PR76 9.53K_0402_1% MAINPWON BATT_TEMP OT1 TMSNS2 OT2 RHYST2 PU3 C @ PR77 47K_0402_1% G718TM1U_SOT23-8 1 @ PR74 100K_0402_1% PR75 1K_0402_1% C PR71 10K_0402_1% VL +3VALWP PC52 0.01U_0402_25V7K PR73 6.49K_0402_1% 1 PC51 1000P_0402_50V7K 2 EC_SMB_CK1 PR70 1K_0402_5% PL6 SMB3025500YA_2P PH2 @ PH1 100K_0402_1%_NCP15WF104F03RC 100K_0402_1%_NCP15WF104F03RC PQ28 TP0610K-T1-E3_SOT23-3 +VSBP PC54 0.1U_0603_25V7K 2 VL PC53 0.22U_0603_25V7K PR79 22K_0402_1% 2 PR78 100K_0402_1% B+ PR80 100K_0402_1% 1 D S PQ29 2N7002W-T/R7_SOT323-3 G PC55 1U_0402_6.3V6K SPOK PR81 1K_0402_5% B B A A Compal Secret Data Security Classification Issued Date 2010/07/13 2011/07/13 Deciphered Date Title Compal Electronics, Inc PWR-BATTERY CONN/OTP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Rev 0.1 P5WE0 M/B LA-6901P Schematic Date: Wednesday, November 24, 2010 Sheet 39 of 47 B C FB 0.22U_0402_10V6K FB_1.8VS PR85 10K_0402_1% 2 1M_0402_5% PR83 20K_0402_1% 1 PC120 PR86 PC119 1 LX_1.8VS 200K_0402_5% @ NC NC TP EN_1.8VS 11 PR84 PR82 SUSP# FB=0.6Volt PC118 22U_0805_6.3VAM 1 EN PC115 22U_0805_6.3VAM +1.8VSP SVIN PC117 22U_0805_6.3VAM LX LX_1.8VS PC116 68P_0402_50V8J PVIN JUMP_43X39 LX PVIN 10 4.7_1206_5% 680P_0603_50V7K 2 +5VALW D PL7 2.2UH_MSCDRI-74A-2R2M-E_6.5A_20% PU4 SY8033BDBC_DFN10_3X3 @ PJ14 PG A G5603 RT8209B ℃ Temperature Compensated TPS51117 ℃ -1180ppm/ RT8209M ℃ ℃ 1600ppm/ 4500ppm/ 4800ppm/ 50mV 30mV 50mV 2 PR87 255K_0402_1% 2 FB PGOOD 15 NC 14 UGATE 13 DH_1.5V PHASE 12 LX_1.5V CS 11 VDDP 10 LGATE VFB=0.75V PL9 1.0UH_PCMC104T-1R0MN_20A_20% +1.5VP 0.1U_0603_25V7K PR92 7.68K_0402_1% @ PR93 4.7_1206_5% +5VALW DL_1.5V + PC128 330U_6.3V_M 2 PGND RT8209MGQW _W QFN14_3P5X3P5 PC131 4.7U_0805_10V6K PQ31 AO4726L_SO8 @ PC130 680P_0603_50V7K GND PC129 4.7U_0603_6.3V6K PQ30 AO4466_SO8 PC127 VDD BST_1.5V-1 BOOT VOUT 0_0603_5% 100_0603_5% 2 PR91 TON PR89 1 +5VALW PU5 EN/DEM PC126 @ 1U_0402_16V7K 2 PR90 30K_0402_5% 0_0402_5% BST_1.5V PR88 1 SYSON B+ PC125 2200P_0402_50V7K 200mV PC124 0.1U_0603_25V7K 200mV PC123 4.7U_0805_25V6-K 200mV PC121 4.7U_0805_25V6-K 200mV PL8 HCB2012KF-121T50_0805 Vtrip_max (SPEC) 30mV Vtrip_min (SPEC) Rtrip: 5KΩ~15KΩ Rds(on) = 5.3m ohm (typ) 7m ohm (max) PR94 5.1K_0402_1% PR95 5.1K_0402_1% VFB=0.75V Vo=0.75*(1+10K/10K)=1.5V Fsw=280KHz Cout ESR=17 mohm Rdson(max)=7 mohm Rdson(typ)=5.3 mohm Ipeak=9.45A, Imax=6.615A Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.93A =>1/2Delta I=2.467A Vtrip=Rtrip*10uA=0.0768 Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=11.61A Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=14.54A Iocp=11.61A~14.54A Issued Date Compal Electronics, Inc Compal Secret Data Security Classification 2010/01/25 Deciphered Date 2009/04/28 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C 1.8VSP/1.5VP Rev 0.1 W ednesday, November 24, 2010 D Sheet 40 of 47 A B C D PL10 HCB2012KF-121T50_0805 PR96 255K_0402_1% PR97 0_0402_5% PC208 0.1U_0603_25V7K PC207 0.1U_0603_25V7K PC135 2200P_0402_50V7K 1 PC134 0.1U_0603_25V7K 2 PR98 0_0603_5% PQ32 AO4466_SO8 LGATE DL_1.1VALW PQ33 AO4712_SO8 PGND GND PC139 4.7U_0603_6.3V6K +5VALW RT8209MGQW _W QFN14_3P5X3P5 PC140 4.7U_0805_10V6K Rtrip: 5KΩ~15KΩ PR103 4.7K_0402_1% PC138 330U_6.3V_M 10 VDDP PR102 10.7K_0402_1% LX_1.1VALW @ PR100 4.7_1206_5% 11 PGOOD 12 CS PHASE @ PC141 680P_0603_50V7K FB 13 DH_1.1VALW 0.1U_0603_25V7K UGATE VDD BOOT VOUT 14 15 2 PR101 100_0603_1% TON PL11 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% PC137 1 +5VALW NC PU6 EN/DEM PC136 1U_0402_16V7K @ PR99 30K_0402_5% @ BST_1.1V ALW B+ VFB=0.75V V=0.75*(1+4.7K/10K)=1.1V Fsw=280KHz Cout ESR=17 mohm Rdson(max)=18 mohm Rdson(typ)=15 mohm Ipeak=4.5A, Imax=3.15A Delta I=((19-1.1)*(1.1/19))/(L*Fsw)=1.68A =>1/2Delta I=0.84A Vtrip=Rtrip*10uA=0.107 Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=5.79A Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=6.78A Iocp=5.79A~6.78A SPOK 1 PC133 4.7U_0805_25V6-K PC132 4.7U_0805_25V6-K 1.1VALW _B+ +1.1VALW P + 2 PR104 10K_0402_1% PL12 HCB2012KF-121T50_0805 CS 11 VDDP 10 PR111 8.25K_0402_1% DL_1.05VALW LX_1.05VALW LGATE RT8209MGQW _W QFN14_3P5X3P5 PC150 4.7U_0805_10V6K Rtrip: 5KΩ~15KΩ PR112 4.02K_0402_1% RT8209B Vtrip_min (SPEC) ℃ -1180ppm/ 30mV ℃ TPS51117 RT8209M ℃ ℃ 1600ppm/ 4500ppm/ 4800ppm/ 50mV 30mV 50mV 200mV 200mV 200mV 200mV 2010/01/25 Deciphered Date PC206 0.1U_0603_25V7K 2009/04/28 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: A B C Compal Electronics, Inc Compal Secret Data Security Classification Issued Date Vtrip_max (SPEC) PC205 0.1U_0603_25V7K PC145 2200P_0402_50V7K PC144 0.1U_0603_25V7K 1 PC143 4.7U_0805_25V6-K 2 G5603 + Cout ESR=17 mohm Rdson(max)=7 mohm Rdson(typ)=5.3 mohm Ipeak=8.7A, Imax=6.09A Delta I=((19-1.05)*(1.05/19))/(L*Fsw)=1.61A =>1/2Delta I=0.81A Vtrip=Rtrip*10uA=0.0825 Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=10.63A Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=13.78A Iocp=10.63A~13.78A Temperature Compensated VFB=0.75V V=0.75*(1+4.02K/10K)=1.05V Fsw=280KHz Rds(on) = 5.3m ohm (typ) 7m ohm (max) PR113 10K_0402_1% +1.05VSP PQ35 AO4726L_SO8 PGND PGOOD GND PC149 4.7U_0603_6.3V6K +5VALW 1 PC148 330U_6.3V_M 12 PHASE PR109 4.7_1206_5% 14 13 PC151 680P_0603_50V7K FB PL13 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% 2 DH_1.05VALW 0.1U_0603_25V7K UGATE VDD 5 VOUT BST_1.05V ALW PC147 BOOT B+ PQ34 AO4466_SO8 PR110 100_0603_1% +5VALW TON PR107 0_0603_5% 2 NC PU7 EN/DEM PC146 1U_0402_16V7K PR108 30K_0402_5% @ 1 SUSP# PR106 200K_0402_5% 15 PR105 255K_0402_1% PC142 4.7U_0805_25V6-K 1.05VALW _B+ 1.1VALWP/1.05VSP Rev 0.1 W ednesday, November 24, 2010 D Sheet 41 of 47 14 PGOOD 10 @ PR182 4.7_1206_5% +5VALW DL_1.5V-2 +1.5VSP + @ PC202 330U_6.3V_M RT8209MGQW_WQFN14_3P5X3P5 @ PQ39 AO4726L_SO8 @ PC200 4.7U_0805_10V6K @ PC195 680P_0603_50V7K LGATE 11 VDDP LX_1.5V-2 @ PR185 7.68K_0402_1% 12 15 BOOT CS VFB=0.75V FB PHASE 1 VDD 0.1U_0603_25V7K DH_1.5V-2 100_0603_5% VOUT @ PL21 1.0UH_PCMC104T-1R0MN_20A_20% 13 @ PQ46 AO4466_SO8 @ PC199 BST_1.5V-2 @ PR178 @ PC196 4.7U_0603_6.3V6K D 0_0603_5% UGATE PGND +5VALW TON NC PU11 @ EN/DEM @ PC203 1U_0402_16V7K 2 @ PR183 30K_0402_5% @ @ PR181 BST_1.5V-2 0_0402_5% @ B+ @ PR186 GND SYSON D @ @ PL20 HCB2012KF-121T50_0805 PC197 2200P_0402_50V7K @ @ PR180 255K_0402_1% PC201 0.1U_0603_25V7K 2 PC204 4.7U_0805_25V6-K PC198 4.7U_0805_25V6-K Rtrip: 5KΩ~15KΩ @ PR184 5.1K_0402_1% VFB=0.75V Vo=0.75*(1+10K/10K)=1.5V Fsw=280KHz C @ PR179 5.1K_0402_1% RT8209B TPS51117 RT8209M C G5603 Temperature Compensated -1180ppm/ ℃ 1600ppm/ ℃ 4500ppm/ ℃ 4800ppm/ Vtrip_min (SPEC) 30mV 50mV 30mV 50mV Vtrip_max (SPEC) 200mV 200mV 200mV 200mV ℃ Cout ESR=17 mohm Rdson(max)=7 mohm Rdson(typ)=5.3 mohm Ipeak=9.45A, Imax=6.615A Delta I=((19-1.5)*(1.5/19))/(L*Fsw)=4.93A =>1/2Delta I=2.467A Vtrip=Rtrip*10uA=0.0768 Iocpmin=Vtrip/(Rds(on)(max)*1.2)+Delta I/2=11.61A Iocpmax=Vtrip/(Rds(on)(typ)*1.2)+Delta I/2=14.54A Iocp=11.61A~14.54A PJ15 JUMP_43X39 2 1 +1.5V PU8 VIN NC GND NC VREF VCNTL PC153 1U_0603_10V6K PR114 1K_0402_1% B +3VALW 1 VOUT PC152 4.7U_0805_6.3V6K B NC TP +0.75VSP S PQ36 2N7002W-T/R7_SOT323-3 PC154 1U_0402_16V7K 1 PR116 1K_0402_1% PC155 10U_0603_6.3V6M PC156 1U_0402_16V7K D G PR115 300K_0402_5% SUSP APL5336KAI-TRL_SOP8P8 For shortage changed A A Compal Secret Data Security Classification 2009/10/02 Issued Date 2010/10/02 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Compal Electronics, Inc 0.75VSP Document Number Rev 0.3 Wednesday, November 24, 2010 Sheet 42 of 47 VGA@ PL14 HCB2012KF-121T50_0805 B+ B+_CORE VGA_PWRGD TRIP DRVH DH_VCORE EN SW SW_VCORE VFB V5IN RF DRVL VGA@ PC162 1U_0603_6.3V6M 1 @ PR122 4.7_1206_5% 2 VGA@ PC163 390U_2.5V_M + VGA@ PR124 0_0402_5% @ PC164 680P_0603_50V7K VGA@ PR125 10_0402_5% GCORE_SEN GCORE_SEN C VGA@ PQ38 TPCA8057-H_PPAK56-8-5 VGA@ PR126 2.87K_0402_1% Rds=2.6m/3.2mOHM VGA@ PC165 1U_0402_16V7K ESR=10mohm DL_VCORE 11 Switch Freq (RF pin setting) 47K =>450KHz 100K =>390KHz 200K =>350KHz 470K =>290KHz +VGA_COREP TP VFB=0.7V C VGA@ PL15 0.36UH_PCMC104T-R36MN1R17_30A_20% +5VALW TPS51218DSCR_SON10_3X3 1.5_VDDC_PWREN VGA@ PQ37 TPCA8065-H_PPAK56-8-5 VGA@ PR120 200K_0402_1% 10 2 @ PR121 10K_0402_5% VBST VGA@ PR118 VGA@ PC161 0_0603_5% 0.1U_0603_25V7K BST_VCORE 2 +3VS VGA@ PU9 PGOOD VGA@ PR119 44.2K_0402_1% VGA@ PR123 20K_0402_1% D VGA@ VGA@ @ PR117 10K_0402_5% VGA@ PC160 10U_0805_25V6K VGA@ PC159 10U_0805_25V6K D PC158 0.1U_0603_25V7K PC157 2200P_0402_25V7K +3VS +3VSG VGA@ PC167 4700P_0402_25V7K @ PR132 10K_0402_5% S G DMN66D0LDW-7_SOT363-6 VGA@ PQ40A G 2 D VGA@ PR133 10K_0402_5% VGA@ PR134 10K_0402_5% VGA@ PR130 40.2K_0402_1% +3VSG D VGA@ PR129 10K_0402_5% VGA@ PR128 9.31K_0402_1% VGA@ PC166 2200P_0402_25V7K Ipeak=18.2A Imax=12.74A, 1.2*Ipeak=21.84A Delta I= ((19-0.9)*(0.9/19))/(L*Fsw)=6.8A Iocpmax=(66.5K*11uA)/(8*1.2*0.0026) +3.4=32.71A Iocpmin=(66.5K*9uA)/(8*1.2*0.0032)+3.4=22.88A Iocp=22.88~32.71A VGA@ PR127 15.4K_0402_1% VGA@ PR131 30.1K_0402_1% VGA_CORE Vtrip= 0.7V Vo=0.7*(1+Rtop/Rdown) Fsw=350KHz B VGA@ PC168 4700P_0402_25V7K @ PR135 10K_0402_5% +3VSG GPIO 15 GPIO 20 GPU_VID0 GPU_VID1 Core Voltage Level Seymour G VGA@ PQ41B DMN66D0LDW-7_SOT363-6 VGA@ PR140 10K_0402_5% @ PR139 10K_0402_5% +3VSG GPU_VID0 D 11 2 S VGA@ PQ40B DMN66D0LDW-7_SOT363-6 B VGA@ PR141 10K_0402_5% @ PR136 10K_0402_5% 0.9V D AP 1.00V 1.05V 0 1.10V GPU_VID1 VGA@ PR138 10K_0402_5% S VGA@ PR137 10K_0402_5% 1 G VGA@PQ41A DMN66D0LDW-7_SOT363-6 1 1 S A A Compal Secret Data Security Classification Issued Date 2010/07/13 2011/07/13 Deciphered Date Title Compal Electronics, Inc +VGA_COREP THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: Rev 0.1 P5WE6/S6/H6 Wednesday, November 24, 2010 Sheet 43 of 47 B C D E PL16 HCB2012KF-121T50_0805 CPU_B+ ENABLE LGATE0 ISL6265CHRTZ-T_TQFN48_6X6 RBIAS PVCC OCSET LGATE1 VDIFF0 PGND1 PHASE0 32 +5VALW 28 APU_VDD0_RUN_FB_L PR170 10_0402_1% PC57 10U_1206_25V6M PC175 220U_25V_M PC173 0.1U_0603_25V7K 2 PC212 0.1U_0603_25V7K PC211 0.1U_0603_25V7K PC210 0.1U_0603_25V7K PC209 0.1U_0603_25V7K PC214 0.1U_0603_25V7K PC185 0.1U_0603_25V7K PC184 4.7U_0805_25V6-K PC183 4.7U_0805_25V6-K PQ45 TPCA8057-H 1N PPAK56-8 PR162 12.7K_0402_1% PC188 680P_0603_50V7K PC189 0.1U_0603_16V7K PC190 1U_0603_16V6K LGATE0 27 PR166 4.53K_0402_1% 26 TP 25 49 ISN1 24 ISP1 23 VW1 22 COMP1 21 FB1 20 VDIFF1 19 VSEN1 18 RTN1 17 16 +APU_CORE ISN0 VSEN0 0_0402_5% PR171 RTN0 +1.5V DIFF_0 PR169 0_0402_5% APU_VDD0_RUN_FB_H 14 PR168 0_0402_5% 10_0402_1% ISP0 +APU_CORE BOOT1 30 29 3 ISP0 ISN0 VSEN1 PR167 13 VSEN1 RTN0 UGATE1 VW0 VSEN0 COMP0 ISP0 12 PHASE1 15 11 FB0 ISN0 10 PR161 4.7_1206_5% LGATE0 31 PGND0 UGATE0 33 PQ44, PQ45 need to link SVC 34 PC187 0.22U_0603_10V7K 38 39 40 41 37 UGATE_NB PHASE_NB LGATE_NB PGND_NB 43 44 45 42 RTN_NB VSEN_NB FSET_NB 46 FB_NB PHASE0 BOOT0 UGATE0 SVD 35 ISN0 PWROK 36 PL19 PR163 0_0402_5% PR165 95.3K_0402_1% BOOT0 DCR = 1.1m ohm +-7% 0.36UH_PCMC104T-R36MN1R17_30A_20% ISP0 BOOT_NB PGOOD BOOT_NB PR158 2.2_0603_1% BOOT0 PQ44 TPCA8065-H_PPAK56-8-5 ESR = 15 m ohm PC179 220U_6.3V_M VR_ON PR164 21.5K_0402_1% 1 PR160 0_0402_5%2 PHASE0 ISL6265_PWROK APU_SVD APU_SVC OFS/VFIXEN OCSET_NB COMP_NB VCC 47 VIN 48 PU10 H_PWRGD_L + CPU_B+ PR190 0_0603_5% UGATE0-1 UGATE0 @ PR156 105K_0402_1% @ PR159 100K_0402_5% PR157 100K_0402_5% Rds(on) max =18 m ohm typ = 15 m ohm UGATE_NB PC180 680P_0603_50V7K PC182 4.7U_0805_25V6-K 2 1 1 LGATE_NB @ PR153 105K_0402_1% VGATE FCH_PWRGD PR146 4.7_1206_5% PC213 0.1U_0603_25V7K 1 PR187 10_0402_5%PHASE_NB @ PR155 10K_0402_1% +APU_CORE_NB PQ43 AO4712_SO8 PHASE_NB PR154 105K_0402_1% PC174 2200P_0402_50V7K PC186 2200P_0402_50V7K 1 PR152 0_0402_5% PL18 2.2UH_FDVE0630-H-2R2M=P3_8.3A_20% PC178 0.22U_0603_10V7K APU_VDDNB_RUN_FB_H + B+ APU_VDD0_RUN_FB_L PR151 23.7K_0402_1% 2 PC181 0.1U_0603_25V7K LGATE_NB PR148 2_0603_5% +3VS PQ42 AO4466_SO8 +5VS PHASE_NB PR145 2.2_0603_1% BOOT_NB PR149 0_0402_5% PR150 0_0402_5% 1 +3VS UGATE_NB1 PC170 1000P_0402_50V7K PR147 10_0402_5% +APU_CORE_NB PR189 0_0603_5% PR188 220_0402_1% 1 UGATE_NB PR144 22K_0402_1% 2 PC177 0.1U_0603_16V7K CPU_B+ PC176 1000P_0402_50V7K 1 +5VALW PR142 44.2K_0402_1% PR143 2_0603_5% PC171 4.7U_0805_25V6-K 1 PC172 4.7U_0805_25V6-K 2 PC169 47P_0402_50V8J PC58 10U_1206_25V6M A 1K_0402_5% PR172 VW0 PR173 PC191 255_0402_1% 2200P_0402_25V7K 2 COMP0 PC192 220P_0402_50V8J PR174 1K_0402_5% PR175 PC194 2 PC193 1000P_0402_50V7K PR176 6.81K_0402_1% 54.9K_0402_1% 1200P_0402_50V7K Compal Secret Data Security Classification PR177 36.5K_0402_1% 2009/10/02 Issued Date 2010/10/02 Deciphered Date Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC @ Date: A B C D Compal Electronics, Inc CPU_CORE Document Number Rev 0.3 Wednesday, November 24, 2010 Sheet E 44 of 47 Version change list (P.I.R List) Item D Fixed Issue Page of for PWR Reason for change Rev PG# Modify List Date Change PR115 from SD028000080 to SD028300380(S RES 1/16W 300K +-5% 0402) Add PC156 SE076104K80(S CER CAP 1U 16V K X7R 0402) Phase 2010/09/24 DVT 0.75VSP EN RC value HW adjust timing 0.1 42 1.8VSP EN RC value HW adjust timing 0.1 40 Change PR84 from SD028000080 to SD028200380(S RES 1/16W 200K +-5% 0402) Add PC120 SE095224K00(S CER CAP 0.22U 10V K X5R 0402) 2010/09/24 DVT 1.05VSP EN RC value HW adjust timing 0.1 41 Change PR106 from SD028000080 to SD028200380(S RES 1/16W 200K +-5% 0402) Add PC146 SE076104K80(S CER CAP 1U 16V K X7R 0402) 2010/09/24 DVT HW adjust timing 0.1 43 Change PR123 from SD034100280 to SD034200280(S RES 1/16W 20K +-1% 0402) 2010/09/24 DVT 42 Change PU11, PL21, PQ39, PQ46, PR178, PR179, PR180, PR181, PR184, PR185, PR186, PC196, PC197, PC198, PC199, PC200, PC201, PC202, PC204 BOM structure to VGA@ del PL20 SM01000C000(S SUPPRE_ TAI-TECH HCB2012KF-121T50 0805) 2010/10/05 DVT D VGA_COREP EN RC value change BOM structure 1.5VSP change BOM structure to VGA@ for cost down of UMA 0.1 C C Adjust APU_CORE_NB OCP to 15A 0.1 44 Add input choke in charger circuit Add input choke for EMI ISN test in charger circuit 0.1 37 Add snubber Add snubber in APU_COREP and APU_CORE_NB circuit 0.1 44 Add PR146, PR161 SD001470B80(S RES 1/4W 4.7 +-5% 1206) Add PC180, PC188 SE025681K80(S CER CAP 680P 50V K X7R 0603) Add PR188 SD034220080(S RES 1/16W 220 +-1% 0402) Add snubber and input Cup 0.1 41 10 Add input Cup 0.1 Adjust APU_CORE_NB OCP Add snubber and input Cup in 1.05VSP circuit Add input Cup in 1.1VALWP circuit for EMI test 2010/10/07 DVT 2010/10/18 DVT 2010/10/18 DVT Add PR161 SD001470B80(S RES 1/4W 4.7 +-5% 1206) Add PC188 SE025681K80(S CER CAP 680P 50V K X7R 0603) Add PC205, PC206 SE042104K80(S CER CAP 1U 25V K X7R 0603) 2010/10/18 DVT 41 Add PC207, PC208 SE042104K80(S CER CAP 1U 25V K X7R 0603) 2010/10/18 DVT Add PC209, PC210, PC211, PC212 SE042104K80(S CER CAP 1U 25V K X7R 0603) Add PC57, PC58 SE142106M80(S CER CAP 10U 25V M X5R 1206 H1.7) Add PR189, PR190 SD013000080(S RES 1/10W +-5% 0603) Change PR151 from SD034110280 to SD034237280(S RES 1/16W 23.7K +-1% 0402) Change PL17 from SM010018710 to SH00000IY00(S COIL 1.2UH +-30% 1231AS-H-1R2N=P3 2.9A) B B 11 Add input Cup Add input Cup and H/S gate resistance in CPU_COREP circuit for EMI ISN test 0.1 44 2010/10/19 DVT 12 Adjust VGA_COREP VID value Adjust VGA_COREP VID value 0.1 43 Change PR128 from SD034100280 to SD034931180(S RES 1/16W 9.31K +-1% 0402) Change PR127 from SD034200280 to SD034154280(S RES 1/16W 15.4K +-1% 0402) Change PR131 from SD000009K00 to SD034301280(S RES 1/16W 30.1K +-1% 0402) 2010/10/21 DVT 13 change BOM structure 1.5VSP change BOM structure to @ for cost down 0.1 42 Change PU11, PL21, PQ39, PQ46, PR178, PR179, PR180, PR181, PR184, PR185, PR186, PC196, PC197, PC198, PC199, PC200, PC201, PC202, PC204 BOM structure to @ del PL20 SM01000C000(S SUPPRE_ TAI-TECH HCB2012KF-121T50 0805) 2010/10/21 DVT 14 change main source change main source for reduce source 0.1 42 2010/10/26 DVT Adjust VGA_COREP VID timing to avoid OVP 0.1 43 2010/11/01 DVT 2010/11/01 DVT 15 Adjust VGA_COREP VID timing 16 Delete precharge circuit Change PQ36 from SB000009610 to SB000006800(S TR 2N7002W T/R7 1N SOT-323) Change PR130 from SD028100280 to SD034402280(S RES 1/16W 40.2K +-1% 0402) A Delete precharge circuit to avoid adapter UVP 0.1 36 del PR8, PR11, PR12 SD001100180(S RES 1/4W 1K +-5% 1206) del PD3 SC100001Y80(S DIO LL4148 LL-34 PANJIT) del PR9, PR10, PR13 SD028100380(S RES 1/16W 100K +-5% 0402) change PR7 SD001100180 to SD011000080(S RES 1/4W +-5% 1206) Compal Electronics, Inc Compal Secret Data Security Classification 2010/04/12 Issued Date A Deciphered Date 2010/10/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PIR (PWR) Rev 0.1 PEW96 LA-6552P Monday, November 15, 2010 Sheet 45 of 47 Version change list (P.I.R List) Item D Fixed Issue Page of for PWR Reason for change Rev PG# Delete precharge circuit Delete precharge 連連 circuit Delete precharge 連連 circuit Delete precharge 連連 circuit to avoid adapter UVP 0.1 37 Delete precharge 連連 circuit Delete precharge 連連 circuit to avoid adapter UVP 0.1 37 Delete precharge 連連 circuit Delete precharge 連連 circuit to avoid adapter UVP 0.1 37 0.1 44 Delete precharge circuit to avoid adapter UVP Delete precharge 0.1 連連 circuit to avoid adapter UVP 36 0.1 37 Modify List Date del PQ2 SB906100210(S TR TP0610K-T1-E3 1P SOT23) del PQ3, PQ4 SB301150200(S TR PDTC115EU NPN SOT323) del PD4 SCS00001200(S SCH DIO BAS40CW SOT-323) change PQ7 SB00000DL00 to SB00000I600(S TR SI4459ADY-T1-GE3 1P SO8) del PR21 SD034100380(S RES 1/16W 100K +-1% 0402) del PC17 SE075222K80(S CER CAP 2200P 25V K X7R 0402) del PQ12 SB000006800(S TR 2N7002W T/R7 1N SOT-323) Phase 2010/11/01 DVT 2010/11/01 D DVT 2010/11/01 DVT Add PR357 SD034200380(S RES 1/16W 200K +-1% 0402) add PC253 SE042104K80(S CER CAP 1U 25V K X7R 0603) add PQ61 SB000006800(S TR 2N7002W T/R7 1N SOT-323) 2010/11/01 DVT Add PD9, PD12 SC100001K00(S DIO 1SS355 SOD323 T/R-5K) 2010/11/01 DVT C C Add PC213, PC214 SE042104K80(S CER CAP 1U 25V K X7R 0603) Add input Cup Add input Cup in CPU_COREP circuit for EMI ISN test PVT 2010/11/12 10 B B 11 12 13 14 15 A A 16 2010/04/12 Issued Date Compal Electronics, Inc Compal Secret Data Security Classification Deciphered Date 2010/10/12 Title THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL Size Document Number AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC Date: PIR (PWR) Rev 0.1 PEW96 LA-6552P Monday, November 15, 2010 Sheet 46 of 47 PHASE PAGE 0.1 P08 0.2 0.2 D 0.2 P-P Modification list PURPOSE First release Base on PEW96, change platform (NB,CPU >APU,SB820 >FCH) C220, C336, C347, C357, C359, C360, C387, C388, C389, C390, C391, C392, C393, C421, Follow Standard Part 0805 >0603 C427, C428, C1461 change 0603 size C721 C669, C1005, C705, C708, C713, C715, C736, C794, C797, C932, C934, C983 Follow Standard Part 0805 >0603 change 0603 size C215, C216, C218, C224, C226, C227, C229, C230, C231, C660, C671, C821, C823, D P C1210, C1517, C1522, C1526, C1529, C1532, C1512, C1523, C1443, C1445, C1446, C1447, Follow Standard Part 0805 >0603 C1448, C1452, C1453, C1454 change 0603 size C 0.2 P35 R1122 change as 200k ohm, C1463 change as 0.1UF Adjust sequence 0.2 P5 Add R109, R155 Pull up 4.7k ohm for CRT EDIE 0.2 P16 Unpop R632, C744, C69, C746; Pop R633 +VDDIO_18_FC Tie to GND for Nun-share ROM 0.2 P16 Add R635; Unpop R634 AMD suggestion for +VDDIO_AZ 0.2 P24 Add R170, R171 For DISO BOM option 0.2 P13 Add U33, C1199, R830, R838, R839 For VGA_PWRGD 0.2 P13 Remove C52, R557 For A_RST# 0.2 P27 EC_MUTE# change as 12 PIN form 46 PIN in Codec For External Mute Fail issue 0.2 P16 C113, C77, C743, C96 change 0603 size and add C121, C105, C108, C109 22uF cap change two 10uF cap 0603 size 0.2 P19 C14 change 0603 size and add C52 22uF cap change two 10uF cap 0603 size 0.2 P13 C66, C67 change 27pF Follow suggestion by TXC result 0.2 P26 C1485, C1486 change 33pF Follow suggestion by TXC result 0.2 P33 C711 Change as SF000003I00 Material shortage 0.2 P9 Add C643, C675, C676, C678 For DDR3 moat issue C 0.2 P26 Remove C939 ; Reserve C941, D48, D49, D51, L109 For LAN 0.2 P7 Add C604, C684 For CRT Moniter issue 0.3 P C212, C623 change 0603 size ; add C628, C685 Follow Standard Part 0805 >0603 0.3 P27 R786 change as 15k ohm Dos Beep issue 0.3 P19 change R21, R22 as DISO@ Device Menage Audio issue 1.0 P27 Add R797, R800 Mic noise issue 1.0 P26,10 1.0 P32 Reverse C939, C942, R456, R419, R426 for EMI ISN solution Add C753, C785 for EMI request B B A A Compal Secret Data Security Classification 2010/08/20 Issued Date Change footprint 20100812 Deciphered Date 2011/08/20 THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC : For cost down purpose to change parts Title Compal Electronics, Inc HW-PIR Size B Date: Document Number Rev 1.0 LA-7092P P5WE6/H6/S6 Tuesday, November 16, 2010 Sheet 47 of 47 ... C1480 LAN_X11 Y6 close to pin34 LAN_ACTIVITY LAN_LINK# LED2_CKR# TRXN0 TRXP0 TRXN1 TRXP1 TRXN2 TRXP2 TRXN3 TRXP3 12 11 15 14 18 17 21 20 LAN_MDI0LAN_MDI0+ LAN_MDI1LAN_MDI1+ LAN_MDI2LAN_MDI2+ LAN_MDI3LAN_MDI3+... LAN_MDI2LAN_MDI2+ LAN_MDI3LAN_MDI3+ RBIAS TEST_RST TESTMODE VDD33 LX XTLO XTLI Close LAN chip LAN_CLKREQ# R1139 8152@ 0_0402_5% LAN_MDI0LAN_MDI1+ LAN_MDI1LAN_MDI2+ LAN_MDI2LAN_MDI3+ LAN_MDI3- 1@ C1466... 25MHZ_20PF_7A25000012 C1486 33P_0402_50V8K close to Lan pin9 close to Lan pin22 close to Lan pin16 close to Lan pin37 close to Lan pin24 +3V_LAN +3VALW Change Y6 P/N as SJ100003300 R1157 1A 0_0603_5%