(BQ) Part 1 of the document Digital electronics has contents: Number systems, binary codes, digital arithmetic, logic gates and related devices, logic families, boolean algebra and simplification techniques, arithmetic circuits, multiplexers and demultiplexers.
Digital Electronics Digital Electronics: Principles, Devices and Applications Anil K Maini © 2007 John Wiley & Sons, Ltd ISBN: 978-0-470-03214-5 Digital Electronics Principles, Devices and Applications Anil K Maini Defence Research and Development Organization (DRDO), India Copyright © 2007 John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England Telephone +44 1243 779777 Email (for orders and customer service enquiries): cs-books@wiley.co.uk Visit our Home Page on www.wiley.com All Rights Reserved No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except under the terms of the Copyright, Designs and Patents Act 1988 or under the terms of a licence issued by the Copyright Licensing Agency Ltd, 90 Tottenham Court Road, London W1T 4LP, UK, without the permission in writing of the Publisher Requests to the Publisher should be addressed to the Permissions Department, John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex PO19 8SQ, England, or emailed to permreq@wiley.co.uk, or faxed to (+44) 1243 770620 Designations used by companies to distinguish their products are often claimed as trademarks All brand names and product names used in this book are trade names, service marks, trademarks or registered trademarks of their respective owners The Publisher is not associated with any product or vendor mentioned in this book This publication is designed to provide accurate and authoritative information in regard to the subject matter covered It is sold on the understanding that the Publisher is not engaged in rendering professional services If professional advice or other expert assistance is required, the services of a competent professional should be sought Other Wiley Editorial Offices John Wiley & Sons Inc., 111 River Street, Hoboken, NJ 07030, USA Jossey-Bass, 989 Market Street, San Francisco, CA 94103-1741, USA Wiley-VCH Verlag GmbH, Boschstr 12, D-69469 Weinheim, Germany John Wiley & Sons Australia Ltd, 42 McDougall Street, Milton, Queensland 4064, Australia John Wiley & Sons (Asia) Pte Ltd, Clementi Loop #02-01, Jin Xing Distripark, Singapore 129809 John Wiley & Sons Canada Ltd, 6045 Freemont Blvd, Mississauga, ONT, Canada L5R 4J3 Wiley also publishes its books in a variety of electronic formats Some content that appears in print may not be available in electronic books Anniversary Logo Design: Richard J Pacifico Library of Congress Cataloging in Publication Data Maini, Anil Kumar Digital electronics : principles, devices, and applications / Anil Kumar Maini p cm Includes bibliographical references and index ISBN 978-0-470-03214-5 (Cloth) Digital electronics I Title TK7868.D5M275 2007 621.381—dc22 2007020666 British Library Cataloguing in Publication Data A catalogue record for this book is available from the British Library ISBN 978-0-470-03214-5 (HB) Typeset in 9/11pt Times by Integra Software Services Pvt Ltd, Pondicherry, India Printed and bound in Great Britain by Antony Rowe Ltd, Chippenham, Wiltshire This book is printed on acid-free paper responsibly manufactured from sustainable forestry in which at least two trees are planted for each one used for paper production In the loving memory of my father, Shri Sukhdev Raj Maini, who has been a source of inspiration, courage and strength to me to face all challenges in life, and above all instilled in me the value of helping people to make this world a better place Anil K Maini Contents Preface xxi 1 2 3 4 4 5 5 6 6 7 9 10 10 11 12 13 13 Number Systems 1.1 Analogue Versus Digital 1.2 Introduction to Number Systems 1.3 Decimal Number System 1.4 Binary Number System 1.4.1 Advantages 1.5 Octal Number System 1.6 Hexadecimal Number System 1.7 Number Systems – Some Common Terms 1.7.1 Binary Number System 1.7.2 Decimal Number System 1.7.3 Octal Number System 1.7.4 Hexadecimal Number System 1.8 Number Representation in Binary 1.8.1 Sign-Bit Magnitude 1.8.2 1’s Complement 1.8.3 2’s Complement 1.9 Finding the Decimal Equivalent 1.9.1 Binary-to-Decimal Conversion 1.9.2 Octal-to-Decimal Conversion 1.9.3 Hexadecimal-to-Decimal Conversion 1.10 Decimal-to-Binary Conversion 1.11 Decimal-to-Octal Conversion 1.12 Decimal-to-Hexadecimal Conversion 1.13 Binary–Octal and Octal–Binary Conversions 1.14 Hex–Binary and Binary–Hex Conversions 1.15 Hex–Octal and Octal–Hex Conversions 1.16 The Four Axioms 1.17 Floating-Point Numbers 1.17.1 Range of Numbers and Precision 1.17.2 Floating-Point Number Formats Contents viii Review Questions Problems Further Reading 17 17 18 Binary Codes 2.1 Binary Coded Decimal 2.1.1 BCD-to-Binary Conversion 2.1.2 Binary-to-BCD Conversion 2.1.3 Higher-Density BCD Encoding 2.1.4 Packed and Unpacked BCD Numbers 2.2 Excess-3 Code 2.3 Gray Code 2.3.1 Binary–Gray Code Conversion 2.3.2 Gray Code–Binary Conversion 2.3.3 n-ary Gray Code 2.3.4 Applications 2.4 Alphanumeric Codes 2.4.1 ASCII code 2.4.2 EBCDIC code 2.4.3 Unicode 2.5 Seven-segment Display Code 2.6 Error Detection and Correction Codes 2.6.1 Parity Code 2.6.2 Repetition Code 2.6.3 Cyclic Redundancy Check Code 2.6.4 Hamming Code Review Questions Problems Further Reading 19 19 20 20 21 21 21 23 24 25 25 25 27 28 31 37 38 40 41 41 41 42 44 45 45 Digital Arithmetic 3.1 Basic Rules of Binary Addition and Subtraction 3.2 Addition of Larger-Bit Binary Numbers 3.2.1 Addition Using the 2’s Complement Method 3.3 Subtraction of Larger-Bit Binary Numbers 3.3.1 Subtraction Using 2’s Complement Arithmetic 3.4 BCD Addition and Subtraction in Excess-3 Code 3.4.1 Addition 3.4.2 Subtraction 3.5 Binary Multiplication 3.5.1 Repeated Left-Shift and Add Algorithm 3.5.2 Repeated Add and Right-Shift Algorithm 3.6 Binary Division 3.6.1 Repeated Right-Shift and Subtract Algorithm 3.6.2 Repeated Subtract and Left-Shift Algorithm 3.7 Floating-Point Arithmetic 3.7.1 Addition and Subtraction 3.7.2 Multiplication and Division 47 47 49 49 52 53 57 57 57 58 59 59 60 61 62 64 65 65 Contents ix Review Questions Problems Further Reading Logic 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.12 4.13 4.14 Gates and Related Devices Positive and Negative Logic Truth Table Logic Gates 4.3.1 OR Gate 4.3.2 AND Gate 4.3.3 NOT Gate 4.3.4 EXCLUSIVE-OR Gate 4.3.5 NAND Gate 4.3.6 NOR Gate 4.3.7 EXCLUSIVE-NOR Gate 4.3.8 INHIBIT Gate Universal Gates Gates with Open Collector/Drain Outputs Tristate Logic Gates AND-OR-INVERT Gates Schmitt Gates Special Output Gates Fan-Out of Logic Gates Buffers and Transceivers IEEE/ANSI Standard Symbols 4.12.1 IEEE/ANSI Standards – Salient Features 4.12.2 ANSI Symbols for Logic Gate ICs Some Common Applications of Logic Gates 4.13.1 OR Gate 4.13.2 AND Gate 4.13.3 EX-OR/EX-NOR Gate 4.13.4 Inverter Application-Relevant Information Review Questions Problems Further Reading Logic Families 5.1 Logic Families – Significance and Types 5.1.1 Significance 5.1.2 Types of Logic Family 5.2 Characteristic Parameters 5.3 Transistor Transistor Logic (TTL) 5.3.1 Standard TTL 5.3.2 Other Logic Gates in Standard TTL 5.3.3 Low-Power TTL 5.3.4 High-Power TTL (74H/54H) 5.3.5 Schottky TTL (74S/54S) 67 68 68 69 69 70 71 71 73 75 76 79 79 80 82 85 85 87 87 88 91 95 98 100 100 101 102 103 104 104 105 107 109 110 114 115 115 115 116 118 124 125 127 133 134 135 Contents x 5.4 5.5 5.6 5.7 5.8 5.9 5.10 5.11 5.12 5.13 5.14 5.3.6 Low-Power Schottky TTL (74LS/54LS) 5.3.7 Advanced Low-Power Schottky TTL (74ALS/54ALS) 5.3.8 Advanced Schottky TTL (74AS/54AS) 5.3.9 Fairchild Advanced Schottky TTL (74F/54F) 5.3.10 Floating and Unused Inputs 5.3.11 Current Transients and Power Supply Decoupling Emitter Coupled Logic (ECL) 5.4.1 Different Subfamilies 5.4.2 Logic Gate Implementation in ECL 5.4.3 Salient Features of ECL CMOS Logic Family 5.5.1 Circuit Implementation of Logic Functions 5.5.2 CMOS Subfamilies BiCMOS Logic 5.6.1 BiCMOS Inverter 5.6.2 BiCMOS NAND NMOS and PMOS Logic 5.7.1 PMOS Logic 5.7.2 NMOS Logic Integrated Injection Logic (I2 L) Family Comparison of Different Logic Families Guidelines to Using TTL Devices Guidelines to Handling and Using CMOS Devices Interfacing with Different Logic Families 5.12.1 CMOS-to-TTL Interface 5.12.2 TTL-to-CMOS Interface 5.12.3 TTL-to-ECL and ECL-to-TTL Interfaces 5.12.4 CMOS-to-ECL and ECL-to-CMOS Interfaces Classification of Digital ICs Application-Relevant Information Review Questions Problems Further Reading Boolean Algebra and Simplification Techniques 6.1 Introduction to Boolean Algebra 6.1.1 Variables, Literals and Terms in Boolean Expressions 6.1.2 Equivalent and Complement of Boolean Expressions 6.1.3 Dual of a Boolean Expression 6.2 Postulates of Boolean Algebra 6.3 Theorems of Boolean Algebra 6.3.1 Theorem (Operations with ‘0’ and ‘1’) 6.3.2 Theorem (Operations with ‘0’ and ‘1’) 6.3.3 Theorem (Idempotent or Identity Laws) 6.3.4 Theorem (Complementation Law) 6.3.5 Theorem (Commutative Laws) 6.3.6 Theorem (Associative Laws) 6.3.7 Theorem (Distributive Laws) 136 137 139 140 141 142 147 147 148 150 151 151 165 170 171 171 172 173 174 174 176 176 179 179 179 180 180 183 183 184 185 185 187 189 189 190 190 191 192 192 192 193 193 193 194 194 195 Contents 6.4 6.5 6.6 xi 6.3.8 Theorem 6.3.9 Theorem 6.3.10 Theorem 10 (Absorption Law or Redundancy Law) 6.3.11 Theorem 11 6.3.12 Theorem 12 (Consensus Theorem) 6.3.13 Theorem 13 (DeMorgan’s Theorem) 6.3.14 Theorem 14 (Transposition Theorem) 6.3.15 Theorem 15 6.3.16 Theorem 16 6.3.17 Theorem 17 (Involution Law) Simplification Techniques 6.4.1 Sum-of-Products Boolean Expressions 6.4.2 Product-of-Sums Expressions 6.4.3 Expanded Forms of Boolean Expressions 6.4.4 Canonical Form of Boolean Expressions 6.4.5 and Nomenclature Quine–McCluskey Tabular Method 6.5.1 Tabular Method for Multi-Output Functions Karnaugh Map Method 6.6.1 Construction of a Karnaugh Map 6.6.2 Karnaugh Map for Boolean Expressions with a Larger Number of Variables 6.6.3 Karnaugh Maps for Multi-Output Functions Review Questions Problems Further Reading Arithmetic Circuits 7.1 Combinational Circuits 7.2 Implementing Combinational Logic 7.3 Arithmetic Circuits – Basic Building Blocks 7.3.1 Half-Adder 7.3.2 Full Adder 7.3.3 Half-Subtractor 7.3.4 Full Subtractor 7.3.5 Controlled Inverter 7.4 Adder–Subtractor 7.5 BCD Adder 7.6 Carry Propagation–Look-Ahead Carry Generator 7.7 Arithmetic Logic Unit (ALU) 7.8 Multipliers 7.9 Magnitude Comparator 7.9.1 Cascading Magnitude Comparators 7.10 Application-Relevant Information Review Questions Problems Further Reading 196 197 197 197 198 199 200 201 201 202 204 204 205 206 206 207 208 212 216 216 222 225 230 230 231 233 233 235 236 236 237 240 242 244 245 246 254 260 260 261 263 266 266 267 268 Digital Electronics 284 Example 8.4 We have an eight-line to three-line priority encoder circuit with D0 D1 D2 D3 D4 D5 D6 and D7 as the data input lines the output bits are A (MSB), B and C (LSB) Higher-order data bits have been assigned a higher priority, with D7 having the highest priority If the data inputs and outputs are active when LOW, determine the logic status of output bits for the following logic status of data inputs: (a) All inputs are in logic ‘0’ state (b) D1 to D are in logic ‘1’ state and D5 to D7 are in logic ‘0’ state (c) D7 is in logic ‘0’ state The logic status of the other inputs is not known Solution (a) Since all inputs are in logic ‘0’ state, it implies that all inputs are active Since D7 has the highest priority and all inputs and outputs are active when LOW, the output bits are A = 0, B = and C = (b) Inputs D5 to D7 are the ones that are active among these, D7 has the highest priority Therefore, the output bits are A = 0, B = and C = (c) D7 is active Since D7 has the highest priority, it will be encoded irrespective of the logic status of other inputs Therefore, the output bits are A = 0, B = and C = Example 8.5 Design a four-line to two-line priority encoder with active HIGH inputs and outputs, with priority assigned to the higher-order data input line Solution The truth table for such a priority encoder is given in Table 8.10, with D0 , D1 , D2 and D3 as data inputs and X and Y as outputs The Boolean expressions for the two output lines X and Y are given by the equations X = D2 D3 + D3 = D2 + D3 (8.5) Y = D1 D2 D3 + D3 = D1 D2 + D3 (8.6) Figure 8.17 shows the logic diagram that implements the Boolean functions given in equations (8.5) and (8.6) Table 8.10 Example 8.5 D0 D1 D2 D3 X Y X X X X X 0 X 0 0 1 1 Multiplexers and Demultiplexers 285 D2 X D3 Y D1 Figure 8.17 Example 8.5 8.3 Demultiplexers and Decoders A demultiplexer is a combinational logic circuit with an input line, 2n output lines and n select lines It routes the information present on the input line to any of the output lines The output line that gets the information present on the input line is decided by the bit status of the selection lines A decoder is a special case of a demultiplexer without the input line Figure 8.18(a) shows the circuit representation of a 1-to-4 demultiplexer Figure 8.18(b) shows the truth table of the demultiplexer when the input line is held HIGH A decoder, as mentioned earlier, is a combinational circuit that decodes the information on n input lines to a maximum of 2n unique output lines Figure 8.19 shows the circuit representation of 2-to-4, 3-to-8 and 4-to-16 line decoders If there are some unused or ‘don’t care’ combinations in the n-bit code, then there will be fewer than 2n output lines As an illustration, if there are three input lines, it D0 1-to-4 D1 DEMUX D2 D3 I/P line B A (a) Select I/P 1 1 A 0 1 B 1 O/P D0 0 D1 0 D2 0 (b) Figure 8.18 1-to-4 demultiplexer D3 0 Digital Electronics 286 A 2-to-4 B A B 3-to-8 C A B 4-to-16 C D 15 Figure 8.19 Circuit representation of 2-to-4, 3-to-8 and 4-to-16 line decoders can have a maximum of eight unique output lines If, in the three-bit input code, the only used three-bit combinations are 000, 001, 010, 100, 110 and 111 (011 and 101 being either unused or don’t care combinations), then this decoder will have only six output lines In general, if n and m are respectively the numbers of input and output lines, then m ≤ 2n A decoder can generate a maximum of 2n possible minterms with an n-bit binary code In order to illustrate further the operation of a decoder, consider the logic circuit diagram in Fig 8.20 This logic circuit, as we will see, implements a 3-to-8 line decoder function This decoder has three inputs designated as A, B and C and eight outputs designated as D0 , D1 , D2 , D3 , D4 , D5 , D6 and D7 From the truth table given along with the logic diagram it is clear that, for any given input combination, only one of the eight outputs is in logic ‘1’ state Thus, each output produces a certain minterm that corresponds to the binary number currently present at the input In the present case, D0 , D1 , D2 , D3 , D4 , D5 , D6 and D7 respectively represent the following minterms: D0 → A B C D1 → A B C D2 → A B C D3 → A B C D4 → A B C D5 → A B C D6 → A B C D7 → A B C 8.3.1 Implementing Boolean Functions with Decoders A decoder can be conveniently used to implement a given Boolean function The decoder generates the required minterms and an external OR gate is used to produce the sum of minterms Figure 8.21 shows the logic diagram where a 3-to-8 line decoder is used to generate the Boolean function given by the equation Y = A B C +A B C +A B C +A B C (8.7) In general, an n-to-2n decoder and m external OR gates can be used to implement any combinational circuit with n inputs and m outputs We can appreciate that a Boolean function with a large number of minterms, if implemented with a decoder and an external OR gate, would require an OR gate with an equally large number of inputs Let us consider the case of implementing a four-variable Boolean function with 12 minterms using a 4-to-16 line decoder and an external OR gate The OR gate here needs to be a 12-input gate In all such cases, where the number of minterms in a given Boolean function with n variables is greater than 2n /2 (or 2n−1 , the complement Boolean function will have fewer minterms In that case it would be more advantageous to NORing of minterms of the complement Boolean function using a NOR gate rather than doing ORing of the given function using an OR gate The output will be nothing but the given Boolean function Multiplexers and Demultiplexers Figure 8.20 Logic diagram of a 3-to-8 line decoder 287 Digital Electronics 288 A B C 2 3-to-8 Decoder Y Figure 8.21 Implementing Boolean functions with decoders 8.3.2 Cascading Decoder Circuits There can possibly be a situation where the desired number of input and output lines is not available in IC decoders More than one of these devices of a given size may be used to construct a decoder that can handle a larger number of input and output lines For instance, 3-to-8 line decoders can be used to construct 4-to-16 or 5-to-32 or even larger decoder circuits The basic steps to be followed to carry out the design are as follows: If n is the number of input lines in the available decoder and N is the number of input lines in the desired decoder, then the number of individual decoders required to construct the desired decoder circuit would be 2N −n Connect the less significant bits of the input lines of the desired decoder to the input lines of the available decoder The left-over bits of the input lines of the desired decoder circuit are used to enable or disable the individual decoders The output lines of the individual decoders together constitute the output lines, with the outputs of the less significant decoder constituting the less significant output lines and those of the higher– order decoders constituting the more significant output lines The concept is further illustrated in solved example 8.8, which gives the design of a 4-to-16 decoder using 3-to-8 decoders Example 8.6 Implement a full adder circuit using a 3-to-8 line decoder Solution A decoder with an OR gate at the output can be used to implement the given Boolean function The decoder should at least have as many input lines as the number of variables in the Boolean function to be implemented The truth table of the full adder is given in Table 8.11, and Fig 8.22 shows the hardware implementation From the truth table, Boolean functions for SUM and CARRY outputs are given by the following equations: Sum output S = (8.8) Carry output Co = (8.9) Multiplexers and Demultiplexers 289 Example 8.6 Table 8.11 A B C S Co 0 0 1 1 0 1 0 1 1 1 1 0 0 1 1 A B C S 2 3-to-8 Decoder Co Figure 8.22 Example 8.6 Example 8.7 A combinational circuit is defined by F = 0, 2, 5, 6, Hardware implement the Boolean function F with a suitable decoder and an external OR/NOR gate having the minimum number of inputs Solution The given Boolean function has five three-variable minterms This implies that the function can be implemented with a 3-to-8 line decoder and a five-input OR gate Also, F will have only three three-variable minterms, which means that F could also be implemented by considering minterms corresponding to the complement function and using a three-input NOR gate at the output The second option uses a NOR gate with fewer inputs and therefore is used instead F = 0, 2, 5, 6, Therefore, F = 1, 3, Figure 8.23 shows the hardware implementation of Boolean function F Digital Electronics 290 C B A 2 3-to-8 Decoder F Figure 8.23 Example 8.7 Example 8.8 Construct a 4-to-16 line decoder with two 3-to-8 line decoders having active LOW ENABLE inputs Solution Let us assume that A (LSB), B, C and D (MSB) are the input variables for the 4-to-16 line decoder Following the steps outlined earlier, A (LSB), B and C (MSB) will then be the input variables for the two 3-to-8 line decoders If we recall the 16 possible input combinations from 0000 to 1111 in the case of a 4-to-16 line decoder, we find that the first eight combinations have D = 0, with CBA going through 000 to 111 The higher-order eight combinations all have D = 1, with CBA going through 000 to 111 If we use the D-bit as the ENABLE input for the less significant 3-to-8 line decoder and the D-bit as the ENABLE input for the more significant 3-to-8 line decoder, the less significant 3-to-8 line decoder will be enabled for the less significant eight of the 16 input combinations, and the more significant 3-to-8 line decoder will be enabled for the more significant of the 16 input combinations Figure 8.24 shows the hardware implementation One of the output lines D0 to D15 is activated as the input bit sequence DCBA goes through 0000 to 1111 Example 8.9 Figure 8.25 shows the logic symbol of IC 74154, which is a 4-to-16 line decoder/demultiplexer The logic symbol is in ANSI/IEEE format Determine the logic status of all 16 output lines for the following conditions: (a) D = HIGH, C = HIGH, B = LOW, A = HIGH, G1 = LOW and G2 = LOW (b) D = HIGH, C = HIGH, B = LOW, A = HIGH, G1 = HIGH and G2 = HIGH (c) D = HIGH, C = HIGH, B = LOW, A = HIGH, G1 = HIGH and G2 = HIGH Solution It is clear from the given logic symbol that the device has active HIGH inputs, active LOW outputs and two active LOW ENABLE inputs Also, both ENABLE inputs need to be active for the decoder to function owing to the indicated ANDing of the two ENABLE inputs Multiplexers and Demultiplexers 291 C B A D E 2 3-to-8 Decoder 3-to-8 Decoder E Figure 8.24 Example 8.8 74154 1(A) 2(B) 4(C) 8(D) G1 G2 & 10 11 12 13 14 15 Figure 8.25 Example 8.9 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D 10 D 11 D 12 D 13 D 14 D 15 Digital Electronics 292 (a) Since both ENABLE inputs are active, the decoder outputs will therefore be active depending upon the logic status of the input lines For the given logic status of the input lines, decoder output line 13 will be active and therefore LOW All other output lines will be inactive and therefore in the logic HIGH state (b) Since neither ENABLE input is active, all decoder outputs will be inactive and in the logic HIGH state (c) The same as (b) Example 8.10 The decoder of example 8.9 is to be used as a 1-of-16 demultiplexer A logically compatible pulsed waveform is to be switched between output line and line 15 when the logic status of an external control input is LOW and HIGH respectively Draw the logic diagram indicating the logic status of ENABLE inputs and DCBA inputs and the point of application of the pulsed waveform Solution Figure 8.26 shows the logic diagram When the external control input is in the logic LOW state, D = HIGH, C = LOW, B = LOW and A = HIGH This means that output line is activated When the external control input is in the logic HIGH state, D = HIGH, C = HIGH, B = HIGH and A = HIGH This means that output line 15 is activated In the logic diagram shown in Fig 8.26, the two ENABLE inputs are tied together and the pulsed waveform is applied to a common point This means that either both ENABLE inputs are active (when the input waveform is in the logic LOW state) or inactive (when the input waveform is in the logic HIGH state) Thus, when the input waveform is in the logic LOW state, output line will be in the logic LOW state and all other output lines will be in the logic HIGH state provided the external control input is also in the logic LOW state If the external 74154 '1’ 1(A) 2(B) External Control 4(C) 8(D) G1 G2 & Figure 8.26 Example 8.10 10 11 12 13 14 15 Multiplexers and Demultiplexers 293 control input is in the logic HIGH state, logic LOW in the input waveform appears at output line 15 In essence, the logic status of the input waveform is reproduced at either line or line 15, depending on whether the external control signal is LOW or HIGH 8.4 Application-Relevant Information Table 8.12 lists commonly used IC type numbers used as multiplexers, encoders, demultiplexers and decoders Application-relevant information such as the pin connection diagram, truth table, etc., in respect of the more popular of these type numbers is given in the companion website Table 8.12 Commonly used IC type numbers used as multiplexers, encoders, demultiplexers and decoders IC Type number Function Logic family 7442 74138 74139 74145 74147 74148 74150 74151 74152 74153 74154 74155 74156 74157 74158 74247 74248 74251 74253 74256 74257 74258 74259 74298 74348 74353 74398 74399 4019 4028 40147 4511 4512 4514 1-of-10 decoder 1-of-8 decoder/demultiplexer Dual 1-of-4 decoder/demultiplexer 1-of-10 decoder/driver (open collector) 10-line to four-line priority encoder Eight-line to three-line priority encoder 16-input multiplexer Eight-input multiplexer Eight-input multiplexer Dual four-input multiplexer 4-of-16 decoder/demultiplexer Dual 1-of-4 decoder/demultiplexer Dual 1-of-4 decoder/demultiplexer (open collector) Quad two-input noninverting multiplexer Quad two-input inverting multiplexer BCD to seven-segment decoder/driver (open collector) BCD to seven-segment decoder/driver with Pull-ups Eight-input three-state multiplexer Dual four-input three-state multiplexer Dual four-bit addressable latch Quad two-input non-inverting three-state multiplexer Quad two-input inverting three-state multiplexer Eight-bit addressable latch Dual two-input multiplexer with output latches Eight-line to three-line priority encoder (three-state) Dual four-input multiplexer Quad two-input multiplexer with output register Quad two-input multiplexer with output register Quad two-input multiplexer 1-of-10 decoder 10-line to four-line BCD priority encoder BCD to seven-segment latch/decoder/driver Eight-input three-state multiplexer 1-of-16 decoder/demultiplexer with input latch TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL TTL CMOS CMOS CMOS CMOS CMOS CMOS (continued overleaf ) Digital Electronics 294 Table 8.12 (continued) IC Type number Function Logic family 4515 4532 4539 4543 1-of-16 decoder/demultiplexer with input latch Eight-line to three-line priority encoder Dual four-input multiplexer BCD to seven-segment latch/decoder/driver for LCD displays Dual 1-of-4 decoder/demultiplexers Dual 1-of-4 decoder/demultiplexers Dual four-bit addressable latch Eight-bit addressable latch Dual two-input multiplexer with latch and common reset Dual multiplexer with latch Quad two-input multiplexer (non-inverting) Quad two-input multiplexer (inverting) 3-to-8 line decoder (LOW) 3-to-8 line decoder (HIGH) Eight-line multiplexer Eight-input priority encoder Dual 2-to-4 line decoder (LOW) Dual 2-to-4 line decoder (HIGH) Quad two-input multiplexer/latch Dual 4-to-1 multiplexer CMOS CMOS CMOS CMOS 4555 4556 4723 4724 10132 10134 10158 10159 10161 10162 10164 10165 10171 10172 10173 10174 CMOS CMOS CMOS CMOS ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL ECL Review Questions What is a multiplexer circuit? Briefly describe one or two applications of a multiplexer? Is it possible to enhance the capability of an available multiplexer in terms of the number of input lines it can handle by using more than one device? If yes, briefly describe the procedure to so, with the help of an example What is an encoder? How does a priority encoder differ from a conventional encoder? With the help of a truth table, briefly describe the functioning of a 10-line to four-line priority encoder with active LOW inputs and outputs and priority assigned to the higher-order inputs What is a demultiplexer and how does it differ from a decoder? Can a decoder be used as a demultiplexer? If yes, from where we get the required input line? Briefly describe how we can use a decoder optimally to implement a given Boolean function? Illustrate your answer with the help of an example Draw truth tables for the following: (a) an 8-to-1 multiplexer with active LOW inputs and an active LOW ENABLE input; (b) a four-line to 16-line decoder with active HIGH inputs and active LOW outputs and an active LOW ENABLE input; (c) an eight-line to three-line priority encoder with active LOW inputs and outputs and an active LOW ENABLE input Multiplexers and Demultiplexers 295 Problems Implement the three-variable Boolean function F A B C = A C + A B C + A B C using (i) an 8-to-1 multiplexer and (ii) a 4-to-1 multiplexer (i) Fig 8.27(a); (ii) Fig 8.27(b) '0’ '1’ I0 I1 I2 I3 I4 I5 I6 I7 8-to-1 MUX F S2 S1 S0 A B C (a) '0’ I0 '1’ I1 A I2 I3 4-to-1 MUX S1 S0 B C F (b) Figure 8.27 Problem Design a 32-to-1 multiplexer using 8-to-1 multiplexers having an active LOW ENABLE input and a 2-to-4 decoder Fig 8.28 Digital Electronics 296 D0 I0 I1 D7 I7 E S0 S1 S2 D8 I0 I1 S0 S1 S2 D15 S3 S4 S1 2-to-4 Decoder S2 I7 E S0 S1 S2 8-to-1 MUX Y 8-to-1 MUX Y F D16 I0 I1 8-to-1 MUX Y D23 I7 E S0 S1 S2 D24 I0 I1 D31 I7 E S0 S1 S2 8-to-1 MUX Y Figure 8.28 Answer to problem Multiplexers and Demultiplexers 297 Determine the function performed by the combinational circuit of Fig 8.29 Figure 8.29 Problem 4-to-1 multiplexer Implement a full subtractor combinational circuit using a 3-to-8 decoder and external NOR gates Fig 8.30 Difference A B Bin 2 3-to-8 Decoder Figure 8.30 Answer to problem Borrow Out 298 Digital Electronics Further Reading Floyd, T L (2005) Digital Fundamentals, Prentice-Hall Inc., USA Tokheim, R L (1994) Schaum’s Outline Series of Digital Principles, McGraw-Hill Companies Inc., USA Tocci, R J (2006) Digital Systems – Principles and Applications, Prentice-Hall Inc., NJ, USA Cook, N P (2003) Practical Digital Electronics, Prentice-Hall, NJ, USA Rafiquzzaman, M (2005) Fundamentals of Digital Logic and Microcomputer Design, Wiley-Interscience, New York, USA Morris Mano, M and Kime, C R (2003) Logic and Computer Design Fundamentals, Prentice-Hall Inc., USA ... Gray 0000 00 01 0 010 0 011 010 0 010 1 011 0 011 1 0000 00 01 0 011 0 010 011 0 011 1 010 1 010 0 10 11 12 13 14 15 10 00 10 01 1 010 10 11 110 0 11 01 111 0 11 11 110 0 11 01 111 1 11 10 10 10 10 11 10 01 1000 Digital Electronics... 0 010 0 010 0 010 0 011 0 011 0 011 0 011 0 011 0 011 0 011 0 011 0 011 0 011 0 011 0 011 0 011 0 011 0 011 0 011 010 0 010 0 0 010 0 011 010 0 010 1 011 0 011 1 10 00 10 01 1 010 10 11 110 0 11 01 111 0 11 11 0000 00 01 0 010 0 011 ... 11 11 0000 00 01 0 010 0 011 010 0 010 1 011 0 011 1 10 00 10 01 1 010 10 11 110 0 11 01 111 0 11 11 0000 00 01 0 010 0 011 010 0 010 1 011 0 011 1 10 00 10 01 1 010 10 11 110 0 11 01 111 0 11 11 0000 00 01 Code Code description