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MINISTRY OF EDUCATION AND TRANING MINISTRY OF DEFENSE ACADEMY OF MILITARY SCIENCE AND TECHNOLOGY TRAN DINH LAM RESEARCHING ON THE DEVELOPMENT OF HARDWARE IMPLEMENTATION SOLUTION FOR THE CONTEXT-ADAPTIVE BINARY ARITHMETIC CODER IN THE HEVC STANDARD Ph.D THESIS IN ENGINEERING Ha Noi - 2021 MINISTRY OF EDUCATION AND TRANING MINISTRY OF DEFENSE ACADEMY OF MILITARY SCIENCE AND TECHNOLOGY TRAN DINH LAM RESEARCHING ON THE DEVELOPMENT OF HARDWARE IMPLEMENTATION SOLUTION FOR THE CONTEXT-ADAPTIVE BINARY ARITHMETIC CODER IN THE HEVC STANDARD Specialization: Electronic engineering Code: 52 02 03 Ph.D THESIS IN ENGINEERING SCIENTIFIC SUPERVISOR: ASSOC PROF DR TRAN XUAN TU Ha Noi - 2021 i STATEMENT OF AUTHORSHIP Except where reference is made in the text of the thesis, this thesis contains no material published elsewhere or extracted in whole or in part from a thesis or any other degree or diploma No other person’s work has been used without acknowledgment in the main text of the thesis This thesis has not been submitted for the award of any degree or diploma in any other tertiary institution Hanoi, Date month year 2021 Author Tran Dinh Lam ii ACKNOWLEDGEMENTS During the research work and fulfill the Ph.D thesis, I have received tremendous support, facilitated from Institute of Electronics, Training Department of Academy of Military Science and Technology I would like to express my sincere thanks to the representatives of the organisations I would like to express my deep gratitude to my supervisor, Assoc Prof., Dr Tran Xuan Tu for his continuous support, encouragement and supervision throughout my research work and the completion of this thesis I would also like to extend my gratitude to the teachers in the Institute of Electronics, the Academy of Military Science and Technology for their valuable suggestions during my research I would like to thank the teachers and other members of VNU Key Labpratory for Smart Integrated Systems (SISLAB) for their comments and supports throughout my PhD work I would like to thank my colleagues and friends, who always support and encourage me during taking the PhD Last but not least, I would like to express my sincere gratitude to my family, relatives who have shared and always encouraged me to overcome difficulties to successfully complete this thesis Hanoi, Date month year 2021 Author Tran Dinh Lam iii CONTENTS Page LIST OF ABBREVIATIONS …………………….…………………….… vi LIST OF TABLES……….………….………….………….………….…… ix LIST OF FIGURES……….………….………….………….………….…… x INTRODUCTION………………………………………………………… Chapter OVERVIEW OF THE CONTEXT ADAPTIVE BINARY ARITHMETIC CODING IN THE HEVC STANDARD 1.1 Development history of video encoding standard 1.1.1 The necessity of video encoding 1.1.2 The evolution of video compression standards 1.2 Principle of video encoding in the HEVC standard 10 1.2.1 The architecture of the HEVC encoder 10 1.2.2 The improvements of encoding algorithms in the HEVC standard 11 1.2.3 Principle and architecture of a CABAC encoder for HEVC 19 1.3 Overview on the development of CABAC encoder in HEVC standard 25 1.3.1 Research directions of hardware development towards realizing CABAC in HEVC standard for video applications 26 1.3.2 Solutions to improve encoding throughput 29 1.3.3 High efficient hardware architecture 35 1.3.4 Conclusion on research and development, thesis research orientation 38 1.4 Chapter conclusion 39 Chapter PROPOSE HARDWARE DESIGN SOLUTIONS TO IMPROVE THE EFFICIENCY OF THE CABAC ENCODER IN THE HEVC STANDARD 41 2.1 Proposed funtional block diagram of CABAC encoder architecture 41 2.2 Binarizer 43 2.2.1 Data statistics of Binarizer 43 2.2.2 The structure of residual syntax elements 45 iv 2.2.3 The drawbacks of multi-core syntax element generation architecture 49 2.2.4 The “one scan for multiple syntax element generation” technique 52 2.2.5 The solution for binarization of last_sig_coeff_post syntax element 56 2.3 Binary arithmetic encoding (BAE) module 59 2.3.1 The context-adaptive encoding algorithm 60 2.3.2 Algorithm modification for simultaneously encoding multi bypass bins 63 2.3.3 The hardware solution for four-stage BAE architecture 65 2.3.4 Proposed architecture for hardware savings 67 2.4 Chapter conclusion 71 Chapter SIMULATION, VERIFICATION, IMPLEMENTATION AND EVALUATION OF THE RESEARCH RESULTS 73 3.1 Building the simulation software model 74 3.1.1 HM Test Model 74 3.1.2 Building the software model for verification 75 3.2 Proposing the Hardware-Software co-simulation model for verification the research results 76 3.2.1 CodecVisa tool 76 3.2.2 The experimental model for verification of the results 78 3.3 Simulation and verification of proposed design solutions 84 3.4 Synthesis, simulation and evaluation of parameters of proposed design solutions 88 3.4.1 Report of performance parameters for residual syntax element generation module 89 3.4.2 Report of performance parameters for Binarization module 90 3.4.3 Report of performance parameters for Binary Arithmetic Encoding module 91 3.5 Summary of proposed research results and comparisons with related state-of-the-art results 92 3.6 Chapter conclusion 95 CONCLUSION 96 v LIST OF SCIENTIFIC PUBLICATIONS 99 BIBLIOGRAPHY 100 vi LIST OF ABBREVIATIONS AI All Intra ASIC Application Specific Integrated Circuit AVC Advanced Video Coding BAE Binary Arithmetic Encoder BIBO Block-In-Block-Out CABAC Context Adaptive Binary Arithmetic Coding CALR Coefficient Absolute Level Remaining CALVC Context Adaptive Variable Length Coding CB Coding Block CG Coefficient Group CM Context Modeler CODEC COding DECoding CTB Coding Tree Block CTU Coding Tree Unit CU Coding Unit DCT Discrete Cosine Transform DST Discrete Sine Transform EGk Exponential Golomb k-order FIFO First In First Out FL Fixed Length FSM Finite State Machine vii HDTV High Definition TeleVision HEVC High Efficient Video Coding ISO/IEC International Organization for Standardization/ International Electrotechnical Commission ITU-T International Telecommunication Union – Telecommunication JCT-VC Joint Collaborative Team – Video Coding LD Low Delay LPS Least Probably Symbol LUT Look Up Table MBBS Multi Bypass Bin Spliting MC Motion Compensation MRSET Multiple Residual Syntax Element Treatment MPEG Moving Picture Expert Group MPS Most Probably Symbol MV Motion Vector PB Prediction Block PISO Parallel In Serial Out PU Prediction Unit RD Random Access rLPS range Least Probably Symbol RTL Register Transfer Level SAO Sample Adaptive Offset viii SE Syntax Element TB Transform Block TC Transform Coefficient TU Transform Unit UHD Ultra High Definition UHD-TV Ultra High Definition-TeleVision VHDL Very-high-speed-integrated-circuit Hardware Description Language VLSI Very Large Scale Integration WPP Wave-front Parallel Processing 94 the [41] has the highest efficiency and is followed by the results of the thesis However, the work in [41] is just a low-performance low-cost binarization core, which is not able to support UHD applications Its throughput is only 200 Mbins/s while the thesis’s throughput is 1525 Mbins/s (7.6 times higher) In comparison with other high throughput designs for UHD applications ([2], [49], [65] and [68]), the thesis achieves the highest efficiency (1.293) which is four times and 20 times better than those of [2] and [49], respectively The residual syntax element generation module is a power efficiency solution by reducing the frequency of memory access It processes 3,5 SEs/clock at the frequency of 500 MHz, which can support data throughput for high-speed CABAC encoder in UHD video applications In addition, the throughput is comparable to those of [2], [65], [68] It is almost half of Ramos [49], which is a parallel four-core design operating at the frequency of 668 MHz However, the power consumption of the thesis is only 0.055 mW, which is much lower than Ramos’s solution (11.52 mW) Over 90% of power consumption in Ramos’s proposal is dynamic power consumption Because Ramos applies a parallel four-core architecture to process TBs of 44 data blocks, then the hardware is more complex It has to utilize buffer designs and exchange data between cores Moreover, the four-core design will consume more dynamic power due to the higher frequency of memory access For the power-efficient aspect (measured in Mbins/mW), the thesis solution achieves the highest one (8,228 Mbins/mW), which is double of [2] and [41] The proposed solution and the corresponding result of the thesis are published in the third article of the list of published works Table 3.16 compares the research results, proposed technical solutions for BAE modules with other works and is published in the second article of the list of published works The proposed BAE design achieves the throughput of 1134 Mbins/s, which allows encoding UHD video formats It is 95 a moderate throughput compared with the results of other works in Table 3.16 Regarding the hardware efficiency, compared with other single-core BAEs, the BAE design of the thesis has the highest efficiency The hardware area cost of 2.2 KGates is the smallest in comparison with [27], [40] and [42], which are 3.17, 3.96 and 24.95 KGates, respectively Table 0.16 Comparison with the state-of-the-art works in implementation of BAE module Bins/clock Clock frequency (MHz) Technology (nm) Throughput (Mbin/s) Area cost (K Gates) Power consumption (mW) Peng2013 [40] 1.18 Zhou2015 Pham2014 [68] [42] 4.37 Jo2016 Ramos2016 Thesis [27] [46] results 1.99 1.4 357 420 180 1530 1110 280 810 130 90 180 65 65 45 45 421 1836 180 1530 2219 1120 1134 24.95 7.98 3.96 3.17 5.68 9.95 2.2 - - 2.88 - - 2.49 2.0 3.6 Chapter conclusion In this chapter, based on surveying the software tools recommended by ITU-T, the thesis has proposed a simulation solution to verified the research results A Hardware-Software co-simulation architecture is built to generate test vectors for simulation and evaluation of each proposed hardware solution The hardware solution proposals in Chapter are modeled and simulated at the RTL level to evaluate the correctness of the solution Finally, the performance efficiency of hardware solutions is evaluated by the Synopsys IC design tool in terms of design area and power consumption The research results are compared with other related works to evaluate the efficiency of proposed solutions Thesis results have been also published in an IEEE international conference proceedings - ICDV17 (publication 2) and in an international journal MPDI-Electronics that is in the ISI list (publication 3) 96 CONCLUSION The HEVC standard is proposed to support effectively encoding high- quality real-time digital video streams Since the standard was published (April 2013), the realization of the HEVC standard into video applications has faced many challenges Researching and proposing technical solutions, especially hardware solutions, are important in applying the standard diversely into various video services In the framework of this doctoral thesis, the Ph.D student focuses on researching and proposing solutions to improve the performance of CABAC encoder hardware in the HEVC standard The thesis achievements contribute to this evolution To sum up, based on the research work has been conducted, this part presents conclusions drawn from the main achievements and contributions of this thesis, including: Research outcomes The thesis “Research and development of hardware implementation solutions for the context-adapted binary arithmetic encoder in the HEVC standard” has contributed to solving the problems in the hardware implementation of the CABAC encoder The proposed solutions aim to effectively apply the HEVC standard in next-generation multimedia services The thesis has studied the hardware architecture design solutions for the CABAC encoder, processing techniques for residual video data Particularly, it focuses on the main component modules of the CABAC encoder such as residual syntax element generation, binarization and binary arithmetic encoder Accordingly, the three main issues that the dissertation solves are: Firstly, the thesis has proposed an efficient algorithm and solution in terms of power consumption in hardware implementation for the residual syntax element generation module The one scan for multiple syntax element generation technique has been applied to reduce the frequency of memory access, thus reducing dynamic power consumption for this module 97 Secondly, an efficient hardware resource usage solution has been proposed for the binarization module The combined-binarization technique was applied to implement the binarization process for several syntax elements on the same hardware architecture As a result, the hardware resource is reduced and the internal datapath is simplified, which contributes to improving the hardware efficiency of the binarization module Thirdly, the thesis has proposed an efficient hardware usage in the implementation of the binary arithmetic encoding module In the four-stage BAE architecture, the proposed “multiple bypass bin processing” solution allows the processing of high throughput video streams Whereas, the proposed pre-multiply and unified datapath techniques have been applied to reduce the number of stage-buffered registers and the number of datapaths for hardware savings in implementation The main research results of the dissertation have been published in three articles published in scientific journals, the proceedings of prestigious scientific conferences The publications are the authors’ own work and are compatible with the thesis proposals The proposed solutions in the thesis were evaluated, modeled at RTL level using VHDL and simulated by software tools The hardware implementation was synthesized on the specialized IC design tool The results of synthesis and simulation were used to evaluate and compare with other related works The implementation hardware designs were tested and evaluated on the HM Test Model and the CodecVisa tools The standard video test sequences recommended by ITU-T for validating hardware implementation solutions were employed in the software model to build test vectors for verification Contributions This thesis has proposed techniques and developed hardware solutions for the CABAC encoder in the HEVC standard towards improving efficiency 98 in hardware resource and energy consumption The thesis has three main contributions that are specificated as follows: - Proposing the “one scanning for multiple syntax element generation” techniques in order to reduce the power consumption of the residual syntax element generation module - Proposing the “combined binarization” technique to save hardware resources in implementing the binarization module - Proposing the “pre-multiply” and “unified datapath” to save hardware resources in implementing the binary arithmetic encoding module Future research works Based on the achieved results of the thesis, future research objectives are expected as follows: - Further simulating the proposed solution of the thesis with different high-quality video sequences for more diverse evaluations - Conducting research work to propose efficient techniques and architectural design solutions for the remaining modules in the CABAC encoder This will contribute to implementing a complete high efficient hardware architecture of the CABAC encoder for video applications on mobile battery-powered devices - Continue to research high-efficiency hardware solutions for other functional modules of the HEVC encoder in the form of IP cores to propose a complete hardware implementation of the HEVC encoder - Based on the completed hardware implementation, several experiments of the HEVC encoder should be carried out on DSP, FPGA hardware platforms Otherwise, a VLSI implementation of an HEVC encoder is expected to be fulfilled for special applications 99 LIST OF SCIENTIFIC PUBLICATIONS Dinh-Lam Tran, Viet-Huong Pham, Kiem Hung Nguyen and Xuan-Tu Tran, “A Survey of High-Efficient CABAC Hardware Implementations in HEVC Standard,” VNU Journal of Computer Science and Communication Engineering, vol 35, no 2, pp 1-21, 2019 Quang-Linh Nguyen, Dinh-Lam Tran, Duy-Hieu Bui, Duc-Tho Mai and Xuan-Tu Tran, “Efficient Binary Arithmetic Encoder for HEVC with Multiple Bypass Bin Processing,” in The 7th IEEE International Conference on Integrated Circuits, Design, and Verification, Hanoi, Vietnam, 2017, pp.82-87 DOI: 10.1109/ICDV.2017.8188644 Dinh-Lam Tran, Xuan-Tu Tran, Duy-Hieu Bui, Cong-Kha Pham An Efficient Hardware Implementation of Residual Data Binarization in HEVC CABAC Encoder Electronics, vol 9, issue 4, p 684, April 2020 ISSN 20799292 (SCI, IF 2.412, Q1) DOI:10.3390/electronics9040684 100 BIBLIOGRAPHY English [1] M Abeydeera, M Karunaratne, G Karunaratne, K Silva and A Pasqual, “4K Real Time HEVC Decoder on FPGA,” IEEE Transactions on Circuits and Systems for Video Technology, Vol 26, Issue 1, 2015 [2] C.-M Alonso, “Low-power HEVC Binarizer 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H.265/HEVC,” IEEE Transactions on Circuits and Systems for Video Technology, Vol.28, Issue 2, Feb 2018 [71] https://media.xiph.org/video/derf/ [72] ftp://ftp.kw.bbc.co.uk/hevc/hm-10.0-anchors/bitstreams/ra_main/ [73] http://trace.eas.asu.edu/yuv/ ... ARITHMETIC CODING IN THE HEVC STANDARD Preamble Chapter presents the theoretical basis of video encoding, video encoding standards and the CABAC encoder in HEVC standards This Chapter also reports... the HEVC standard 1.2.1 The architecture of the HEVC encoder As an enhancement of the H.264/AVC standard, the HEVC architecture was designed to encode video in blocks of image data However, HEVC. .. diagram of HEVC encoder [57] 11 Figure 1.3 Block division technique of HEVC and H.264/AVC standards 12 Figure 1.4 The partition and organization techniques of video data in HEVC
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