Recommendation 3-1 - Internal assertions should be used instead of comments.
Recommendation 3-2 - Internal corner cases should be identified using coverage properties or coverage group.
Recommendation 3-3 - Assertions on internal signals should be placed with the design code.
Recommendation 3-4 - Assertions inside always blocks should be used with caution.
Recommendation 3-5 - Inlined assertions should be embedded in ‘ifdef blocks.
Rule 3-6 - Assertions for normal DUT operations shall be disabled when reset is in progress.
Recommendation 3-7 - The checkers from the VMM checker library should be used wherever possible.
Rule 3-8 - Assertion-based checkers shall be encapsulated using an interface construct.
Rule 3-9 - Every FSM shall have assertions that verify the state encoding and transitions.
Rule 3-10 - Every internal block interface shall have assertions that verify the assumed interface protocol.
Recommendation 3-11 - Interface-related assertions or checkers should be specified in the interface declarations.
Rule 3-12 - Every FIFO, stack or memory shall have assertions on its proper use.
Rule 3-13 - Assertions shall be used to verify that arbitration for access to resources follows the appropriate rules.
Rule 3-14 - There shall be no assertion on the periodicity of the system clock itself.
Rule 3-15 - There shall be no concurrent assertion to monitor combinatorial signal glitches or asynchronous timing.
Rule 3-16 - There shall be no assertion that verifies the correctness of the SystemVerilog language or known-to-be-good components.
Recommendation 3-17 - Assertions should verify that arithmetic operations do not overflow and/or the target registers do not change value by more than some +/- delta.
Rule 3-18 - Decoding and selection logic shall have assertions to verify mutual exclusion.
Rule 3-19 - Whenever a signal is to hold for some time or until some condition occurs, such behavior shall be verified using assertions.
Rule 3-20 - Any time-bounded well-defined relationship between signals shall be checked using assertions.
Rule 3-21 - During a reset, conditions on control signals and shared buses shall be verified using assertions.
Suggestion 3-22 - A category attribute on assert and cover property statements may be used for tool-specific control of assertions in simulation.
Rule 3-23 - A specific failure message of an assert property statement shall be produced through a VMM message service interface in the action block of the assertion.