VFP Instructions Notes Absolute value function The function abs(x) means a copy of x with its sign bit forced to zero, as defined in the Appendix to the IEEE 754-1985 standard Flush-to-zero mode The FZ bit of the FPSCR does not affect the operand or result of this instruction Vectors When the LEN field of the FPSCR indicates scalar mode (vector length 1), FABSD performs just one absolute value operation, and vec_len=1, Dd[0]=Dd, and Dm[0]=Dm When the LEN field indicates a vector mode (vector length > 1), FABSD might perform more than one absolute value operation Addressing Mode - Double-precision vectors (monadic) on page C5-19 describes how FABSD encodes the registers it uses and how vec_len, Dd[i], and Dm[i] are determined Signaling NaNs To comply with the VFP architecture, FABSD must not generate an exception even if the value in its source register is a signaling NaN This is a more stringent requirement than the one in the Appendix to the IEEE 754-1985 standard ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-3 VFP Instructions 4.1.2 FABSS 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cond 1 1 D 1 0 0 12 11 10 Fd 1 1 M 0 Fm The FABSS (Floating-point Absolute Value, Single-precision) instruction writes the absolute value of a single-precision register to another single-precision register It can also perform a vector version of this operation Syntax FABSS{} , where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the destination register Its number is encoded as Fd (top bits) and D (bottom bit) Specifies the source register Its number is encoded as Fm (top bits) and M (bottom bit) Architecture version All Exceptions None Operation if ConditionPassed(cond) then for i = to vec_len-1 Sd[i] = abs(Sm[i]) C4-4 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions Notes Absolute value function The function abs(x) means a copy of x with its sign bit forced to zero, as defined in the Appendix to the IEEE 754-1985 standard Flush-to-zero mode The FZ bit of the FPSCR does not affect the operand or result of this instruction Vectors When the LEN field of the FPSCR indicates scalar mode (vector length 1), FABSS performs just one absolute value operation, and vec_len=1, Sd[0]=Sd, and Sm[0]=Sm When the LEN field indicates a vector mode (vector length > 1), FABSS might perform more than one absolute value operation Addressing Mode - Single-precision vectors (monadic) on page C5-14 describes how FABSS encodes the registers it uses and how vec_len, Sd[i], and Sm[i] are determined Signaling NaNs To comply with the VFP architecture, FABSS must not generate an exception even if the value in its source register is a signaling NaN This is a more stringent requirement than the one in the Appendix to the IEEE 754-1985 standard ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-5 VFP Instructions 4.1.3 FADDD 31 28 27 26 25 24 23 22 21 20 19 cond 1 0 1 16 15 Dn 12 11 10 Dd 1 0 0 Dm The FADDD (Floating-point Addition, Double-precision) instruction adds together two double-precision registers and writes the result to a third double-precision register It can also perform a vector version of this operation Syntax FADDD{} , , where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the destination register Specifies the register that contains the first operand for the addition Specifies the register that contains the second operand for the addition Architecture version D variants only Exceptions Floating-point exceptions: Invalid Operation, Overflow, Inexact Operation if ConditionPassed(cond) then for i = to vec_len-1 Dd[i] = Dn[i] + Dm[i] C4-6 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions Notes Vectors When the LEN field of the FPSCR indicates scalar mode (vector length 1), FADDD performs just one addition, and vec_len=1, Dd[0]=Dd, Dn[0]=Dn, and Dm[0]=Dm When the LEN field indicates a vector mode (vector length > 1), FADDD might perform more than one addition Addressing Mode - Double-precision vectors (non-monadic) on page C5-8 describes how FADDD encodes the registers it uses and how vec_len, Dd[i], Dn[i], and Dm[i] are determined Rounding ARM DDI 0100E The operation is a fully-rounded addition The rounding mode is determined by the FPSCR Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-7 VFP Instructions 4.1.4 FADDS 31 28 27 26 25 24 23 22 21 20 19 cond 1 0 D 1 16 15 Fn 12 11 10 Fd 1 N M 0 Fm The FADDS (Floating-point Addition, Single-precision) instruction adds together two single-precision registers and writes the result to a third single-precision register It can also perform a vector version of this operation Syntax FADDS{} , , where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the destination register Its number is encoded as Fd (top bits) and D (bottom bit) Specifies the register that contains the first operand for the addition Its number is encoded as Fn (top bits) and N (bottom bit) Specifies the register that contains the second operand for the addition Its number is encoded as Fm (top bits) and M (bottom bit) Architecture version All Exceptions Floating-point exceptions: Invalid Operation, Overflow, Inexact Operation if ConditionPassed(cond) then for i = to vec_len-1 Sd[i] = Sn[i] + Sm[i] C4-8 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions Notes Vectors When the LEN field of the FPSCR indicates scalar mode (vector length 1), FADDS performs just one addition, and vec_len=1, Sd[0]=Sd, Sn[0]=Sn, and Sm[0]=Sm When the LEN field indicates a vector mode (vector length > 1), FADDS might perform more than one addition Addressing Mode - Single-precision vectors (non-monadic) on page C5-2 describes how FADDS encodes the registers it uses and how vec_len, Sd[i], Sn[i], and Sm[i] are determined Rounding ARM DDI 0100E The operation is a fully-rounded addition The rounding mode is determined by the FPSCR Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-9 VFP Instructions 4.1.5 FCMPD 31 28 27 26 25 24 23 22 21 20 19 cond 16 15 1 1 1 0 12 11 10 Dd 1 1 0 Dm The FCMPD (Floating-point Compare, Double-precision) instruction compares two double-precision registers, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction) Syntax FCMPD{} , where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the register which contains the first operand for the comparison Specifies the register which contains the second operand for the comparison Architecture version D variants only Exceptions Floating-point exceptions: Invalid Operation Operation if ConditionPassed(cond) then if (Dd is a signaling NaN) or (Dm is a signaling NaN) then raise Invalid Operation exception FPSCR N flag = if (Dd < Dm) then else FPSCR Z flag = if (Dd == Dm) then else FPSCR C flag = if (Dd < Dm) then else FPSCR V flag = if (Dd and Dm compare as unordered) then else C4-10 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions Notes Vectors FCMPD always specifies a scalar operation, regardless of the LEN field of the FPSCR NaNs The IEEE 754 standard specifies that the result of a comparison is precisely one of or unordered If either or both of Dd and Dm are NaNs, they are unordered, and all three of (Dd < Dm), (Dd == Dm) and (Dd > Dm) are false This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1 FCMPD only raises an Invalid Operation exception if one or both operands are signaling NaNs, and is suitable for testing for ==, !=, unorderedness, and other predicates which not raise an exception when the operands are unordered ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-11 VFP Instructions 4.1.6 FCMPED 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cond 1 1 1 0 12 11 10 Dd 1 1 0 Dm The FCMPED (Floating-point Compare (NaN Exceptions), Double-precision) instruction compares two double-precision registers, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction) Syntax FCMPED{} , where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the register which contains the first operand for the comparison Specifies the register which contains the second operand for the comparison Architecture version D variants only Exceptions Floating-point exceptions: Invalid Operation Operation if ConditionPassed(cond) then if (Dd is a NaN) or (Dm is a NaN) then raise Invalid Operation exception FPSCR N flag = if (Dd < Dm) then else FPSCR Z flag = if (Dd == Dm) then else FPSCR C flag = if (Dd < Dm) then else FPSCR V flag = if (Dd and Dm compare as unordered) then else C4-12 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions 4.1.9 FCMPEZS 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cond 1 1 D 1 1 12 11 10 Fd 1 1 0 SBZ The FCMPEZS (Floating-point Compare (NaN Exceptions) with Zero, Single-precision) instruction compares a single-precision register with zero, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction) Syntax FCMPEZS{} where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the register which contains the first operand for the comparison The register number is encoded as Fd (top bits) and D (bottom bit) Architecture version All Exceptions Floating-point exceptions: Invalid Operation Operation if ConditionPassed(cond) then if (Sd is a NaN) then raise Invalid Operation exception FPSCR N flag = if (Sd < 0.0) then else FPSCR Z flag = if (Sd == 0.0) then else FPSCR C flag = if (Sd < 0.0) then else FPSCR V flag = if (Sd is a NaN) then else C4-18 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions Notes Vectors FCMPEZS always specifies a scalar operation, regardless of the LEN field of the FPSCR NaNs The IEEE 754 standard specifies that the result of a comparison is precisely one of or unordered If Dd is a NaN, it compares as unordered with zero, and all three of (Dd < 0.0), (Dd == 0.0) and (Dd > 0.0) are false This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1 FCMPEZS raises an Invalid Operation exception if the operand is any type of NaN, and is suitable for testing for =, and other predicates which raise an exception when the operands are unordered ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-19 VFP Instructions 4.1.10 FCMPS 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cond 1 1 D 1 0 12 11 10 Fd 1 0 M 0 Fm The FCMPS (Floating-point Compare, Single-precision) instruction compares two single-precision registers, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction) Syntax FCMPS{} , where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the register which contains the first operand for the comparison The register number is encoded as Fd (top bits) and D (bottom bit) Specifies the register which contains the second operand for the comparison The register number is encoded as Fm (top bits) and M (bottom bit) Architecture version All Exceptions Floating-point exceptions: Invalid Operation Operation if ConditionPassed(cond) then if (Sd is a signaling NaN) or (Sm is a signaling NaN) then raise Invalid Operation exception FPSCR N flag = if (Sd < Sm) then else FPSCR Z flag = if (Sd == Sm) then else FPSCR C flag = if (Sd < Sm) then else FPSCR V flag = if (Sd and Sm compare as unordered) then else C4-20 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions Notes Vectors FCMPS always specifies a scalar operation, regardless of the LEN field of the FPSCR NaNs The IEEE 754 standard specifies that the result of a comparison is precisely one of or unordered If either or both of Dd and Dm are NaNs, they are unordered, and all three of (Dd < Dm), (Dd == Dm) and (Dd > Dm) are false This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1 ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-21 VFP Instructions 4.1.11 FCMPZD 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cond 1 1 1 1 12 11 10 Dd 1 1 0 SBZ The FCMPZD (Floating-point Compare with Zero, Double-precision) instruction compares a double-precision register with zero, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction) Syntax FCMPZD{} where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the register which contains the first operand for the comparison Architecture version D variants only Exceptions Floating-point exceptions: Invalid Operation Operation if ConditionPassed(cond) then if (Dd is a signaling NaN) then raise Invalid Operation exception FPSCR N flag = if (Dd < 0.0) then else FPSCR Z flag = if (Dd == 0.0) then else FPSCR C flag = if (Dd < 0.0) then else FPSCR V flag = if (Dd is a NaN) then else C4-22 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions Notes Vectors FCMPZD always specifies a scalar operation, regardless of the LEN field of the FPSCR NaNs The IEEE 754 standard specifies that the result of a comparison is precisely one of or unordered If Dd is a NaN, it compares as unordered with zero, and all three of (Dd < 0.0), (Dd == 0.0) and (Dd > 0.0) are false This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1 FCMPZD only raises an Invalid Operation exception if the operand is a signaling NaN, and is suitable for testing for ==, !=, unorderedness, and other predicates which not raise an exception when the operands are unordered ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-23 VFP Instructions 4.1.12 FCMPZS 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cond 1 1 D 1 1 12 11 10 Fd 1 0 0 SBZ The FCMPZS (Floating-point Compare with Zero, Single-precision) instruction compares a single-precision register with zero, writing the result to the FPSCR flags (which is normally transferred to the ARM flags by a subsequent FMSTAT instruction) Syntax FCMPZS{} where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the register which contains the first operand for the comparison The register number is encoded as Fd (top bits) and D (bottom bit) Architecture version All Exceptions Floating-point exceptions: Invalid Operation Operation if ConditionPassed(cond) then if (Sd is a signaling NaN) then raise Invalid Operation exception FPSCR N flag = if (Sd < 0.0) then else FPSCR Z flag = if (Sd == 0.0) then else FPSCR C flag = if (Sd < 0.0) then else FPSCR V flag = if (Sd is a NaN) then else C4-24 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions Notes Vectors FCMPZS always specifies a scalar operation, regardless of the LEN field of the FPSCR NaNs The IEEE 754 standard specifies that the result of a comparison is precisely one of or unordered If Dd is a NaN, it compares as unordered with zero, and all three of (Dd < 0.0), (Dd == 0.0) and (Dd > 0.0) are false This results in the FPSCR flags being set as N=0, Z=0, C=1 and V=1 FCMPZS only raises an Invalid Operation exception if the operand is a signaling NaNs, and is suitable for testing for ==, !=, unorderedness, and other predicates which not raise an exception when the operands are unordered ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-25 VFP Instructions 4.1.13 FCPYD 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cond 1 1 1 0 0 12 11 10 Dd 1 1 0 Dm The FCPYD (Floating-point Copy, Double-precision) instruction copies one double-precision register to another double-precision register It can also perform a vector version of this operation Syntax FCPYD{} , where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the destination register Specifies the source register Architecture version D variants only Exceptions None Operation if ConditionPassed(cond) then for i = to vec_len-1 Dd[i] = Dm[i] C4-26 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions Notes Vectors When the LEN field of the FPSCR indicates scalar mode (vector length 1), FCPYD performs just one copy, and vec_len=1, Dd[0]=Dd, and Dm[0]=Dm When the LEN field indicates a vector mode (vector length > 1), FCPYD might perform more than one copy Addressing Mode - Double-precision vectors (monadic) on page C5-19 describes how FCYPD encodes the registers it uses and how vec_len, Dd[i], and Dm[i] are determined Flush-to-zero mode The FZ bit of the FPSCR does not affect the operand or result of this instruction Signaling NaNs To comply with the VFP architecture, FCPYD must not generate an exception even if the value in its source register is a signaling NaN This is a more stringent requirement than the one in the IEEE 754-1985 standard ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-27 VFP Instructions 4.1.14 FCPYS 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cond 1 1 D 1 0 0 12 11 10 Fd 1 0 M 0 Fm The FCPYS (Floating-point Copy, Single-precision) instruction copies one single-precision register to another single-precision register It can also perform a vector version of this operation Syntax FCPYS{} , where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the destination register The register number is encoded as Fd (top bits) and D (bottom bit) Specifies the source register The register number is encoded as Fm (top bits) and M (bottom bit) Architecture version All Exceptions None Operation if ConditionPassed(cond) then for i = to vec_len-1 Sd[i] = Sm[i] C4-28 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions Notes Vectors When the LEN field of the FPSCR indicates scalar mode (vector length 1), FCPYS performs just one copy, and vec_len=1, Sd[0]=Sd, and Sm[0]=Sm When the LEN field indicates a vector mode (vector length > 1), FCPYD might perform more than one copy Addressing Mode - Single-precision vectors (monadic) on page C5-14 describes how FCYPS encodes the registers it uses and how vec_len, Sd[i], and Sm[i] are determined Flush-to-zero mode The FZ bit of the FPSCR does not affect the operand or result of this instruction Signaling NaNs To comply with the VFP architecture, FCPYS must not generate an exception even if the value in its source register is a signaling NaN This is a more stringent requirement than the one in the IEEE 754-1985 standard ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-29 VFP Instructions 4.1.15 FCVTDS 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cond 1 1 1 1 12 11 10 Dd 1 1 M 0 Fm The FCVTDS (Floating-point Convert to Double-precision from Single-precision) instruction converts the value in a single-precision register to double precision and writes the result to a double-precision register Syntax FCVTDS{} , where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the destination register Specifies the source register The register number is encoded as Fm (top bits) and M (bottom bit) Architecture version D variants only Exceptions Floating-point exception: Invalid Operation Operation if ConditionPassed(cond) then Dd = ConvertSingleToDouble(Sm) Notes Vectors C4-30 FCVTDS always specifies a scalar operation, regardless of the LEN field of the FPSCR Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions 4.1.16 FCVTSD 31 28 27 26 25 24 23 22 21 20 19 18 17 16 15 cond 1 1 D 1 1 12 11 10 Fd 1 1 0 Dm The FCVTSD (Floating-point Convert to Single-precision from Double-precision) instruction converts the value in a double-precision register to single precision and writes the result to a single-precision register Syntax FCVTSD{} , where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the destination register The register number is encoded as Fd (top bits) and D (bottom bit) Specifies the source register Architecture version D variants only Exceptions Floating-point exceptions: Invalid Operation, Overflow, Underflow, Inexact Operation if ConditionPassed(cond) then Sd = ConvertDoubleToSingle(Dm) Notes Vectors FCVTSD always specifies a scalar operation, regardless of the LEN field of the FPSCR Rounding FCVTSD performs a fully-rounded conversion The rounding mode is determined by the FPSCR ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark C4-31 VFP Instructions 4.1.17 FDIVD 31 28 27 26 25 24 23 22 21 20 19 cond 1 1 0 16 15 Dn 12 11 10 Dd 1 0 0 Dm The FDIVD (Floating-point Divide, Double-precision) instruction divides one double-precision register by another double-precision register and writes the result to a third double-precision register It can also perform a vector version of this operation Syntax FDIVD{} , , where: Is the condition under which the instruction is executed The conditions are defined in The condition field on page A3-5 If is omitted, the AL (always) condition is used Specifies the destination register Specifies the register that contains the first operand for the division Specifies the register that contains the second operand for the division Architecture version D variants only Exceptions Floating-point exceptions: Invalid Operation, Division by Zero, Overflow, Underflow, Inexact Operation if ConditionPassed(cond) then for i = to vec_len-1 Dd[i] = Dn[i] / Dm[i] Usage Divisions take a large number of cycles on most implementations, and vector divisions take proportionately longer This can have a major effect on performance If a lot of divisions by the same number are wanted, the performance can usually be improved by using one division to calculate the number’s reciprocal, followed by a lot of multiplications by that reciprocal This slightly reduces the accuracy of the calculations, since they incur two rounding errors rather than one, but this is often an acceptable tradeoff Also see Interrupts on page C1-5 for a description of some implications for interrupt latency C4-32 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E ... bits) and M (bottom bit) Architecture version All Exceptions None Operation if ConditionPassed(cond) then for i = to vec_len-1 Sd[i] = abs(Sm[i]) C4-4 Copyright © 1996-2000 ARM Limited All rights... stringent requirement than the one in the Appendix to the IEEE 754-1985 standard ARM DDI 0100E Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com... Dn[i] + Dm[i] C4-6 Copyright © 1996-2000 ARM Limited All rights reserved Please purchase PDF Split-Merge on www.verypdf.com to remove this watermark ARM DDI 0100E VFP Instructions Notes Vectors