Exception Handling

h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 84 Chapter 7 Exception Handling Exception handling is classified into reset and interrupts and the interrupt function is indispensable for control using programs. It is almost always used when a timer is used and is also required for effective data input/output. To write the program you have made to the ROM for execution, you also need to understand how reset works. The concepts of reset and interrupts, however, are difficult to understand for beginners. Since practical uses are not mentioned in this chapter, you may not get a clear idea of them. The effects of interrupts are described in chapters relating to timers and serial interface. Here, you should fully understand the following key items: interrupt mask bit in the CCR, vector addresses and storage of the PC and CCR values. Note: Some IC signal names have bars over them to indicate negative logic. In the contents of the CD-ROM, however, no bar can be placed on them since they are written in HTML format. Still, bars are added to negative logic signals in figures included as images. The following are negative logic signals: 7.1 What Is Exception Handling? The CPU sometimes shows special operation called "exception handling". Exception handling refers to the operation that moves execution not to the next instruction but to another program after the current instruction is completely executed if any exception handling source is generated while the CPU is executing the main routine. The program to which execution is moved by exception handling is referred to as an "exception handling routine". h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 85 Figure 7.1: Exception Handling Operation Overview The H8/3048 has 42 types of exception handling sources, which are classified into one reset and 41 interrupts. Reset is mainly designed to start execution from a particular program after turning the microcomputer on. Interrupts are designed to move operation to an exception handling routine when an interrupt source is generated during program execution and return operation to the original program after the exception handling routine has been executed completely. Figure 7.2: Types of Exception Handling Sources Although what generates an exception handling source depends on the type, all types of exception handling routines employ the vector method. This method is designed to notify the CPU of the start address of an exception handling routine. The details are described in the following sections. 7.2 Reset 7.2.1 Reset Sources and Operation Reset is generated for two purposes. One is to start execution from a particular program after turning the microcomputer on. This program is called the "main routine". The other is to stop any program being executed by the CPU and resume processing from the same state when the power is turned on again. Figure 7.3 shows reset sources: h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 86 Figure 7.3: Reset Sources The CPU shows the operation described in Figure 7.4 after reset is generated. Figure 7.4: Reset Operation h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 87 After reset is generated, the CPU stops any program being executed, loads the reset vector to the PC and fetches an instruction from this address to execute it. In other words, reset generation always causes the main routine stored in the address indicated by the reset vector to be executed. After reset is generated to start main routine execution, processing cannot be returned to the original program to continue. Reset generation means that the microcomputer starts processing from the initial state. When the microcomputer starts operation, users are required to set the program to be executed first, namely the start address of the main routine, as the reset vector in the lower three addresses of the four-address area starting from address 0. This area is referred to as the "reset vector address". 7.2.2 Power-on Reset Although you can generate reset any time, there is one time that you must generate it. That is, when the microcomputer is turned on. Simply turning it on will not set all registers in the CPU to specific values and even the value in the PC cannot be determined. This means that the CPU cannot determine from which address the program should be executed when the microcomputer is turned on. Therefore, reset must be generated prior to any other processing after power-on. This is called "power-on reset". Figure 7.5: Overview of Reset Pin External Circuit and Voltage Waveform For reset to be generated properly at power-on, the electrical characteristics of the H8/3048 specify that the low-level voltage be kept at least 20ms before the high-level voltage applied to the reset pin. This allows the internal clock oscillating circuit to stabilize after power-on. On the contrary, to prevent reset generation in the microcomputer, you must externally apply the high-level voltage to the reset pin beforehand. Note that reset may be generated by a low-level noise only. To satisfy these two conditions, it is recommended that a circuit using a commercially available reset IC be designed around the reset pin. h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 88 Precautions on storing the reset vector For a program to operate properly after power-on reset, the reset vector must be stored in the reset vector addresses before the microcomputer is turned on. This means that the reset vector addresses must be in the ROM whose contents remain even after power-off. You must store the reset vector in this ROM. As shown in Figure 7.6, use the DATA.L assembler control instruction to store the reset vector. In this example, the main routine (symbol MAIN) is placed starting from the H'001000 address and the value of H'001000 indicated by the MAIN symbol is stored as the reset vector in the 4-address area between the H'000000 and H'000003 addresses. Figure 7.6: Description to Store the Reset Vector 7.3 Interrupts 7.3.1 Interrupt Overview The H8/3048 has 41 types of interrupts, which are exception handling routines with a variety of types. Any microcomputer-applied system must timely respond to processing requests which may be generated at any time such as signal inputs from many sensors and outputs to specific equipment. Although it is possible for one program to sequentially search for and respond to all processing requests, this results in long search time and slow response speed. To solve this problem, a mechanism is needed to allow a response program (interrupt handling routine) to be executed only when a processing request is issued. The CPU is provided with interrupts for this function. Interrupts are designed to respond to a processing request with a higher priority than the current program and move execution to it. h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 89 Figure 7.7: Interrupt Operation Let's take a microcomputer used in a beverage vending machine as an example. The microcomputer is generally required simply to execute a program to keep the product temperature at a certain level. Only when coins are dropped in, should interrupt operation be started to execute programs as interrupt handling routines to judge how many coins have been dropped in or which button has been pressed. After execution is completed, the microcomputer can return to the original temperature control program. 7.3.2 Interrupt Types Two conditions must be satisfied to allow an interrupt to be generated: one is that an interrupt request has been generated and the other is that an interrupt is enabled. Although the judgement of whether an interrupt request is generated or not depends on the interrupt type, event occurrence in the microcomputer hardware is generally regarded to be generation of an interrupt request. Interrupts are roughly classified into 41 types, which are further divided into external and internal interrupts based on the sources. For internal interrupts, requests are generated by the internal peripheral functions, which are described in the following chapters. In other words, interrupt requests are generated when something happens on the internal peripheral function hardware. Since internal interrupts are described in the following chapters, external interrupts only are explained here. Operation, however, is the same for both external and internal interrupts, which you should fully understand here. h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 90 Figure 7.8: External Interrupt Request Input Pins The H8/3048 has seven pins to input external interrupt requests in all and six of them are named "IRQ0" to "IRQ5". The remaining pin is named "NMI". In the case of external interrupts, a request is regarded to be generated when the low-level voltage is applied to one of these interrupt request input pins. To prevent an external interrupt request from being generated, apply the high-level voltage to these pins. For example, if the low-level voltage is applied to the IRQ3 input pin, an external interrupt request of the "IRQ3" type is regarded to be generated. If the interrupt is enabled at this time, the interrupt is generated to move execution to the IRQ3 interrupt handling routine. Accordingly, you can execute a program to handle requests only when required by creating an external circuit to apply the low-level voltage to a corresponding interrupt request input pin when a sensor has prepared data to be read by the microcomputer. Disabling/Enabling Interrupts As indicated by the above description saying "If the interrupt is enabled at this time", interrupt requests, irrespective of whether they are external or internal, are not necessarily accepted by the microcomputer. The following describes the interrupt mask bit in the CCR, which controls whether to accept interrupt requests or not. Figure 7.9: Interrupt Mask Bit h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 91 Whether to enable or disable interrupts is controlled by the most significant bit in the CCR (I bit), or the interrupt mask bit. This I bit can be set to 1 or 0 using an LDC instruction or others. When the I bit is 1, interrupts are masked, or disabled, and interrupt operation is not performed even if an interrupt request is generated. When the I bit is 0, interrupts are enabled and interrupt operation is performed if an interrupt request is generated. This I bit collectively disables or enables all external and internal interrupts excluding the NMI. The NMI is an acronym for non-maskable interrupt, an interrupt which cannot be disabled even if the I bit is set to 1. In addition, interrupts other than the NMI can be individually enabled or disabled by the respective bits. They are described in the next section. 7.3.3 IRQs (1) Electrical characteristics of IRQs Since external interrupts generate requests by externally inputting electrical signals to the interrupt request input pins, they must satisfy certain characteristics. This section describes the electrical characteristics of external interrupts specified for the H8/3048. In the case of the H8/3048, all operations are based on digital circuits synchronous with the system clock named "φ (phi)". Whether the high or low voltage is applied to the seven interrupt request input pins is judged based on the timing of the trailing edge of the system clock φ (phi). Accordingly, the setup time and hold time, which are inevitably specified for all clock synchronous digital IC input pins, are also specified for the H8/3048. Figure 7.10: Electrical Characteristics of External Interrupts h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 92 (2) Internal I/O registers of IRQs Next, you will learn about internal I/O registers of IRQs. Internal I/O registers collectively refer to registers for using various internal peripheral functions. Each register is placed at a specific address in the memory and given a specific name. This lesson contains many descriptions of various internal I/O registers. In the microcomputer, external interrupt operation is controlled by the internal peripheral function named "interrupt controller". Two internal I/O registers for using this interrupt controller are described below. First, the IRQ enable register (IER) is described, together with how to interpret the explanatory diagram. Figure 7.12: IRQ Enable Register (IER) Using bits 5 to 0 of the IRQ enable register (IER), you can enable or disable six IRQ interrupts individually. To enable the IRQ0 interrupt, for example, you should set the least significant IRQ0 enable bit (IRQ0E) to 1. As a matter of course, you should set the I bit in the CCR to 0 as well. Since all bits of this register are set to 0 by default, all IRQ interrupts are disabled without modification after resetting. To allow a specific IRQ interrupt, set the relevant bit of the IER to 1 using an instruction. Figure 7.13: IRQ Sense Control Register (ISCR) h t t p : / / r e s o u r c e . r e n e s a s . c o m Page 93 The other register relating to IRQ interrupts is the IRQ sense control register (ISCR). Using bits 5 to 0 of this register, you can set the sense level to low or the trailing edge for six IRQ interrupts individually. These two differ as follows. When it is set to the low level, the system assumes that interrupt requests are continuously generated while the low-level voltage is applied to an IRQ interrupt request input pin. When it is set to the trailing edge, on the other hand, the system assumes that an interrupt request is generated only when the low-level voltage is first applied to an IRQ interrupt request input pin and does not assume continuous generation even if the low- level voltage continues to be applied. Select a setting appropriate for your system. 7.3.4 Interrupt Operations (1) Shift to an interrupt handling routine Figure 7.14 shows three operations performed by the CPU when an interrupt is generated: Figure 7.14: Interrupt Operations [...]... correct type of exception handling sources in the H8/3048? (A) Reset only (B) Interrupts only (C) Reset and interrupts Answer: (C) The H8/3048 has both reset and interrupt exception handling routines 3 What is common to all exception handling routines? (A) Employs the vector method (B) Sets the I bit in the CCR to 0 (C) Initializes the internal I/O registers Answer: (A) (B) Exception handling sets the... a program? (A) The current instruction is interrupted for exception handling (B) Exception handling is performed after the current instruction is completed (C) Exception handling is performed after the program is completed Answer: (B) (A) disables the original program to properly continue even after execution is returned from the interrupt handling routine to the next instruction of the original program... the vector address? (A) Addresses between H'000000 and H'000003 in the memory space (B) Start address of an exception handling routine (C) Specific address area for storing the start address of an exception handling routine (D) Specific address area for storing the return address at exception handling generation Answer: (C) (A) refers to the vector address for reset only (B) refers to the vector http://resource.renesas.com... written Whether to set other exception handling vector addresses in the ROM or RAM depends on the system When using the microcomputer as an internal controller, however, other exception handling vector addresses are generally located in the same ROM as the reset vector addresses 7.5 Sample Interrupt Programs Let's take a look at some sample programs to perform IRQ0 interrupt handling after the H8/3048... these instructions properly to store and restore general-purpose registers 7.4 Vector List As described earlier, all exception handling routines employ the vector method to notify the CPU of the start address of the program to which execution is moved Table 7.1 shows the list of exception handling vector addresses: The vector addresses are located in the area between H'000000 (start address of the memory... of an interrupt handling routine and the RTS instruction at the end of a subroutine Also note that if an interrupt handling routine arbitrarily uses a generalpurpose register, the value in the register changes when execution is returned to the original program, causing the normal process to fail To prevent this from happening, develop a program so as to start processing in an interrupt handling routine... interrupt is generated You can determine how many IRQ0 interrupts have been generated by referring to the contents of the COUNTER address afterward http://resource.renesas.com Page 96 Table 7.1: H8/3048 Exception Handling Sources http://resource.renesas.com Page 97 C Language sample #include ; /* include embedded function */ /* Internal I/O register address define */ #define IER (*(volatile unsigned... routine, is executed The NMI interrupt, however, is always accepted irrespective of the I bit in the CCR (2) Return from an interrupt handling routine Figure 7.17: Restoration of the CCR and PC Values from the Stack You must specify the RTE instruction at the end of every interrupt handling routine and its execution enables processing to return to the original program to continue The RTE instruction works... moved to different interrupt handling routines according to the type of interrupt generated For the vector address of each interrupt, refer to Table 7.1 in the following section As the last operation after interrupt generation, the CCR sets the I bit in the CCR to 1 to disable (mask) interrupts This means that after an interrupt is generated to move execution to an interrupt handling routine, any other... the reset vector addresses 7.5 Sample Interrupt Programs Let's take a look at some sample programs to perform IRQ0 interrupt handling after the H8/3048 is turned on and reset Programs to generate exception handling routines require that the vectors be stored in the memory beforehand and that interrupts be enabled What all the programs shown below do is to increment the contents of the COUNTER address . signals: 7.1 What Is Exception Handling? The CPU sometimes shows special operation called " ;exception handling& quot;. Exception handling refers to the. is interrupted for exception handling. (B) Exception handling is performed after the current instruction is completed. (C) Exception handling is performed