Hand Off for the UHCI Host Controller

Hand Off for the UHCI Host Controller Section 5 of the Universal Host Controller Interface (UHCI) Design Guide, Revision 1.1 gives an example implementation of mouse and keyboard legacy support and describes one way to hand off control of the host controller between the BIOS and the UHCI host controller driver in the operating system. The key UHCI register used in the example is the legacy support register (LEGSUP). For implementers in a PCI device, the LEGSUP register is located at offset C0-C1h, in function 2 PCI configuration space. The Microsoft UHCI host controller driver also uses the LEGSUP register as the primary interface in implementing the handoff of the host controller between the operating system and the BIOS; the Microsoft host controller driver implementation logic is described in this section of the article. LEGSUP register structure. The LEGSUP register is a bitmap containing 16 bits. The meaning of each of the 16 bits is fully specified in Section 5 of the Universal Host Controller Interface (UHCI) Design Guide, Revision 1.1. A summary description is given in the following table so the reader can interpret the bitmap constant values used in later sections of this article without referring to the Design Guide. Table 1. LEGSUP register structure Bit Name Description 15 (R/WC) A20PTS 1 = A20GATE passthrough sequence has ended. 14 Reserved. 13 (R/W) USBPIRQDEN 1 = USB interrupt is routed to PIRQD (default). 0 = Not routed to PIRQD. This bit can be used to prevent the host controller from generating an interrupt. 12 (RO) USBIRQS 1 = USB IRQ is active. 11 (R/WC) TBY64W 1 = Write to port 64h has occurred. 10 (R/WC) TBY64R 1 = Read to port 64h has occurred. 9 (R/WC) TBY60W 1 = Write to port 60h has occurred. 8 (R/WC) TBY60R 1 = Read to port 60h has occurred. 7 (R/W) SMIEPTE 1 = Enable generation of an SMI when A20GATE passthrough sequence has ended. 0 = Disable (default). 6 (RO) PSS 1 = A20GATE passthrough sequence is currently in progress. 0 = Not executing (default). 5 (R/W) A20PTEN 1 = Enable A20GATE passthrough sequence. 0 = Disable (default). 4 (R/W) USBSMIEN 1 = Enable SMI# generation on USB IRQ. 0 = Disable (default). 3 (R/W) 64WEN 1 = Enable I/O Trap and SMI# generation of port 64h write. 0 = Disable (default). 2 (R/W) 64REN 1 = Enable I/O Trap and SMI# generation of port 64h read. 0 = Disable (default). 1 (R/W) 60WEN 1 = Enable I/O Trap and SMI# generation of port 60h write. 0 = Disable (default). 0 (R/W) 60REN 1 = Enable I/O Trap and SMI# generation of port 60h read. 0 = Disable (default). How the Microsoft host controller driver uses the LEGSUP register. The Microsoft UHCI host controller driver writes the following value to LEGSUP for normal HCD use: 0x2000. Note that this sets bit 13 and clears bit 4, which routes USB interrupts to PIRQD and disables SMI# generation on a USB IRQ event. The host controller driver sets bit 4 for BIOS/SMI use, which enables SMI# generation on a USB IRQ event. SOF MODIFY register. The SOF MODIFY register is a one-byte register that can be used to modify the value used to generate timing on the USB. (For more information, see section 2.1.6 of the Universal Host Controller Interface (UHCI) Design Guide, Revision 1.1.) Guidelines for modification of frame time are contained in Chapter 7 of the USB Specification. How the Microsoft host controller driver uses the SOF MODIFY register. When the Microsoft host controller driver takes control of the host controller from the BIOS, it always reads the value of the SOF MODIFY register value established by the BIOS and saves it in a per-device, per-host controller data structure. USB COMMAND (USBCMD) register structure. The USBCMD register is a bit- map containing 16 bits. The meaning of each of the 16 bits is fully specified in Section 2.1.1 of the Universal Host Controller Interface (UHCI) Design Guide, Revision 1.1. A summary description is given in the following table so the reader can, without referring to the Design Guide, interpret the CMDREG bits that are set and cleared in the pseudocode in later sections of this article. Table 2. USBCMD register structure Bit Name Description 15:8 Reserved. 7 (R/W) MAXP 1 = 64 bits. 0 = 32 bits. 6 (R/W) CF Host controller driver software sets this bit as the last action in its process of configuring the host controller; has no effect on the hardware. Provided only as a semaphore service for the software. 5 (R/W) SWDBG 1 = Debug mode. 0 = Normal mode. 4 (R/W) FGR 1 = host controller sends Global Resume signal on the USB. 3 (R/W) EGSM 1 = host controller enters Global Suspend mode. 2 (R/W) GRESET 1 = host controller sends Global Reset signal on the USB and then resets all its logic. 1 (R/W) HCRESET 1 = host controller resets its internal timers, counters, state machines, and so on to their initial values. 0 (R/W) RS 1 = Run (host controller proceeds with execution of the schedule). 0 = Stop (host controller completes current transaction and then halts). How the Microsoft host controller driver uses the USBCMD register. When it takes control of the host controller from the BIOS, the Microsoft host controller driver clears the RS bit to stop the host controller and clears the CF bit. USB STATUS (USBSTS) register structure. The USBSTS register is a bitmap containing 16 bits. The meaning of each of the 16 bits is fully specified in Section 2.1.2 of the Universal Host Controller Interface (UHCI) Design Guide, Revision 1.1. A summary description is given in the following table so the reader can, without referring to the Design Guide, interpret the CMDSTS bits that are set and cleared in the pseudocode in later sections of this article. Table 3. USBSTS register structure Bit Name Description 15:6 Reserved. 5 (R/WC) HcHalted Set to 1 by host controller when it is halted. 4 (R/WC) Host Controller Process Error Set to 1 by host controller when it encounters a consistency check error while processing a Transfer Descriptor. 3 (R/WC) Host System Error Set to 1 by host controller when a serious error occurs during a host system access. 2 (R/WC) Resume Detect Set to 1 by host controller when it receives a RESUME signal from a USB device. 1 (R/W) USB Error Interrupt Set to 1 by host controller when completion of a USB transaction results in an error condition. 0 (R/W) USBINT Set to 1 by host controller either when completion of a USB transaction causes an interrupt or when a short packet is detected. How the Microsoft host controller driver uses the USBSTS register. During the process of taking control of the host controller from the BIOS, the Microsoft host controller driver monitors the HcHalted bit to determine if and when the host controller is halted. Operating System Takes Control of the UHCI Host Controller When the host controller driver is loaded and running, it can determine whether the platform has a USB BIOS by the bits set in the LEGSUP register. A USB BIOS is a BIOS that contains code to: 1* Configure the host controller. 2* Enable a USB keyboard and mouse. 3* Set up the host controller scheduler. 4* Route USB keyboard and mouse input to the 8042 Keyboard Controller (KBC). When a USB BIOS boots, if it contains the code that does the functions listed above and has legacy keyboard support enabled, then it should always set bit 4 of the host controller LEGSUP register and make sure bit 13 is cleared. Conversely, when a BIOS boots that does not contain the code that does the above functions or when it contains the code but has legacy keyboard support disabled, the BIOS should always set bit 13 of the LEGSUP register and make sure bit 4 is cleared. This will ensure the appropriate interaction between the BIOS and the Windows UHCI host controller driver. The following pseudocode shows the structure and logic of the entire StopBIOS routine in the UHCI host controller. Get a pointer to the per-device, per-host controller data structure Read current value of SOF MODIFY register into data structure Read current value of USB COMMAND REGISTER into data structure Read current value of USB INTERRUPT ENABLE REGISTER into data structure Read upper 20 bits of FRAME LIST BASE ADDRESS REGISTER into data structure // Override SOF MODIFY value from BIOS with value in Registry, if there is one. If SOF MODIFY value is in the Registry Read SOF MODIFY value from Registry Save SOF MODIFY value read from Registry in data structure Endif // Prepare first host controller command. Read current value of USB COMMAND REGISTER Clear RS bit in the USB COMMAND REGISTER // Will stop host controller. Clear CF bit in the USB COMMAND REGISTER // Will signal BIOS that OS has control. Write new value to USB COMMAND REGISTER // Wait until host controller halts. While total time elapsed is less than one millisecond Write 0xFF to Interrupt Status Register // Clear all pending interrupts. If HcHalt bit in USB STATUS REGISTER is set Break // Host controller has halted. Endif Endwhile Read the current value of the LEGSUP register Save read value of LEGSUP register in data structure // If any bits in the bit pattern 0x00BF are set in read LEGSUP value, then the platform // BIOS has legacy keyboard support code and legacy keyboard support is enabled for // the platform. If ((LEGSUP value) AND (0x00BF))!= 0 then Set USBBIOS flag in data structure // Platform has USB BIOS. Clear SMI enable bit (bit 4) in read LEGSUP value Write new value to LEGSUP register Read current value of LEGSUP register Write 0x2000 to the LEGSUP register // Route USB interrupt to PIRQD and // disable SMI# interrupt generation. Endif Return(STATUS_SUCCESSFUL) BIOS Takes Control of the UHCI Host Controller The following pseudocode shows the structure and logic of the StartBIOS routine for the UHCI host controller. Note that whenever StartBIOS is executed, it can be assumed that StopBIOS has been executed earlier; all StartBIOS calls are conditional and performed only if the USBBIOS flag is set in the per-device, per- controller data structure maintained by the host controller driver. This means that a set of host controller register values the BIOS needs to take control of the host controller are saved in the same data structure. Get pointer to per-device, per-host controller data structure // Clear all pending interrupts. Write 0xFF to Interrupt Status Register // Restore host controller register values saved at last BIOS to operating system handoff. Write value from data structure to HC USB INTERRUPT ENABLE REGISTER Write value from data structure to HC FRAME LIST BASE ADDRESS REGISTER // Enable routing of USB keyboard and mouse interrupts to SMI#. Write value from data structure into HC LEGSUP register Read value of HC LEGSUP register into data structure Set USBSMIEN bit (bit 4) of LEGSUP register value in data structure Write new value from data structure into HC LEGSUP register // Start host controller schedule. Write value from data structure into HC COMMAND REGISTER Set RS bit of COMMAND REGISTER value in data structure Write new COMMAND REGISTER value to HC COMMAND REGISTER Return(STATUS_SUCCESSFUL) HID Draft #4 Compliance Note In the USB HID Device Class Definition for Human Interface Devices, Draft #4, the HID descriptor has been repositioned within the Configuration descriptor; the correct order is now Configuration/Interface/HID/Endpoint. The HID USB driver supplied with Windows 98 and Windows 2000 looks at the order of the descriptors within the Configuration descriptor to determine whether a device is Draft #4– compliant. If the driver sees a descriptor order of Interface/Endpoint/HID, it assumes this is an older device and sends all requests to the Endpoint. If it sees a descriptor order of Interface/HID/Endpoint, it assumes this is a Draft #4–compliant device and sends all requests to the Interface. If the value of bmRequestType is 82h, the HID descriptor is associated with the Endpoint descriptor, rather than with the Interface descriptor. To fix this, the developer must relocate the HID descriptor so that it sits after the Interface descriptor and before the Endpoint descriptor. The device firmware that handles the setup packet needs to look for a request type of 81h, rather than 82h. Finally, for devices with multiple interfaces, such as a keyboard with built-in mouse, the wIndex field must reflect the interface for which a Report descriptor is being requested. The Windows 95 OSR 2.1 USB class driver incorrectly assumes that the Endpoint descriptor immediately follows the Interface descriptor. A solution that works equally well on Windows 95 and Windows 98 is to clear everything out of the Configuration descriptor returned from the device except Configuration, Interface, and Endpoint descriptors before being passed to USB functions. A sample function that performs this task can be downloaded from the web site at www.microsoft.com/hwdev/driver/hid4.htm. References and Call to Action 5* OEMs should ensure that the BIOS they ship on all platforms with USB host controllers and USB connectors has the code that provides legacy keyboard and mouse support for USB keyboards and mice. The platform should have legacy keyboard support enabled. 6* BIOS vendor developers who write code that provides legacy support for USB keyboards and mice on Windows platforms should use program logic that works with the host controller driver code logic presented in this article. 7* For more information and related references, see: 8* OpenHCI: Open Host Controller Interface Specification for USB, Release 1.0a, available from www.microsoft.com/hwdev/specs/default.htm. 9* Intel information about USB, including the UHCI design guide for USB http://developer.intel.com/design/litcentr/ http://developer.intel.com/design/usb/. 10* USB Specification and USB Implementers Forum http://www.usb.org/developers/. 11* USB information on Microsoft Hardware Developers web site www.microsoft.com/hwdev/busbios/default.htm. For more information about SMM, see Chapter 20 in Pentium Processor User's Manual, Volume 3: Architecture and Programming Manual, 1994, which can be ordered from Intel by calling 1-800-548-4725. Send feedback to MSDN. Look here for MSDN Online resources. . to hand off control of the host controller between the BIOS and the UHCI host controller driver in the operating system. The key UHCI register used in the. space. The Microsoft UHCI host controller driver also uses the LEGSUP register as the primary interface in implementing the handoff of the host controller