Design of pipeline R2MDC FFT for implementation of MIMO OFDM transceivers using FPGA

In this paper, an area-efficient low power Fast Fourier Transform (FFT) processor is proposed for Multi Input Multi Output—Orthogonal Frequency Division Multiplexing (MIMO-OFDM) that consists of a modified architecture of radix-2 algorithm which is described as Radix-2 multipath delay commutation (R2MDC). Orthogonal frequencydivision multiplexing is a popular method for high-data-rate wireless transmission.

See discussions, stats, and author profiles for this publication at: https://www.researchgate.net/publication/290324049 Design of pipeline R2MDC FFT for implementation of MIMO OFDM transceivers using FPGA Article in Telecommunication Systems · November 2016 DOI: 10.1007/s11235-016-0136-8 CITATIONS READS 53 2 authors: Dr Kirubanandasarathy N Karthikeyan Kottaisamy Syed Ammal Engineering College ABB 28 PUBLICATIONS 21 CITATIONS 9 PUBLICATIONS 68 CITATIONS SEE PROFILE SEE PROFILE All content following this page was uploaded by Dr Kirubanandasarathy N on 04 May 2016 The user has requested enhancement of the downloaded file All in-text references underlined in blue are added to the original document and are linked to publications on ResearchGate, letting you access and read them immediately Telecommun Syst DOI 10.1007/s11235-016-0136-8 Design of pipeline R2MDC FFT for implementation of MIMO OFDM transceivers using FPGA N Kirubanandasarathy1 · K Karthikeyan1 © Springer Science+Business Media New York 2016 Abstract In this paper, an area-efficient low power Fast Fourier Transform (FFT) processor is proposed for Multi Input Multi Output—Orthogonal Frequency Division Multiplexing (MIMO-OFDM) that consists of a modified architecture of radix-2 algorithm which is described as Radix-2 multipath delay commutation (R2MDC) Orthogonal frequencydivision multiplexing is a popular method for high-data-rate wireless transmission OFDM may be combined with multiple antennas at both the access point and mobile terminal to increase diversity gain and/or Enhance system capacity on a time-varying multi path fading channel, resulting in a multiple-input multiple-output OFDM system This paper describes the design of R2MDC FFT for implementation of MIMO OFDM transceiver using FPGA targeted to future wireless LAN systems The proposed system is pipeline Radix 2multipath delay commutation FFT has been designed for MIMO OFDM The MIMO OFDM transceivers have been designed according to the proposed OFDM parameters A low-power efficient and full-pipeline architecture enables the real-time operations of MIMO OFDM transceivers The FPGA board has been developed to verify their circuit behavior and implementation of MIMO OFDM Transceivers Keywords Radix-2 multipath delay commutation · Frequency division multiplexing · Multi input multi output—orthogonal frequency division multiplexing · Inverse fast Fourier Transform · Fast Fourier Transform · Discrete Fourier Transform B N Kirubanandasarathy nksarathy@gmail.com K Karthikeyan sayalkarthik@yahoo.co.in Department of ECE, Syed Ammal Engineering College, Ramanathapuram, Tamilnadu, India Introduction Multiple input multiple output–Orthogonal frequency division multiplexing (MIMO-OFDM) has become a promising technique for future mobile multimedia communication system because of its robustness to frequency selective fading and its flexibility in handling multiple data rates [1,2] MIMO-OFDM is the efficient solution for transmitting and receiving the data over the long distance The sub-carrier frequency has been chosen in our proposed OFDM transceivers so that cross-talk between the sub-channels are eliminated, hence the inter carrier guard bands are not required The orthogonally allows for efficient modulator and demodulator implementation using the FFT algorithm OFDM Transceivers is popular for wideband communications today by way of low-cost MIMO OFDM Transceivers requires very accurate frequency synchronization between the receiver and they have their reduced the complexity In Transmitter; with frequency deviation, the sub-carriers shall no longer be orthogonal, causing inter-symbol interference (ISI) The proposed FFT Processor is based on radix-2 multipath delay commutation We compare this proposed architecture with existing radix and radix FFT and also give the design and implementation results of the proposed FFF processor About MIMO OFDM The general transceiver structure of MIMO OFDM is presented in Fig The system consists of N transmitter antennas and M receiver antennas Multiple antennas at both sides of receiver and transmitter can improve the spectral efficiency and reliability in multipath fading channels [3–5] According to [6], the cyclic prefix is assumed to be a longer than the channel delay spread The OFDM signal for each 123 N Kirubanandasarathy, K Karthikeyan Fig Architecture for MIMO-OFDM antenna is obtained by using IFFT and can be detected by fast Fourier transform (FFT) Each OFDM block of constellation symbols is transformed using an inverse fast Fourier transform (IFFT) and transmitted by the antenna for its corresponding stream The received signals at each antenna are similarly broken into blocks and processed using an FFT [7] Bolcskei et al have presented an OFDM based spatial multiplexing scheme, the data streams are first passed through OFDM modulators and then launched from the individual antennas In the receiver, the individual signals are passed through OFDM demodulators [8] A powerful improvement over conventional OFDM was the introductions of multicarrier code division multiplex (MC-CDM) OFDM by Kaiser in [9] In MC-CDM, rather than transmitting a single symbol on each subcarrier as in conventional OFDM, groups of symbols are multiplexed together by means of orthogonal spreading codes and simultaneously transmitted on a group of subcarriers [10] OFDM is a multi-carrier system where data bits are encoded to multiple sub-carriers Unlike single carrier systems, all the frequencies are sent simultaneously in time OFDM offers several advantages over single carrier system like better multipath effect immunity, simpler channel equalization and relaxed timing acquisition constraints But it is more susceptible to local frequency offset and radio frontend non-linearity The frequencies used in OFDM system are orthogonal Neighboring frequencies with overlapping spectrum can therefore be used This property is shown in the Fig 2, where A, B, C, D, and E orthogonal This results in efficient usage of BW The OFDM is therefore able to provide higher data rate for the same BW[11] 123 Proposed pipelined architecture for MIMO-OFDM The radix-2 multipath delay commutation (R2MDC) is one of the commutated architectures of radix-2 FFT algorithm which is used to commutate the values as fast as possible in order to process the values and to commutate the FFT inputs, the architecture shown in the Fig consists of different blocks which must be used in the R2MDC Kirubanandasarathy and Karthikeyan [12] have investigated Radix-2 pipelined streaming FFT block, which is used in the baseline MIMO-OFDM system But we use radix-2 multipath delay commutation in the proposed system One of the most straightforward approaches for pipelined implementation of radix-2 FFT algorithm is Radix-2 Multipath Delay Commutator (R2MDC) architecture Figure shows the radix-2 multipath delay commutation architecture with butterfly II structure It is the simplest way to rearrange data for the FFT/IFFT algorithm, the input data sequence are broken into two parallel data stream flowing forward, with correct distance between data elements entering the butter- Fig OFDM wave Design of pipeline R2MDC FFT for implementation of MIMO OFDM transceivers using FPGA Fig Proposed FFT architecture block Fig Radix-2 multipath delay commutation architecture Fig a BF I structure, b BF II structure fly scheduled by proper delays The 8-point FFT in R2MDC architecture is shown in Fig At each stage of this architecture half of the data flow is delayed via the memory (Register) and processed with the second half data stream The A input comes from the previous component twiddle factor multipliers (TFM) The B output is fed to the next component, normally BFII In first cycles, multiplexors direct the input data to the feedback registers until they are filled (position “0”) On next cycles, the multiplexors select the output of the adders/sub tractors (position “1”), the butterfly computes a 2-point DFT with incoming data and the data stored in the feedback registers The detailed structure of BFI is shown in Fig.5a 123 N Kirubanandasarathy, K Karthikeyan Fig FPGA implementation of OFDM Transceiver Fig OFDM transceiver simulation wave form The B input comes from the previous component, BFI The Z output is fed to the next component, normally TFM In first cycles, multiplexors direct the input data to the feedback registers until they are filled (position “0”) On next cycles, the multiplexors select the output of the adders/sub tractors (position “1”), the butterfly computes a 2-point DFT with incoming data and the data stored in the feedback registers The multiplication by –j involves real-imaginary swapping and sign inversion The real-imaginary swapping is handled by the multiplexors MUX in efficiently and the sign inversion is handled by switching the adding-subtracting operations by mean of MUX When there is a need for multiplication by -j, all multiplexors switches to position “1”, the real-imaginary data are swapped and the adding-subtracting operations are switched The architecture of BFI and BFII supporting two receive chains is shown in Fig 5a, b In BFI structure the sample routing MUXs and DEMUXs at the input and output of the BF_RAMs are controlled based on c2 and c3 control signals 123 while the computation unit is controlled by c1 control signal The control signals are issued by the BFI controller Depending on the programming of number of receive chains the extra BF_RAMs are enabled WiMAX supports 1Rx and 2Rx, LTE supports 1Rx, 2Rx and 4Rx Based on the requirement extra buffers can be extended to the existing BF structure The adders and substractors in BFI and BFII are fullypipelined and followed by divide-by-2 and rounding The divide-by-2 is used The algorithm used here is to commutate the radix-2 algorithm in the IFFT architecture and to replace by R2MDC architecture in order to get a low area than the existing system FPGA implementation of MIMO OFDM transceiver The applications like signal processing and telecommunication require FFT implementations which can perform with Design of pipeline R2MDC FFT for implementation of MIMO OFDM transceivers using FPGA Table Comparison results of proposed R2mdc IFFT architecture with existing radix-2 and radix-4 architecture Fig R2MDC FFT output implemetation in the FPGA Altera cyclone II DE2 development board less latency computations and small in size while exhibiting less power consumption These computational tasks are executed either by a single, high frequency embedded processor or by using an Application Specific Integrated Circuit (ASIC) Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASIC) provide different values to designers, and they must be carefully evaluated before Methods Slices Luts Power (W) R2MDC FFT 198 152 1.175 Radix-2 FFT 320 432 2.179 Radix-4 FFT 296 148 2.112 choosing any one over the other FPGA has been suggested as an enabling technology [13] for the hardware platform as they offer the potential of hardware-like performance coupled with software-like programmability [14] The register transfer VHDL net list of the OFDM Transceiver, which is optimized for low power consumption and ASIC implementation, is used as basic net list for mapping on a Xilinx FPGA as shown in Fig The DCM installs a zero phase delay between the internal and external clock and this allows using a FIFO interface operating on the clock edges to transfer transmit data and received data The FPGA implementation is optimized for power consumption by disabling the main internal clock when a functional unit is not operational This derived clock is the output signal of a buffered Fig RTL schematic of R2MDC FFT 123 N Kirubanandasarathy, K Karthikeyan Fig 10 Comparison results of proposed R2MDC IFFT architecture with existing radix-2 and radix-4 architecture AND gate with the main internal units This was the case in the equalizer where additional pipeline registers are added in the divider and in the data path of described above, delay between each butterfly board currently enables base band transmission via ADCs and DACs as shown Fig The FPGA board uses transmitter, receiver, and Viterbi decoder functions implemented in the Xilinx FPGA We added interpolator, decimator, random signal generator, and PC interface The interpolator and decimator require 100MHz clock frequency and the other modules operate at the half clock speed This FPGA with PC interface is used for displaying Bit Error Rate (BER) and Packet Error Rate (PER) results and controlling the transceiver We intend to execute data transmission experiments in both base band and pass band channels The simulation results for R2MDC FFT algorithms have been tested practically by implementing in the Altera DE2 FPGA development board The Quartus-II tool is used to download the design in to FPGA development board In the FPGA board, the reset signal input is connected to the rightmost switch For the set binary inputs at the remaining switches, after the process in the FPGA, the outputs are seen in LED displays in the board These FPGA outputs can also be verified with simulation results obtained using MODELSIM The FPGA board has been developed to verify their circuit behavior and implementation of MIMO OFDM Transceivers The below simulation diagram is for R2MDC as shown in Fig The reset value is high and after some time period the value is low While in reset is high the input value does not taken into the process The output value is occurred when the reset is low FPGA Altera cyclone II DE2 development board to illustrate the implementation of R2MDC FFT is as shown in Fig 123 The register Transfer Logic schematic for R2MDC FFT that is targeted to mapped on FPGA Altera cyclone II DE-2 is shown in Fig Results The prime objective is to construct a FFT in order to have low power consumption and lesser area The parameters (i) power consumption (ii) Area occupancy were given due consideration for comparing the proposed FFT with other FFTs We have designed all coding using Hardware Description Language (HDL) To get power, and area report, we use Xilinx ISE Design Suite 10.1 as synthesis tool and Model-Sim 6.3c for simulation The comparison of Radix-2 FFT and Radix4 with Proposed R2MDC FFT is shown in the Table and Fig 10.The Proposed FFT gives better result than Radix-2 FFT and Radix-4 FFT in terms of area and power consumption as shown in the Table1 and Fig 10 Conclusion We presented a R2MDC pipeline FFT as MIMO OFDM system with a 100-MHz bandwidth, which is an area-efficient low power FFT processor for MIMO-OFDM transceivers implementation using FPGA The transceiver uses fullpipelined processing and provides operations at minimum clock frequency The performance of various FFT such as Radix-2, Radix-4 and proposed R2MDC were carried out and their performance were analyzed with respect to the number of CLB slices, LUTs and Power consumption We demonstrated transceiver architecture suitable for the advanced OFDM system In this paper, we conclude that the proposed Design of pipeline R2MDC FFT for implementation of MIMO OFDM transceivers using FPGA R2MDC architecture gives a lower area and less power than the existing radix-2 and radix-4 algorithm architecture The proposed architecture shows that it can be used for low power applications such as MIMO-OFDM transceiver References Sampath, H., Talwar, S., Tellado, J., Erceg, V., & Paulraj, A (2002) A fourth generation MIMO-OFDM broadband wireless system: design performance, and field trial results IEEE Communications Magazine, 40(9), 143–149 Zelst, A., & Schenk, T (2004) Implementation of a MIMO OFDM-based wireless LAN system IEEE Transactions on Signal Processing, 52(2), 483–494 Heath, R, Jr, & Paulraj, A (2005) Switching between diversity and multiplexing in MIMO systems IEEE Transactions on Communications, 53(6), 962–968 Forenza, A., Pandharipande, A., Kim, H., & Heath, R W, Jr (2005) Adaptive MIMO transmission scheme: exploiting the spatial selectivity of wireless channels In: Proceedings of the IEEE VTC-spring (Vol 5, pp 3188–3192) Wei, Y R., & Wang, M Z (2006) A practical transmit antenna selection scheme with adaptive modulation for spatial multiplexing MIMO systems In IEEE intl conf on inf & commun tech., ICTTA’06, April 2006 Syria IEEE Transactions on Information Theory, 2, 2119–2124 Kirubanandasarathy, N., Karthikeyan, K & Thirunadanasikamani, K (2010) VLSI design of mixed radix FFT for MIMO OFDM in the wireless communication In: Proceedings of the IEEE International conference on communication computing control technologies (pp 98–102), October 7–9, 2010, Ramanathapuram, India Blum, R S., Li, Y G., Winters, J H., & Yan, Q (2001) Improved space time coding for MIMO-OFDM wireless communications IEEE Transactions on Communications, 49(11), 1873–1878 Bolcskei, H., Gesbert, D., & Paulraj, A J (2002) On the capacity of OFDM-based spatial multiplexing systems IEEE Transactions on Communication, 50(2), 225–234 Kaiser, S (2002) OFDM code-division multiplexing in fading channels IEEE Transactions on Communication, 50, 1266–1273 10 Femenias, Guilleum, & Riera-Palou, Felip (2008) Enhancing IEEE 802.11n WLANs using group-orthogonal code-division multiplex Telecommunication Systems (TSMJ), 38(1–2), 37 11 Kirubanandasarathy, N., & Karthikeyan, K (2013) VLSI Design of Pipelined R2MDC FFT for MIMO OFDM transceivers Journal of Applied Sciences (JAS), Science Alert Publications, 13(1), 197– 200 12 Kirubanandasarathy, N & Karthikeyan, K (2012) VLSI Design and Implementation of MIMO OFDM system for wireless communication European Journal of Scientific Research (EJSR), ISSN 1450-216X, 73(2), 269–277 13 Tuttlbee, W.H Software defined radio: Enabling technologies Wiley ISBN 0470843187 14 Coulton, P & Carline, D (2004) An SDR inspired design for the FPGA implementation of 802.11a baseband system In Proceedings of the IEEE international symposium on consumer electronics (pp 470–475), September 1–3, Reading, UK N Kirubanandasarathy received the B Eng degree in Electrical and Electronics Engineering from Madurai Kamaraj University, Madurai, India, in 2002, the M Eng Degree in Applied Electronics from Anna University, Chennai, India in 2004 He has completed Ph.D in ECE from St Peter’s Institute of Higher Education and Research, Avadi, Chennai, Tamilnadu, India in 2013 He is currently working as an professor in Syed Ammal Engineering college, Ramanathapuram, Tamilnadu, India and Pursuing the His fields of interest include VLSI and Communication system K Karthikeyan received the B Eng degree in Electrical and Electronics Engineering from Madurai Kamaraj University, Madurai, India, in 2002, the M Eng degree in Power systems from Anna University, Chennai, India, in 2004, and the Ph.D degree from Indian Institute of Technology Madras, Chennai, India, in 2008 Currently, he is Professor in the Department of Electronics and Communication Engineering of Syed Ammal Engineering College, Ramanathapuram, Tamilnadu, India His fields of interest include Power quality, Power electronics applications in Power system and VLSI Design 123 View publication stats ... architecture suitable for the advanced OFDM system In this paper, we conclude that the proposed Design of pipeline R2MDC FFT for implementation of MIMO OFDM transceivers using FPGA R2MDC architecture... system FPGA implementation of MIMO OFDM transceiver The applications like signal processing and telecommunication require FFT implementations which can perform with Design of pipeline R2MDC FFT for. .. multiple-output OFDM system This paper describes the design of R2MDC FFT for implementation of MIMO OFDM transceiver using FPGA targeted to future wireless LAN systems The proposed system is pipeline