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University  of  Washington   Roadmap   C:   Java:   car *c = malloc(sizeof(car)); c->miles = 100; c->gals = 17; float mpg = get_mpg(c); free(c); Car c = new Car(); c.setMiles(100); c.setGals(17); float mpg = c.getMPG(); Assembly   language:   Machine   code:   get_mpg: pushq movq popq ret %rbp %rsp, %rbp %rbp OS:   0111010000011000 100011010000010000000010 1000100111000010 110000011111101000011111 Computer   system:   Caches   Memory  &  data   Integers  &  floats   Machine  code  &  C   x86  assembly   Procedures  &  stacks   Arrays  &  structs   Memory  &  caches   Processes   Virtual  memory   Memory  allocaIon   Java  vs  C   University  of  Washington   SecIon  7:  Memory  and  Caches   ¢  ¢  ¢  ¢  ¢  Cache  basics   Principle  of  locality   Memory  hierarchies   Cache  organizaIon   Program  opImizaIons  that  consider  caches     Caches   University  of  Washington   How  does  execuIon  Ime  grow  with  SIZE?   int array[SIZE]; int A = 0; for (int i = ; i < 200000 ; ++ i) { for (int j = ; j < SIZE ; ++ j) { A += array[j]; } TIME } Plot Caches   SIZE University  of  Washington   Time   Actual  Data   SIZE   Caches   University  of  Washington   Problem:  Processor-­‐Memory  BoVleneck   Processor  performance   doubled  about     every  18  months   CPU   Bus  bandwidth   evolved  much  slower   Reg   Core  2  Duo:   Can  process  at  least   256  Bytes/cycle   Main   Memory   Core  2  Duo:   Bandwidth    Bytes/cycle   Latency   100  cycles   Problem:  lots  of  wai4ng  on  memory   Caches   University  of  Washington   Problem:  Processor-­‐Memory  BoVleneck   Processor  performance   doubled  about     every  18  months   CPU   Reg   Core  2  Duo:   Can  process  at  least   256  Bytes/cycle   Bus  bandwidth   evolved  much  slower   Cache   Core  2  Duo:   Bandwidth    Bytes/cycle   Latency   100  cycles   Solu4on:  caches   Caches   Main   Memory   University  of  Washington   Cache   ¢  ¢  English  definiIon:  a  hidden  storage  space  for  provisions,   weapons,  and/or  treasures     CSE  definiIon:  computer  memory  with  short  access  Ime  used   for  the  storage  of  frequently  or  recently  used  instrucIons  or   data  (i-­‐cache  and  d-­‐cache)     more  generally,     used  to  opImize  data  transfers  between  system  elements   with  different  characterisIcs  (network  interface  cache,  I/O   cache,  etc.)   Caches   University  of  Washington   General  Cache  Mechanics   Cache       14     Smaller,  faster,  more  expensive   memory  caches  a  subset  of   the  blocks   Data  is  copied  in  block-­‐sized   transfer  units   Memory                       10   11   12   13   14   15   Caches   Larger,  slower,  cheaper  memory   viewed  as  parIIoned  into  “blocks”   University  of  Washington   General  Cache  Concepts:  Hit   Request:  14   Cache       14     Memory                       10   11   12   13   14   15   Caches   Data  in  block  b  is  needed   Block  b  is  in  cache:   Hit!   University  of  Washington   General  Cache  Concepts:  Miss   Request:  12   Cache         12   Request:  12   12   Memory   14                       10   11   12   13   14   15   Caches   Data  in  block  b  is  needed   Block  b  is  not  in  cache:   Miss!   Block  b  is  fetched  from   memory   Block  b  is  stored  in  cache   • Placement  policy:   determines  where  b  goes   • Replacement  policy:   determines  which  block   gets  evicted  (vicAm)   University  of  Washington   Not  to  forget…   CPU A little of super fast memory (cache$) Lots of slower Mem Caches   ...  Memory  and  Caches   ¢  ¢  ¢  ¢  ¢  Cache ? ?basics   Principle  of  locality   Memory  hierarchies   Cache  organizaIon   Program  opImizaIons  that  consider  caches     Caches   University... evolved  much  slower   Cache   Core  2  Duo:   Bandwidth    Bytes/cycle   Latency   100  cycles   Solu4on:  caches   Caches   Main   Memory   University  of  Washington   Cache   ¢  ¢  English...  (i-­? ?cache  and  d-­? ?cache)     more  generally,     used  to  opImize  data  transfers  between  system  elements   with  different  characterisIcs  (network  interface ? ?cache,  I/O   cache,

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