Wiley mobile 3d graphics soc from algorithm to chip 2010 RETAiL EBook

MOBILE 3D GRAPHICS SoC From Algorithm to Chip Jeong-Ho Woo Korea Advanced Institute of Science and Technology, Republic of Korea Ju-Ho Sohn LG Electronics Institute of Technology, Republic of Korea Byeong-Gyu Nam Samsung Electronics, Republic of Korea Hoi-Jun Yoo Korea Advanced Institute of Science and Technology, Republic of Korea MOBILE 3D GRAPHICS SoC MOBILE 3D GRAPHICS SoC From Algorithm to Chip Jeong-Ho Woo Korea Advanced Institute of Science and Technology, Republic of Korea Ju-Ho Sohn LG Electronics Institute of Technology, Republic of Korea Byeong-Gyu Nam Samsung Electronics, Republic of Korea Hoi-Jun Yoo Korea Advanced Institute of Science and Technology, Republic of Korea Copyright Ó 2010 John Wiley & Sons (Asia) Pte Ltd, Clementi Loop, # 02-01, Singapore 129809 Visit our Home Page on www.wiley.com All Rights Reserved No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning, or otherwise, except as expressly permitted by law, without either the prior written permission of the Publisher, or authorization through payment of the appropriate photocopy fee to the Copyright Clearance Center Requests for permission should be addressed to the Publisher, John Wiley & Sons (Asia) Pte Ltd, Clementi Loop, #02-01, Singapore 129809, tel: 65-64632400, fax: 65-64646912, email: enquiry@wiley.com Designations used by companies to distinguish their products are often claimed as trademarks All brand names and product names used in this book are trade names, service marks, trademarks or registered trademarks of their respective owners The Publisher is not associated with any product or vendor mentioned in this book All trademarks referred to in the text of this publication are the property of their respective owners This publication is designed to provide accurate and authoritative information in regard to the subject matter covered It is sold on the understanding that the Publisher is not engaged in rendering professional services If professional advice or other expert assistance is required, the services of a competent professional should be sought Other Wiley Editorial Offices John Wiley & Sons, Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, UK John Wiley & Sons Inc., 111 River Street, Hoboken, NJ 07030, USA Jossey-Bass, 989 Market Street, San Francisco, CA 94103-1741, USA Wiley-VCH Verlag GmbH, Boschstrasse 12, D-69469 Weinheim, Germany John Wiley & Sons Australia Ltd, 42 McDougall Street, Milton, Queensland 4064, Australia John Wiley & Sons Canada Ltd, 5353 Dundas Street West, Suite 400, Toronto, ONT, M9B 6H8, Canada Wiley also publishes its books in a variety of electronic formats Some content that appears in print may not be available in electronic books Library of Congress Cataloging-in-Publication Data Mobile 3D graphics SoC : from algorithm to chip / Jeong-Ho Woo [et al.] p cm Includes index ISBN 978-0-470-82377-4 (cloth) Computer graphics Mobile computing Systems on a chip Three dimensional display systems I Woo, Jeong-Ho T385.M62193 2010 621.3815–dc22 2009049311 ISBN 978-0-470-82377-4 (HB) Typeset in 10/12pt Times by Thomson Digital, Noida, India Printed and bound in Singapore by Markono Print Media Pte Ltd, Singapore This book is printed on acid-free paper responsibly manufactured from sustainable forestry in which at least two trees are planted for each one used for paper production Contents Preface ix Introduction 1.1 Mobile 3D Graphics 1.2 Mobile Devices and Design Challenges 1.2.1 Mobile Computing Power 1.2.2 Mobile Display Devices 1.2.3 Design Challenges 1.3 Introduction to SoC Design 1.4 About this Book 1 3 5 Application Platform 2.1 SoC Design Paradigms 2.1.1 Platform and Set-based Design 2.1.2 Modeling: Memory and Operations 2.2 System Architecture 2.2.1 Reference Machine and API 2.2.2 Communication Architecture Design 2.2.3 System Analysis 2.3 Low-power SoC Design 2.3.1 CMOS Circuit-level Low-power Design 2.3.2 Architecture-level Low-power Design 2.3.3 System-level Low-power Design 2.4 Network-on-Chip based SoC 2.4.1 Network-on-Chip Basics 2.4.2 NoC Design Considerations 2.4.3 Case Studies of Chip Implementation 9 14 18 18 22 25 27 27 27 28 28 29 41 48 Introduction to 3D Graphics 3.1 The 3D Graphics Pipeline 3.1.1 The Application Stage 3.1.2 The Geometry Stage 3.1.3 The Rendering Stage 67 68 68 68 74 Contents vi 3.2 Programmable 3D Graphics 3.2.1 Programmable Graphics Pipeline 3.2.2 Shader Models 78 78 81 Mobile 3D Graphics 4.1 Principles of Mobile 3D Graphics 4.1.1 Application Challenges 4.1.2 Design Principles 4.2 Mobile 3D Graphics APIs 4.2.1 KAIST MobileGL 4.2.2 Khronos OpenGL-ES 4.2.3 Microsoft’s Direct3D-Mobile 4.3 Summary and Future Directions 85 85 86 87 91 91 93 95 96 Mobile 3D Graphics SoC 5.1 Low-power Rendering Processor 5.1.1 Early Depth Test 5.1.2 Logarithmic Datapaths 5.1.3 Low-power Texture Unit 5.1.4 Tile-based Rendering 5.1.5 Texture Compression 5.1.6 Texture Filtering and Anti-aliasing 5.2 Low-power Shader 5.2.1 Vertex Cache 5.2.2 Low-power Register File 5.2.3 Mobile Unified Shader 99 100 101 102 104 106 107 109 110 110 111 113 Real Chip Implementations 6.1 KAIST RAMP Architecture 6.1.1 RAMP-IV 6.1.2 RAMP-V 6.1.3 RAMP-VI 6.1.4 RAMP-VII 6.2 Industry Architecture 6.2.1 nVidia Mobile GPU – SC10 and Tegra 6.2.2 Sony PSP 6.2.3 Imagination Technology MBX/SGX 119 119 120 123 127 132 139 139 143 144 7.1 7.2 7.3 7.4 7.5 149 149 150 150 151 154 154 156 Low-power Rasterizer Design Target System Architecture Summary of Performance and Features Block Diagram of the Rasterizer Instruction Set Architecture (ISA) Detailed Design with Register Transfer Level Code 7.5.1 Rasterization Top Block 7.5.2 Pipeline Architecture Contents 8.1 8.2 8.3 vii 7.5.3 Main Controller Design 7.5.4 Rasterization Core Unit 156 158 The Future of Mobile 3D Graphics Game and Mapping Applications Involving Networking Moves Towards More User-centered Applications Final Remarks 295 295 296 297 Appendix Verilog HDL Design A.1 Introduction to Verilog Design A.2 Design Level A.2.1 Behavior Level A.2.2 Register Transfer Level A.2.3 Gate Level A.3 Design Flow A.3.1 Specification A.3.2 High-level Design A.3.3 Low-level Design A.3.4 RTL Coding A.3.5 Simulation A.3.6 Synthesis A.3.7 Placement and Routing A.4 Verilog Syntax A.4.1 Modules A.4.2 Logic Values and Numbers A.4.3 Data Types A.4.4 Operators A.4.5 Assignment A.4.6 Ports and Connections A.4.7 Expressions A.4.8 Instantiation A.4.9 Miscellaneous A.5 Example of Four-bit Adder with Zero Detection A.6 Synthesis Scripts 299 299 300 300 300 300 301 302 302 303 303 304 304 305 305 306 307 308 309 311 312 312 314 316 318 320 Glossaries 323 Index 325 316 Mobile 3D Graphics SoC //can add or remove ports of the sub-blocks, which is //really helpful for debugging DFF DFF0(.Clk (Clk), reset (reset), ena (ena), D (D[3]), Q (Q[3])); DFF DFF1(.Clk (Clk), reset (reset), ena (ena), D (D[2]), Q (Q[2])); DFF DFF2(.Clk (Clk), reset (reset), ena (ena), D (D[1]), Q (Q[1])); DFF DFF3(.Clk (Clk), reset (reset), ena (ena), D (D[0]), Q (Q[0])); endmodule A.4.9 Miscellaneous Include Directive Like the C language’s #include, Verilog supports an include directive This is used to include other Verilog code or library file within the current Verilog code The syntax of the include directive is shown below: ‘include ‘‘datapath.v’’ //Datapath.v includes adder module, multiplier, divider modules //Then you can use those modules when you declare the include directive module processor(clk, inputs, output); input clk; input inputs; output outputs; //Divider and multiplier are described in datapath.v divider proc_div(.input(input), output(output)); multiplier proc_mul(.input(input), output(output)); endmodule Define Statement The “define” statement is a kind of complier command to transpose a text When you use a certain value recursively, the “define” statement can help you //Do not write semicolons in define statements //Once you have declared a define statement,you can use the text in any modules Verilog HDL Design 317 //You can use these defined texts in other files if you include this file ‘define WISA_RSHA 6’b1000_00 ‘define WISA_RTEX 6’b1000_01 ‘define WISA_RDON 6’b1000_10 ‘define WISA_TMOD 6’b0100_01 ‘define WISA_MBAS 6’b0010_00 ‘define WISA_RCLR 6’b0010_01 module decode(inputs, outputs); input inputs; output outputs; //Command decoder always @(ID1data) begin case(ID1data[123:118]) //In compile time, these texts are converted into defined signals ‘WISA_RSHA : ID1ctrl_OP