06 programming timer and counter instructions Training PLC Allen Bradley

DAY SESSION 6-1 LADDER LOGIC PROGRAMMING – TIMER & COUNTER Ladder Logic Programming – Timer & Counter – 10 December 2010 OBJECTIVES Be able to • Describe the function of an on-delay timer • Describe the function of an off-delay time • Describe the instances in which one would use a retentive timer • Describe the function of an up-counter • Describe the function of a down-counter • Describe the instances in which one would use an up- versus a down-counter 6-2 • Define preset value, accumulative value, and timer or counter address Ladder Logic Programming – Timer & Counter – 10 December 2010 SUB-WINDOW : TIMER / COUNTER Timer is used to delay turning on or off output for maximum 9.1 hours 6-3 Counter is used to count up and down over a range of -32,768 to +32,768 Ladder Logic Programming – Timer & Counter – 10 December 2010 TIMER INSTRUCTIONS • Timer On Delay (TON) • Timer Off Delay (TOF) 6-4 • Retentive Timer On (RTO) Ladder Logic Programming – Timer & Counter – 10 December 2010 TIMER ON DELAY (TON) TON Timer On Delay Timer C5:0 Time Base Preset Accum EN DN Use TON instruction to turn an output on after the timer has been on for a preset time interval 6-5 Status bit: Ladder Logic Programming – Timer & Counter – 10 December 2010 TON OPERATION The TON instruction starts accumulating time when the rung goes true, and continues until one of the following happen: The rung goes false The accumulated value equals its preset value A reset instruction resets the timer The processor resets the accumulated value when the rung condition go false, regardless of whether the timer timed out or not 6-6 • • • • Ladder Logic Programming – Timer & Counter – 10 December 2010 6-7 TON TIMING DIAGRAM Ladder Logic Programming – Timer & Counter – 10 December 2010 TON STATUS BITS Is Set When: Indicates: And Remains Set Until One of the Following Occurs: Timer Enabled EN (bit 15) the rung goes true that timer is enabled • the rung goes false • a reset instruction reset the timer Timer Timing Bit TT (bit 14) the rung goes true that a timing operation is in progress • the rung goes false • the DN bit is set (.ACC = PRE) • a reset instruction reset the timer Timer Done Bit DN (bit 13) the accumulated value is equal to the preset value that a timing operation is complete • the rung goes false • a reset instruction resets the timer 6-8 This Bit: Ladder Logic Programming – Timer & Counter – 10 December 2010 TIMER ON LADDER DIAGRAM EXAMPLE When the input condition is true, the processor increments the accumulated value of Timer_1 in milisecond increment Sets the output while the timer is timing 6-9 Sets the output when the timer is done timing Ladder Logic Programming – Timer & Counter – 10 December 2010 TIMER OFF DELAY (TOF) Use TOF instruction to turn an output off after the timer has been off for a preset time interval 6-10 Status bit: Ladder Logic Programming – Timer & Counter – 10 December 2010 6-18 RTO TIMING DIAGRAM Ladder Logic Programming – Timer & Counter – 10 December 2010 RTO STATUS BITS Is Set When: Indicates: And Remains Set Until One of the Following Occurs: Timer Enabled EN (bit 15) the rung goes true that a timing operation is in progress • the rung goes false • a reset instruction reset the timer Timer Timing Bit TT (bit 14) the rung goes true that a timing operation is in progress • the rung goes false • the DN bit is set • the accumulated value is equal to the preset value (.ACC = PRE) • a reset instruction reset the timer Timer Done Bit DN (bit 13) the accumulated value is equal to the preset value that a timing operation is complete • the DN bit is reset with the RES instruction Ladder Logic Programming – Timer & Counter 6-19 This Bit: – 10 December 2010 EXAMPLE RTO LADDER DIAGRAM When the input is true, the processor starts incrementing the accumulated value of Timer_1 in 6-milisecond increments The timer values remain when the input goes false Sets the output when the input is true and the timer is timing Sets the output when the input is true and the accumulated value is greater then or equal to the preset value 6-20 Resets accumulated value of Timer_1 Ladder Logic Programming – Timer & Counter – 10 December 2010 COUNTER INSTRUCTIONS Count Up (CTU) • Count Down (CTD) 6-21 • Ladder Logic Programming – Timer & Counter – 10 December 2010 COUNT UP (CTU) Use CTU to increment the accumulated value by one count 6-22 Status bit: Ladder Logic Programming – Timer & Counter – 10 December 2010 CTU OPERATION • When the accumulated value equals or exceeds the preset value, the CTU instruction sets a done bit DN • The accumulated value of a counter is retentive 6-23 • The count is retained until reset by a reset instruction (RES) that has the same address as the counter Ladder Logic Programming – Timer & Counter – 10 December 2010 6-24 CTU TIMING DIAGRAM Ladder Logic Programming – Timer & Counter – 10 December 2010 EXAMPLE CTU LADDER DIAGRAM Each time the input goes from false to true, the processor increments the counter by Sets the output while the counter is counting Tells when the count is reached (ACC > or = PRE) 6-25 Reset the counter Ladder Logic Programming – Timer & Counter – 10 December 2010 COUNT DOWN (CTD) Use CTD to decrement the accumulated value by one count Status bit: – 10 December 2010 • The done bit DN is set as long as the accumulated value is greater than or equal to the preset value • When the accumulated value is less than the preset value, the done bit DN is reset • The accumulated value of a counter is retentive • When the accumulated value equals or exceeds the preset value, the CTU instruction sets a done bit DN • The accumulated value of a counter is retentive • The count is retained until reset by a reset instruction (RES) that has the same address as the counter Ladder Logic Programming – Timer & Counter – 10 December 2010 6-27 CTD OPERATION 6-28 CTD TIMING DIAGRAM Ladder Logic Programming – Timer & Counter – 10 December 2010 EXAMPLE CTD LADDER DIAGRAM Each time the input goes false to true, the processor decrements the counter by Sets the output while the counter is counting Tells when the count is reached (ACC > or = PRE) 6-29 Reset the counter Ladder Logic Programming – Timer & Counter – 10 December 2010 TIMER AND COUNTER RESET (RES) The RES instruction is an output instruction that resets a timer or counter The RES instruction executes when its rung is true Each time the input goes false to true, the processor decrements the counter by Sets the output while the counter is counting Tells when the count is reached (ACC > or = PRE) 6-30 Reset the counter Ladder Logic Programming – Timer & Counter – 10 December 2010 CONCLUSION Use this Instruction: Delay turning on an output TON Delay turning off an output TOF Time an event retentively RTO Count up CTU Count down CTD Reset a counter, timer, or counter instruction RES 6-31 If You Want to: Ladder Logic Programming – Timer & Counter – 10 December 2010 DAY SESSION 6-32 LADDER LOGIC PROGRAMMING – CONTROL INSTRUCTIONS Ladder Logic Programming – Timer & Counter – 10 December 2010 ... Logic Programming – Timer & Counter – 10 December 2010 TIMER INSTRUCTIONS • Timer On Delay (TON) • Timer Off Delay (TOF) 6-4 • Retentive Timer On (RTO) Ladder Logic Programming – Timer & Counter. .. accumulated value of Timer_ 1 Ladder Logic Programming – Timer & Counter – 10 December 2010 COUNTER INSTRUCTIONS Count Up (CTU) • Count Down (CTD) 6-21 • Ladder Logic Programming – Timer & Counter – 10... of Timer_ 1 in milisecond increment Sets the output while the timer is timing 6-9 Sets the output when the timer is done timing Ladder Logic Programming – Timer & Counter – 10 December 2010 TIMER