HighSpeed DSP and Analog System Design

This book covers the highspeed DSP and analog system design techniques and highlights common pitfalls causing noise and electromagnetic interference problems engineers have been facing for many years. The material in this book originated from my highspeed DSP system design guide (Texas Instruments SPRU 889), my system design courses at Rice University and my experience in designing computers and DSP systems for more than 25 years.

High-Speed DSP and Analog System Design Thanh T Tran High-Speed DSP and Analog System Design Thanh T Tran Texas Instruments Incorporated 12203 Southwest Freeway, MS 722 Stafford, TX 77477 USA ISBN 978-1-4419-6308-6 e-ISBN 978-1-4419-6309-3 DOI 10.1007/978-1-4419-6309-3 Springer New York Dordrecht Heidelberg London Library of Congress Control Number: 2010926196 © Springer Science+Business Media, LLC 2010 All rights reserved This work may not be translated or copied in whole or in part without the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or scholarly analysis Use in connection with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed is forbidden The use in this publication of trade names, trademarks, service marks, and similar terms, even if they are not identified as such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary rights Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) To my family, Nga, Lily, Kevin and Robin Preface This book covers the high-speed DSP and analog system design techniques and highlights common pitfalls causing noise and electromagnetic interference problems engineers have been facing for many years The material in this book originated from my high-speed DSP system design guide (Texas Instruments SPRU 889), my system design courses at Rice University and my experience in designing computers and DSP systems for more than 25 years The book provides hands-on, practical advice for working engineers, including: • Tips on cost-efficient design and system simulation that minimize late-stage redesign costs and product shipment delays • 11 easily-accessible chapters in 210 pages • Emphasis on good high-speed and analog design practices that minimize both component and system noise and ensure system design success • Guidelines to be used throughout the design process to reduce noise and radiation and to avoid common pitfalls while improve quality and reliability • Hand-on design examples focusing on audio, video, analog filters, DDR memory, and power supplies The inclusion of analog systems and related issues cannot be found in other high-speed design books vii Preface viii This book is intended for practicing engineers and is organized as follows: • Chapter 1: Highlights challenges in designing video, audio, and communication systems • Chapter 2: Covers transmission line theories and effects Demonstrates different signal termination schemes by performing signal integrity simulations and lab measurements • Chapter 3: Shows the effects of crosstalk and methods to reduce interference • Chapter 4: Provides an overview of switching and linear power supplies and highlights the importance of having proper power sequencing schemes and power supply decoupling • Chapter 5: Covers the analytical and general power supply decoupling techniques • Chapter 6: Covers design considerations of analog phase-locked loop (APLL) and digital phase-locked loop (DPLL) and how to isolate noise from affecting APLL and DPLL jitter • Chapter 7: Presents an overview of data converter, sampling techniques and quantization noise • Chapter 8: Covers analog active and passive filter design including operational amplifier design with single-rail and dual-rail power supplies • Chapter 9: Provides memory sub-system design considerations Includes DDR overview, signal integrity and design example • Chapter 10: Covers printed circuit board (PCB) stackup and signal routing considerations • Chapter 11: Describes sources of electromagnetic interference (EMI) and how to mitigate them ACKNOWLEDGMENTS I would like to thank many of my colleagues at Texas Instruments Incorporated who encouraged me to write this manuscript, Kevin Jones for doing the lab measurements to validate some of the theoretical concepts and simulations and Cathy Wicks for her outstanding support in many ways Also special thanks to Jennifer Maurer and Jennifer Evans of Springer for giving me this writing opportunity and for reviewing and providing great suggestions This book would not have been possible without the help and support from all these great individuals And, I just can’t thank my brother, Nhut Tran, enough for tirelessly spending weeks to review and edit every chapter in this book As for my daughter, Lily Tran, instead of relaxing over the Christmas break from months of extremely hard work at Massachusetts Institute of Technology, she voluntarily reviewed the entire manuscript and provided invaluable inputs Again, sincere thanks to both Nhut and Lily for doing this! Finally, for my wife, Nga, I am still amazed with how she can hold a very demanding full-time job at HP and still find time to provide great support to me and care to our kids She is truly an amazing friend and a remarkable soccer mom Thanh T Tran Houston, Texas, 2010 ix Contents Chapter 1: Challenges of DSP Systems Design 1.1 High-Speed Dsp Systems Overview .2 1.2 Challenges Of Dsp Audio System 1.3 Challenges Of Dsp Video System 1.4 Challenges Of Dsp Communication System References 11 Chapter 2: Transmission Line (TL) Effects 13 2.1 Transmission Line Theory 14 2.2 Parallel Termination Simulations 19 2.3 Practical Considerations Of TL 21 2.4 Simulations And Experimental Results Of TL 22 2.4.1 TL Without Load Or Source Termination 22 2.4.2 TL With Series Source Termination 24 2.5 Ground Grid Effects On TL 27 2.6 Minimizing TL Effects 28 References 30 Chapter 3: Effects of Crosstalk 31 3.1 Current Return Paths 31 3.2 Crosstalk Caused By Radiation 36 3.3 Summary .41 References 43 xi xii Contents Chapter 4: Power Supply Design Considerations 45 4.1 Power Supply Architectures 45 4.2 DSP Power Supply Architectural Considerations 55 4.2.1 Power Sequencing Considerations 61 4.3 Summary .64 References 65 Chapter 5: Power Supply Decoupling 67 5.1 Power Supply Decoupling Techniques .67 5.1.1 Capacitor Characteristics 69 5.1.2 Inductor Characteristics 72 5.1.3 Ferrite Bead Characteristics 74 5.1.4 General Rules-Of-Thumb Decoupling Method 75 5.1.5 Analytical Method of Decoupling 77 5.1.6 Placing Decoupling Capacitors 91 5.2 High Frequency Noise Isolation 94 5.2.1 Pi Filter Design 95 5.2.2 T Filter Design 98 5.3 Summary 102 References 104 Chapter 6: Phase-Locked Loop (PLL) 105 6.1 Analog PLL (APLL) 105 6.1.1 PLL Jitter 107 6.2 Digital PLL (DPLL) 111 6.3 PLL Isolation Techniques 114 6.3.1 Pi and T Filters 114 6.3.2 Linear Voltage Regulator 118 6.4 Summary 119 References 120 Chapter 7: Data Converter Overview .121 7.1 Dsp Systems 121 7.2 Analog-To-Digital Converter (ADC) 122 7.2.1 Sampling 124 7.2.1 Quantization Noise 126 7.3 Digital-To-Analog Converter (DAC) 130 Electromagnetic Interference (EMI) 203 A switching power supply generates fast current transients with a large amount of radiated energies A 1MHz switching power supply can radiate enough energy to fail EMI testing at the 100MHz frequency range • Inadequate power supply decoupling may lead to excessive voltage transients on the power supply planes and traces • The power supply board layout can be a root cause of oscillations + - I 14081/SO 14 U19A + 100nF - U19A 14 • 14081/SO I Figure 11.9 Power Supply Decoupling Reduces Current Loop Area As shown in Figure 11.9, decoupling the power supply reduces transients and provides a smaller current loop area If the power supply trace in Figure 11.9 is long and has no decoupling capacitor, the parasitic inductance is large and requires some time to charge up This delay is a root cause of the power supply droop problem Power supply droop occurs when the output buffer switches at a fast rate, but is starved for the current needed to drive the load, since the parasitic inductance between the power supply and the DSP becomes an open circuit Example 1: - A DSP BGA (ball grid array) package has a trace inductance of 1.44nH - This output is driving a 3” trace with 1nS risetime signal 204 Chapter 11 - This trace is being routed on a typical FR4 printed circuit board.Line characteristic impedance and IO voltage are 68 ohms and 3.3V respectively To estimate the power supply droop caused by the parasitic inductance, first let’s estimate the *as follows The dynamic IO current is the current transient for transmission line load, not steady state resistive load I ( peak ) = 3V ΔV = = 48 mA 68 Zo Since the package inductance is 1.44nH for 1nS risetime signal, the internal voltage droop is V ( droop ) = L dI 48 mA = (1 44 nH ) = 70 mV dt nS Typically, one DSP power supply pin is shared by many output buffers This creates larger droop and leads to higher radiation This helps explain why good power supply decoupling is required for low EMI design 11.6 TRANSMISSION LINE To combat TL effects, use simulation tools to fine-tune the series termination resistors to eliminate overshoots and undershoots caused by impedance mismatch explained in the Transmission Line chapter Improving signal integrity design helps reduce EMI But to minimize EMI, the series termination resistors should also be as large as possible without violating AC timing A parallel termination resistor as shown in Figure 11.10 is commonly used in RF and analog designs, but is not practical for digital signals due to the amount of DC current drained by the 50 ohm resistor If parallel termination is required, use a DC blocking capacitor in series with the resistor as demonstrated in the Transmission Line section Electromagnetic Interference (EMI) 205 Figure 11.10 Terminated and Un-Terminated Transmission Lines Table [5] shows the source current for different values of the series termination resistor Changing the value from 10 ohms to 39 ohms does not have much effect on the waveform, [5] showing about 1nS degradation, but dramatically reduces the source current which greatly lowers the radiate emissions Figure 11.11 shows a DSP board with a 47 ohm series resistor added to the memory clock, reducing the radiated emissions 3dB compared to the emissions of the signal without termination Overall, if slower risetime signals are acceptable and not violate AC timing specifications, designers should use the largest resistor value to terminate high speed signals to optimize the design from an EMI standpoint Table 11.1 Source Current For Different Series Termination Series Termination Resistor Value: Peak Source Current: 10 ohms ~ 40mA 22 ohms ~ 10mA 25 ohms ~ 5mA 30 ohms ~ 10mA 33 ohms ~ 9mA 39 ohms ~ 8mA 206 Chapter 11 Figure 11.11 DSP Board with Terminated Clock 11.7 POWER AND GROUND PLANES For high-speed DSP systems, it is getting more and more difficult to meet EMI regulations without using multiple layer PCBs and dedicating some of the layers as power and ground planes Compared to a trace, a power or ground plane has a lower parasitic inductance and provides a shielding effect for high-speed signals Power and ground planes also provide natural decoupling capacitance As described in the PCB layout section of this document, natural decoupling capacitance occurs when power and ground planes are spaced very closely, yielding higher capacitance This effect becomes very important at 300MHz speed or higher So, adding power and ground planes simplifies PCB routing and reduces the number of highfrequency decoupling capacitors required for the DSP Another important consideration for the PCB is layer assignment Refer to the board layout chapter, Chapter 10, to determine the best board stackup for your application Keep in mind that adding a ground plane directly underneath the high-speed signal plane creates an image plane that provides the shortest current return paths Studies in [2] and [3] show that image planes greatly reduce radiated emissions The comparison between PCB with and without image plane are shown Figures 11.12 and 11.13 Electromagnetic Interference (EMI) 207 Figure 11.12 Radiated Emissions Without Image Plane Figure 11.13 Radiated Emissions With Image Plane 208 Chapter 11 11.8 SUMMARY: EMI REDUCTION GUIDELINES In summary, here are the guidelines for low EMI system design: • Add image planes wherever possible • Create ground planes if there are spaces available on the routing layers Connect these ground areas to the ground plane with vias Creating a quarter-inch via grid is ideal • Add guard traces to high-speed signals if possible • Reduce the risetime of the signal if timing is not critical This can be accomplished by including series termination resistors on high-speed buses and fine-tuning the resistors for optimal signal integrity and EMI Series termination resistors lower the source current, increase the signal risetime and reduce transmission effects Substantial benefits can be achieved with this approach at a low cost • Keep the current loops as small as possible Add as many decoupling capacitors as possible Always apply current return rules to reduce loop areas • Keep high-speed signals away from other signals and especially away from input and output ports or connectors • Avoid isolating the ground plane If this is required for performance reasons, such as with audio ADCs and DACs, apply current return rules to connect the grounds together • Avoid connecting the ground splits with a ferrite bead At high frequencies, a ferrite bead has high impedance and creates a large ground potential difference between the planes • Use multiple decoupling capacitors with different values Every capacitor has a self-resonant frequency so be careful Refer to the Power Supply Decoupling Techniques section for more information • For PC board stackup, add as many power and ground planes as possible Keep the power and ground planes next to each Electromagnetic Interference (EMI) 209 other to ensure low impedance stackup or large natural capacitance stackup • Add an EMI pi filter on all the signals exiting the box or entering the box • If the system fails EMI tests, find the source by tracing the failed frequencies to their source For example, assume the design fails at 300MHz but there is nothing on the board running at that frequency The source is likely a 3rd harmonic of a 100HMz signal • Determine if the failed frequencies are common mode or differential mode Remove all the cables connected to the box If the radiation changes, it is common mode, if not, then it is differential mode Then, go to the clock source and use termination or decoupling techniques to reduce the radiation If it is common mode, add pi filters to the inputs and outputs Adding a common choke onto the cable is an effective but expensive method of reducing EMI 210 Chapter 11 REFERENCES [1] Federal Communication Commission (2005) Unintentional Radiators, Title 47 (47CFR), Part 15 B http://www.fcc.gov/oet/info/rules/part15/part15-91905.pdf [2] Montrose Mark (2000) Printed Circuit Board Design Techniques for EMC Compliance The Institute of Electrical and Electronics Engineers, New York [3] Montrose Mark (1996) Analysis on the Effectiveness of Image Planes within a Printed Circuit Board The Institute of Electrical and Electronics Engineers [4] Ott Henry (1988) Noise Reduction Techniques in Electronic Systems Prentice-Hall, New Jersey [5] Johnson, H, Graham, M (2003) High-Speed Signal Propagation Prentice-Hall, New Jersey [6] Renolds J (2003) DDR PCB Routing Tutorial Texas Instruments Inc Tutorial Glossary AC ADC APLL BER BGA CODEC CP CPU DAC DC DCO DDR DLL DNL DP DPLL DSP DVI ENOB EMC EMI EMIFF EMIFS ESL ESR FCC GP GPS Alternating current Analog-to-Digital Converter Analog phase-locked loop Bit Error Rate Ball Grid Array COmpression/DECompression Charge pump Central Processing Unit Digital-to-Analog Converter Direct Current Digital controlled oscillator Dual Data Rate Delay-Locked Loop Differential Non-Linearity Display Port Digital phase-locked loop Digital Signal Processing Digital Video Interface Effective number of bits Electromagnetic Compatibility Electromagnetic Interference External memory interface fast External memory interface slow Equivalent Series Inductance Equivalent Series Resistance Federal Communication Commission Gain peaking Global Positioning System 211 212 IEEE HD HDMI HSYNC INL IO JTAG LCD LDO LSB McBSP MPEG PCI PCB PFD PLL PSRR PWM RF SD SDRAM SNR SoC TL USB UWB VCO VSYNC WLAN Glossary Institute of Electrical and Electronics Engineers High Definition High Definition Media Interface Horizontal Synchronization Integral Non-Linearity Input/Output Joint Test Action Group Liquid Crystal Display Low dropout regulator Least significant bit Multi-Channel Buffered Serial Port Moving Picture Experts Group Peripherals Component Interface Printed Circuit Board Phase frequency detector Phase-Locked Loop Power Supply Rejection Ratio Pulse Width Modulation Radio Frequency Standard Definition Synchronous Dynamic Random Access Memory Signal-to-noise System-on-Chip Transmission Line Universal Serial Bus Ultra-Wide Band Voltage controlled oscillator Vertical Synchronization Wireless local area network Index AC timing, 204 Active Filter Design, 146, 164 Dynamic Range Limitation, 142 Adjacent power and ground, 189 Algorithms, 122 Amplifier circuit, 135 Amplitude modulating, 124 Analog circuit simulator, 97 Analog Filter Design, 141 Butterworth, 141, 146 Cauer and Besser, 141 Chebyshev, 141 Filter topology, 96, 175 Highpass filter, 160 Inverse Chebyshev, 141 Inverting lowpass, 164 Non-inverting lowpass, 164 Sallen-Key, 171, 172, 169 Analog-to-digital, 121 ADC, 5, 121, 138 Anti-aliasing filter, 5, 121, 126, 141 Differential Non-Linearity, 133, 135 DNL, 138 INL, 138 Integral Non-Linearly, 133, 137 Antenna, 40, 195 Artifacts, Attenuation, 98, 101, 132, 163, 175, 200 Audio, 5, 42, 121 Audio filter, 167 Backward crosstalk, 35 Ball grid array, 77, 82 Bandwidth, 94, 96, 98 BER, BGA package, 92, 188 Biasing, 150, 151, 175 Bluetooth, Board capacitance, 190 Boost converter, 50 Broadband, BT.1120, 213 214 BT.656, Buck converter, 50 Bulk capacitor, 78 Capacitance, 27 Capacitive load, 21 Capacitor characteristics, 69 Ceramic, 89, 71 Characteristic impedance, 17, 14, 24, 29, 27 Charge Pump, 106 Clock oscillator, 108 Clock Speed, 178 CODEC, 6, 24, 39 Common mode, 209 Common mode radiation, 197 Communication system, 8, 10 Controlled impedance, 188 Corner frequency, 98, 99, 102, 145, 159, 162 Cosine, 199 Coupling, CPU, 39 Crosstalk, 5, 7, 31, 33, 36, 40, 41, 187, 202 Current consumption, 80 Current loops, 201 Current return, 31, 201 Current return density, 33 Daisy-chain topology, 20 Data compression, 122 DDR, 78, 177 Decoupling, 6, 80, 203 Analytical decoupling, 82 Analytical Decoupling, 77 Design methodologies, 31 Dielectric constant, 189 Differential Clock, 178 Differential mode radiation, 197 Differential signals, 108 Differential Strobe, 178 Index Digital controlled oscillator, 112 Digital Controller, 112 Digital Controller Oscillator, 111 Digital-to-analog, 121 DAC, 6, 121, 130, 138 Distortion, DLL, 181 DLL power supply, 184 DSP, 1, 23, 45 Dual rail supply, 150 Duty cycle, 37, 51, 52, 200 DVI, Dynamic current, 55 Effective Number of Bits, 130 ENOB, 130, 133, 138 Effective radiator, 200 Effects of crosstalk, 31 Electric field, 197, 198 Electrolytic, 71, 72 Electromagnetic interference, 13 EMI, 28, 50, 79, 187, 191, 195 EMC, 1, 57 EMIFF, 82 EMIFS, 89 Equivalent series inductance, 70 ESL, 71, 76 Equivalent series resistance, 70 ESR, 76 Error amplifier, 45, 46 Ethernet, 9, 188 FCC, 31, 40 FCC Part 15 A, 195 Ferrite bead, 74, 94, 95, 208 Forward crosstalk, 35 FR4 printed circuit board, 204 Frequency Range, 142 Frequency response, 95, 99 Frequency spectrum, 124, 198 Full Grid Layout, 93 Index Gain peaking, 170 General Rules-Of-Thumb, 75 Ground grid, 27, 29, 28 Ground plane, 188 Harmonic, 36, 37, 40, 199, 209 HDMI, High Frequency Current Return, 32 High frequency noise, 94 IEEE802.11, Image plane, 192, 193, 206 Imbalance, 198 Impedance, 96 Impedance mismatch, 202 Inductance, 27, 68 Inductor characteristics, 72, 74 Initial voltage, 17 Input impedance, 157, 161, 162 Insulating core, 74 Interference Reduction, 2, 40, 41 Isolation, 102 Jitter, 6, 107 Cycle-To-Cycle Jitter, 109 Long Term Jitter, 108 Period Jitter, 110 Kirchhoff’s Current Law, 148, 149 Lattice diagram, 16 LC filter, 50 LDO versus Switching Regulators, 58 Least Significant Bit, 123 Line regulation, 56 Line Regulation, 53 Linear and non-linear distortions, 122 215 Linear regulator, 6, 45, 47, 57, 59, 76, 118 LM317, 48 Load regulation, 53, 56 Low dropout regulator, 113 Low Frequency Current Return, 32 Lowpass filter design, 164 Magnitude, 159, 160 Maximum crosstalk, 35 Maximum dynamic range, 146 Maximum swing, 150, 151 McBSP, Memory sub-system, 19, 177 Read Cycle, 181 SDRAM, 20 Write Cycle, 179 Memory signal integrity, 183 Methodologies, 164 Microphone, Microstrip, 190 Minimizing radiation, 36 MPEG-2 decode, 38, 39 MPEG-2 Encoder, 39 Noise characteristics, 69 Avalanche Noise, Burst Noise, Flicker Noise, 4, Shot Noise, Non-adjacent topology, 189, 190 Non-embedded designs, 183 NTSC spectrum, 40 Open ended load, 15 Operating frequency, 166, 198 Operational Amplifier, 141, 147, 148 AC Couple, 155, 160, 175 AC gain, 148 AC ground, 152 216 DC and AC Coupled, 155 Inverting amplifier, 160 Inverting input, 147 Non-inverting amplifier, 147, 154 Virtual ground rule, 148, 149 Oscillations, 45 Oversampling, 134 Oversampling ADC or DAC, 134 Overshoot, 16, 17, 181 Parallel capacitance, 189 Parallel combination, 154, 167 Parallel termination, 19, 25, 29, 204 Parasitic inductance, 68, 206 Passband, 101, 174 Passive and active filters, 142, 146 Passive filter, 144, 146 Passive Lowpass Filter, 143 Pi filter, 94, 114 T filter, 94, 100, 115 PCB, 6, 31, 91, 187 PCB manufacture, 188 PCI, PCI Express, Phase relationship, 165 Phase-Frequency Detector, 106 Phase-shift, 179 Pixel clock, Placing Decoupling Capacitors, 91 PLL, 57, 76, 82, 105 APLL, 106 Digital PLL, 105 Divide-by-M counter, 107 DPLL, 111 PLL isolation, 114 Power Consumption, 178 Power dissipation, 47, 50 Index Power efficiency and dissipation, 45 Power plane, 188 Power Sequencing, 61 Power Sequencing Verification, 63 Power spectral density, 41 Power supple ripple, 56 Power supply architectures, 45, 60 Power supply decoupling, 67 Power supply droop, 204 Printed circuit board, 187 Probability Density Function, 127 Propagation delay, 14, 22, 29 PSRR, PWM, 50, 51, 196 Quantization, 126 Quantization error, 123, 126 Quantization step, 126 Radiated emissions, 94, 192, 195, 206 RapidIO, 188 Reconstruction Filter, 121 Reflected voltage, 17 Reflections, 13, 14, 202 Reliability, 142 Reset, 60 Resolution, 133 RF spectrum, Ripple rejection, 48, 118 Rise and fall-times, 37 RMS, 127 Routability, 191 Routing layer, 189 Sampling, 124 Aliasing, 125 Nyquist, 124, 125, 134 Index Sampling frequency, 125, 134, 141 Sampling noise, 121, 132 Self-resonant frequency, 70, 72, 79, 208 Series termination, 20, 21, 24, 40, 41, 208 Shielding, 175 Shielding layer, 192 Signal integrity, Signal Quality, 191 Signal-to-noise, 129 SNR, 133, 138 Simulation, 145, 146, 158, 163 Single rail supply, 150 Sinusoidal, 127, 199 Skin effect, 32, 201 Spread spectrum, 8, 42 Squarewave, 199 Stability analysis, 166 Stackup, 187, 206 Standard definition, Stripline, 190 Switching Current Estimation, 84 Symmetrical, 93 System start-up, 63 Tantalum capacitor, 71, 76 Termination, 7, 13, 183 Thermal Noise, 217 Threshold voltage, 182 Time shifting, 39, 40 Timing Interval Analyzer, 110, 111 Timing violations, 41 Transient Response, 53, 203 Transistor, 46 Transmission line, 13, 15, 81, 196, 204 Lossy TL, 13 Transmission line effects, 28, 187 Undershoots, 181 Unstable, 166 USB, 188 VCO, 107 Video, 6, 38, 42, 121 Voltage Controlled Oscillator, 106 Voltage droop, 55 VREF, 128, 179 Waveforms at the Terminated and Unterminated Loads, 18 Wavelength, 200, 41 WLAN, Zero-to-peak voltage, 128 Zig zag pattern, 28 .. .High-Speed DSP and Analog System Design Thanh T Tran High-Speed DSP and Analog System Design Thanh T Tran Texas Instruments Incorporated 12203 Southwest... amount of time in the use of low-noise and low-radiation design methods T.T Tran, High-Speed DSP and Analog System Design, DOI 10.1007/97 8-1 -4 41 9-6 30 9-3 _1, © Springer Science+Business Media,... from analog to digital and back to analog T.T Tran, High-Speed DSP and Analog System Design, DOI 10.1007/97 8-1 -4 41 9-6 30 9-3 _2, © Springer Science+Business Media, LLC 2010 13 14 2.1 Chapter TRANSMISSION