A practical guide to RF and mixed signal printed circuit board layout

Contents Table of Figures List Of Tables Acknowledgements Forward So What’s The Difference Between Analog And Digital? Do We Still Use Analog? What’s The Frequency? When Does Analog Become RF? Converging Domains Analog / RF Issues To Consider Loss Dielectric Loss Skin Effect Return Loss Or VSWR Noise / Coupling / EMI / Shielding Clean Power Delivery A Few things Before Starting The Design The Schematic And Mechanical Drawings The Circuit Blocks Slots And Splits In Power And Ground Planes High speed return current Fringe fields Some exceptions Power planes Isolate In X/Y Axis Isolate In Z Axis Isolate In X/Y Axis And Z Axis Layer And Layer Usage Choosing Between Single And Dual Stripline Useful RF And Mixed Technology Stackups Layer RF Only Design Stackup Layer RF Only Design Stackup Layer XYZ Mixed RF - Digital Design Stackup – Low Density Digital 10 Layer Mixed RF - Digital Design Stackup – Low To Medium Density Digital 12 Layer Mixed RF - Digital Design Stackup – Medium To High Density Digital 14 Layer Mixed RF - Digital Design Stackup – High Density Digital 16 Layer Mixed RF - Digital Design Stackup – High Density Digital It’s A Material World On The Right Wavelength ? Processes And Cost Transmission Lines Dispersion Microstrip Structure Impedance Calculation Advantages Disadvantages Embedded Microstrip Structure Impedance Calculation Advantages Disadvantages Stripline Structure Impedance Calculation Advantages Disadvantages Coplanar Waveguide (CPW) Structure Impedance Calculation Notes: Advantages Disadvantages Component Selection A Place For Everything The Long And The Short Of It Power Delivery, Decoupling and Bypassing Decoupling Bypassing Bypassing Low Frequency Analog Circuits Bypassing RF Circuits Bypassing Digital Circuits Capacitor Selection Placing And Routing Decoupling And Bypass Capacitors Routing Mixed Technology Printed Circuit Boards Net Classes And Constraints Classes Constraints Routing Do Not Route Signals Over Splits In Reference Planes No Vias In RF Or High Speed Digital Signal Paths No Stubs Allowed In Signal Path Routing Traces, Shapes And Modified Footprints Corners In RF Traces T-Junctions And Power Dividers In RF Traces Matching Transmission Line Width To Pad Geometries Ground: Copper Floods, Vias and Shielding Flooding Unused Areas With Ground Adding Ground Vias Ground Shielding Vias Ground Stitching Vias Ground Transition Vias EMI Shielding Vias Shielding Summary Conclusion Table of Figures Figure Cross Section Of Current Flow At low And High Frequencies Showing Skin Effect Figure Voltage Reflection Where Load Impedance Is Higher Than Line Impedance Figure Voltage Reflection Where Load Impedance Is Lower Than Line Impedance Figure Power Implemented As A Wide Trace Figure Power Implemented As A Local Plane - Potential Patch Antenna Figure Example Of When An Impedance Mismatch Becomes An Issue - @ f = 5GHz Figure Floorplan View Of X/Y Axis RF And Digital Zone Isolation Figure Cross Section View X/Y Axis Only RF And Digital Zone Isolation Figure Z Axis Isolation Of RF And Digital Circuitry Figure 10 Floorplan View X/Y And Z Axis RF And Digital Zone Isolation Figure 11 Cross Section View X/Y And Z Axis RF And Digital Zone Isolation Figure 12 Layer As Reference Ground For Microstrip Allows Wider Transmission Line Figure 13 Difference Between Past And Present Typical Digital Routing Figure 14 Typical Layer RF Only Stackup Cross Section Figure 15 Typical Layer RF Only Stackup Cross Section Figure 16 Typical Layer Mixed RF/Digital Stackup Cross Section Figure 17 Typical 10 Layer Mixed RF/Digital Stackup Cross Section Figure 18 Typical 12 Layer Mixed RF/Digital Stackup Cross Section Figure 19 Typical 14 Layer Mixed RF/Digital Stackup Cross Section Figure 20 Typical 16 Layer Mixed RF/Digital Stackup Cross Section Figure 21 Differences In Fiber Density With Different Weave Styles Figure 22 Advantages And Examples Of Via In Pad Technology Figure 23 Resistive Model Of A DC Or Low Speed Transmission Line Figure 24 Complete Model Of A High Speed Transmission Line Showing Parasitic Elements Figure 25 Microstrip Transmission Line Construction Figure 26 Embedded Microstrip Transmission Line Construction Figure 27 Stripline Transmission Line Construction Figure 28 Coplanar Waveguide Transmission Line Construction Figure 29 Example Of Keeping Input And Output Of A Circuit Block Well Distanced Figure 30 Amplifier And Filter With Overlapping Loop Areas Figure 31 Modified Amplifier Bypassing To Reduce Loop Area Figure 32 Floorplan Of Typical RF Modem Design With Baseband Processing And Power Supplies Figure 33 Noise Transients Can Travel Anywhere On The Board Figure 34 Well Selected And Placed Decoupling Capacitors Can Keep Power Planes Much Cleaner Figure 35 Bypass Capacitors On Analog Device Can Remove Noise Already Existing On Power Connections Figure 36 Bypass Network Frequency Response With All Low ESR Capacitors Figure 37 Bypass Network Frequency Response May Improve If One Or More Capacitors Have Higher ESR Figure 38 General Placement Of Discrete Parts Around Large Integrated Devices Figure 39 Placement And Via Usage For BGA Bypassing Figure 40 Placement And Connections For Bypassing QFP With Thermal Pad Figure 41 Placement And Connections For Bypassing QFP Without Thermal Pad Figure 42 Connections To Power Plane For Decoupling Capacitors Around High Density Digital Devices Figure 43 Connections To Plane With Bypass Capacitors ‘On The Way’ For An Analog Amplifier Figure 44 Slot In Ground Plane Causes Long Ground Return Path Figure 45 Example Placement With Resulting Return Paths And Loop Areas Figure 46 Adding A Ground Plane Split To Restrict Ground Current Paths Figure 47 Stub Caused By A Through Via Being Accessed On An Internal Layer Figure 48 Back-drill Eliminates Most Of The Stub, Blind Via Or Microvia Eliminates The Stub Figure 49 Routing The Same Connection With And Without Stubs Figure 50 Improved Placement And Via-In-Pad Technology Can Easily Remove Stubs In RF Design Figure 51 Offset Pad Origin Can Resolve DRC Errors On Small Components Figure 52 Footprint Based Rule Area Can Resolve DRC Errors On Small Components Figure 53 Tapered Transitions To Transmission Line Width Can Be Built Into The Footprints Figure 54 The 90 Degree Corner - Worst Case Method And Best Case Method Figure 55 Different Ways To Implement 90 Degree Bends in RF Transmission Lines Figure 56 Impedance Mismatch Area With Simple T-Junction Figure 57 T-Junction Impedance Mismatch And Commonly Used Compensations Figure 58 Transmission Line Geometry Does Not Match Component Pad Geometry Figure 59 Removing Planes Copper Beneath Large Component Pads Figure 60 Stepped And Tapered Matching Of Transmission Line To Pad Geometry Figure 61 Ground Stitching Along RF Signal Paths - Maintain 3H Spacing To Traces Figure 62 Ground Stitching Along RF Traces And Under Perimeter Shield Walls Figure 63 Ground Stitching Vias Added Where Space Permits Around The Design Figure 64 Effect On Ground Return Current If There Are No Ground Vias Nearby Figure 65 Ground Vias And Antipad At Differential Pair Layer Transition Figure 66 Some Typical Perimeter EMI Shielding Via Patterns Figure 67 An Example Of Standard Off The Shelf Shielding Products Figure 68 Photo Etched Shielding Can Be Custom Shaped And More Complex Figure 69 Some Examples Of Custom Milled RF Enclosures List Of Tables Table Common Circuit Board Materials Of Different Compositions With Loss And Dielectric Constant Table Suggested Layer Usage For Typical Layer RF Only Stackup Table Suggested Layer Usage For Typical Layer RF Only Stackup Table Suggested Layer Usage For Typical Layer Mixed Technology Stackup Table Suggested Layer Usage For Typical 10 Layer Mixed Technology Stackup Table Suggested Layer Usage For Typical 12 Layer Mixed Technology Stackup Table Suggested Layer Usage For Typical 14 Layer Mixed Technology Stackup Table Suggested Layer Usage For Typical 16 Layer Mixed Technology Stackup Table Difference In Signal Wavelength In Air And In Different Circuit Board Environments Table 10 Typical SMD Bypass Capacitors And Their Useful Frequency Ranges Acknowledgements The author would like to express thanks and appreciation to the following people, without whom it would not have been possible to put this guideline together Nick Barbin President - Optimum Design Associates For providing the idea, encouragement, patience, and the time to compile and present the guideline This guideline took many hours to produce and would not have been possible if the time was not proved to so Scott Nance Senior Designer - Optimum Design Associates For his invaluable assistance in so many ways Scott spent many hours reading word by word, providing extremely useful content, corrections, feedback and suggestions for improvement Scott has also presented this guideline in slide show/discussion form at trade shows and at specific customer sites Rick Hartley Industry recognized consultant on the topic of High Speed and Mixed Technology Design Rick was kind enough to volunteer his time to read the guideline completely and provided much extremely useful feedback and some very critical and needed corrections to the content Robert Frank Marketing Manager - Optimum Design Associates For many hours of proof-reading, grammar correction and for getting this book published Optimum Design Associates Designers The entire design group at Optimum Design Associates These include Randy Holt, Scott Nance, Juliet Wang, Tom Stout, Mark Gutierrez, Frank Jacobson, Brian Noble, Rick Dachauer All of these designers have contributed over the years by way of being part of a collaborative team of senior designers We all have both common and specific skills and learn from each other Figure 63 Ground Stitching Vias Added Where Space Permits Around The Design In a typical digital circuit there is already quite a high number of ground vias, a single BGA or QFP device these days may have anything from 10 – 200 or more ground pins on the package Each of these is typically connected to its own ground via, so a digital circuit already has significantly more ground vias than a typical analog circuit Of course the problems of inductance and resistance in ground can also be a lot more prevalent in a digital circuit because of the high speeds associated with digital signal edges and the localized very high current paths associated with power in many FPGA and other high density digital device power supplies In a digital circuit the power delivery network is extremely important too, and becoming more so with increased component and pin densities, and device I/O pins all switching simultaneously at very high speeds Along with this are the reduced operating voltages, usually meaning higher power supply currents, so the power delivery network resistance plays a much bigger role in maintaining the correct supply voltages than it has in the past Placing additional ground vias, and therefore holes or slots in power planes, will increase the resistance of the planes, something that may be a serious issue All these factors make adding ground stitching vias something of a ‘double edged sword’ On the one hand it is good to add more vias to improve the ground and signaling performance, but on the other hand care must be taken not to overdo it and reduce the performance of the power planes So keep these factors in mind when adding ground stitching vias in a digital circuit area, and add them carefully Although it sounds complicated it is really not that difficult to achieve significant overall design improvement without causing unwanted side effects as a result Ground stitching vias in an RF area are not usually added to reduce ground return current loop area, there are far fewer signals in an RF circuit, and usually these signals are short point to point connections on a single layer implemented as microstrip or stripline above or between solid ground planes, so the return path is simply in the ground plane immediately adjacent to the signal layer used In a digital circuit however, the signals can travel much longer paths and can easily have multiple vias in the path which transition the signal from one layer to another These signal layer transitions mean that the ground return path can be increased considerably because the return path for a high speed digital signal is in the closest ground plane to the signal Consider an inch long high speed digital signal routed on layer of a 16 layer design that transitions half way along its path to layer 14 With layer and layer 15 being ground planes the return path is initially on layer 2, but when the signal transitions to layer 14 the closest, lowest impedance return path is now on layer 15, so the ground return current will have to travel past the signal layer transition point until it finds a ground via or pin that allows it to transition to layer 15 These increased ground return paths are a major factor in creating signal noise and voltage offsets in ground planes Adding ground stitching vias where possible will go a long way towards preventing these issues When adding the stitching vias in a digital circuit area, a good place to start is in the middle of a group of signal transition vias that are not close to components because it is unlikely that there will be many, if any, ground vias close by (Fig 64) Figure 64 Effect On Ground Return Current If There Are No Ground Vias Nearby Ground Transition Vias These are ‘designed in’ ground vias, added at layer transitions in very high speed signal paths Although they are referred to here as ‘designed in’ vias, they are not usually present in design schematics, although they easily could be In this context the term ‘designed in’ is used to indicate that these vias are actually a part of the electrical design and are not vias simply added post route in spaces where they can fit because space is available Rather they are added at the same time as the signal layer transition vias in the routing process so that they are accounted for at all times These vias serve a very specific and important purpose, that being to provide as close to a continuous ground return path for very high speed signals, typically differential pairs, as possible When a high speed signal transitions from one routing layer to another the result is that the return path of the signal will also attempt to transition to the closest ground plane to the layer that the signal has transitioned to, because it will be the lowest impedance path If there is no immediate path for the return current to the new reference plane, then the return current will travel to a location where it can make the transition Maintaining as tight as possible coupling between a signal trace and its return path is a vital part of minimizing noise and insertion loss in circuit board layout design These vias are required more and more in high speed digital communications circuits where very high speed serial data paths are implemented as differential pairs There are times when it is unavoidable that these signals paths will need to have vias added, and indeed times when adding vias is a useful technique employed to reduce or even eliminate stubs in the signal path Most high speed communications device datasheets and application notes will include manufacturer recommended transition via topologies to employ Sometimes a single via is added near the pair of differential signal transition vias, sometimes one via at each signal via, sometimes more These are also usually accompanied by custom antipad designs that remove planes copper for specified distances around the transition vias, thereby reducing via capacitance When a company uses standardized stackups for their circuit board designs, as many do, then these differential signal transition vias, including the added ground vias and plane antipads, could even be designed as a library part and added to the design at the schematic level Where stackups and via sizes vary from design to design, then for consistency in via placement and mechanical uniformity, a single transition vias model could be created as a drawing part and added to the circuit board CAD design as a reference to ‘snap to’ when placing the vias and antipads in the design (Fig.65) Figure 65 Ground Vias And Antipad At Differential Pair Layer Transition It is also a good idea to try to place ground transition vias at locations where other, possibly less critical, signals transition from layer to layer in the routing process and these transitions are not close to existing ground vias, especially in digital designs Even though a digital signal may be considered less critical, it is very likely, with today’s device technologies, that the edge rates of these signals are still fast enough that they should be considered high speed signals, remember it is the edge rate rather than the clock frequency alone that determines whether a signal should be treated as high speed Increased impedance in the return path for the high speed edge rate signals is a direct cause of noise in digital circuits Consider during routing that, if there is a need to transition a group of signals to another layer(s), then it is a good idea to add some standalone ground vias amongst the group of signal vias This is often overlooked and it will be much more difficult, if not impossible, to add a couple of vias post route, at least not without a great deal of unnecessary editing EMI Shielding Vias These are vias added around the periphery of the circuit board to reduce EMI radiation, caused predominantly by internal power plane and high speed signal trace fringing fields, by creating a Faraday cage This radiation can easily find its way into adjacent circuit boards or even enclosures, depending on the mechanical arrangement of circuit boards in a multi board system The presence of a grounded via fence around the board perimeter can also be useful in preventing noise present outside the circuit board from entering the circuit via the circuit board edges and finding it’s way on to power planes and signal traces near the edge There is often an exposed copper ground strip required on both top and bottom layers, and often on all layers, and these are tied together with ground vias all around the board edges The pitch of the vias should be 75mils or less, and often there are two or more rows of vias It is possible to achieve as much as 10 – 20dB reduction in radiated EMI caused by fringing fields of power planes and high speed signal traces closest to the board edges It is recommended that this perimeter ground strip and via wall be on all layers of the board There has been a 20H rule in place for many years, where the power planes are ‘pulled back’ from the ground planes by 20H to reduce the effects of fringing fields at the board edges As mentioned earlier, there is research to suggest that this can actually cause more EMI issues than it solves If the via wall is around the perimeter, and the GND copper strip is on all layers of the design, then the power planes, and the signal routing, are pulled back from the edges by more than the 20H anyway Even if there are fringing fields radiating from the edges of the planes, the perimeter via wall and ground strip will prevent them from radiating from the board edge and potentially causing an EMI issue Placing power and ground planes on adjacent layers is best because the material thickness would be thinner and the coupling between the planes would be better, with reduced fringing fields Ideally there should be no signal routing amongst these vias but that is not always possible, certainly there should be no routing of any kind outside these vias If there are multiple rows, or more, of vias and some of the available space between them for has to be used for routing, then at least never route in the channel before the last vias at the edge and always be very selective about which signals are routed there Sometimes used this space can for completely static signals like LEDs, configuration switches etc., but never for high speed switching signals High speed signals should be kept at some distance from these shielding vias as well, at least 75 – 100 mils, to prevent any noise reflected back into the board from the via fence from finding its way on to these high speed traces In a modular system utilizing card guide slots, these perimeter vias can also be an effective method of extracting heat from the ground planes and conducting it through metallic card guides to the chassis where it can be further cooled through either convection of conduction cooling methods Figure 66 Some Typical Perimeter EMI Shielding Via Patterns Shielding In RF circuits there are many situations when additional shielding is required Sometimes circuit blocks are so close together because of board space limitations that some coupling between adjacent circuits is unavoidable A design may include ultra-sensitive high impedance input amplifier circuits where any noise in the area is going to induce significant voltage at the amplifier inputs and cause these circuits to fail completely Microstrip RF circuits, with both components and connections on the surface layer nearly always require additional shielding RF designs implemented completely in stripline will already have the connecting traces very well shielded between ground planes, but the components mounted on the board surface are not shielded An additional mechanical shield may still be required Whatever the reason, there will often be a need to shield circuit areas from each other physically There are various ways this can be implemented including: Simple off the shelf shielding products are available from multiple vendors There is a huge variety of these products available for many different circumstances These are available both as predefined surface mount or through hole cans of specific shapes and dimensions or as prefabricated walls, again surface mount or through hole, that allow a certain degree of flexibility to define various shield dimensions These tend to create shielding cans that are rectangular or odd shaped but with squared corners and are flexible only within limits, for example mounting points may be located every 250 mils and maybe it can only bend every 250mils and the bend location is in the middle of the mounting point locations There is normally an exposed surface ground shape the same as the shield on the side(s) of the board that the shield mounts to so that it can be soldered to the board around its perimeter Access to the circuits inside the shield for testing or servicing is usually by way of a removable lid over the shield, but holes can be placed in the lid or the sides of the shield to allow tuning adjustments to be made while the shield is in place It can be a challenge to create a shield that encompasses all of the required circuitry and at the same time not be too large which would cause a loss of valuable real estate that is needed for other circuits Creating odd shapes from these precut strips can be labor intensive in a high volume production environment If the requirement is for a relatively simple shield, and the available space is not overly constrained and the production volume is low enough, then these can be an easy and relatively inexpensive solution to the shielding requirements Figure 67 An Example Of Standard Off The Shelf Shielding Products Photo etched custom shields These are shield walls photo etched to create a custom shield can for a specific design They have the advantage of being much more flexible in terms of shape, mounting point locations, angled edges, cutout tunnels for microstrip entry and exit points, and more height options Like the off the shelf versions, there will usually be exposed copper the same shape as the shield to allow it to be soldered to the board around its entire perimeter if needed The same methods for accessing and adjusting circuitry inside the shield are used as for the simple off the shelf shields described above Since they are custom photo etched for a specific design, there is much less preforming needed at the assembly stage so they are also better suited to higher volume assembly In appearance, these look the same as the standard off the shelf version, but the dimensions are a lot more flexible These are more expensive than the off the shelf versions but the advantages they offer may easily offset the additional expense Figure 68 Photo Etched Shielding Can Be Custom Shaped And More Complex Custom milled cavity shields This is basically a solid block of material, usually aluminum, with various different shaped cavities milled out such that, when it is placed upside down on top of an assembled circuit board, the different circuit blocks simply fall within their own rooms These shields are much more expensive to create but they offer ultimate flexibility of design and the best shielding performance This is an often used design methodology and it is not difficult to The shape of the cavities is almost completely arbitrary, with the only limitation usually being a minimum inside corner radius, based on the size of the milling bit, so it is possible to really optimize circuit placement without needing to consider the shield wall locations The layout designer simply defines the shield walls as the design progresses Another distinct advantage is that the milled rooms can be of different depths, even varying within the same room, so shielding circuits of different heights is also easily achievable with the same single shield Mounting these shields is usually by way of screwing the assembled board to it, the walls are not soldered to the board It is common to use a custom designed conductive gasket between the shield and the board to create a complete seal both for EMI and environmental conditions Curved, round, angled and virtually any odd shaped cavity is easily manufactured using this method This shielding could be used to partition a single large circuit board into multiple different functional rooms, or else smaller single function circuit boards could be designed and each would be mounted upside down in its own room This allows for different board thicknesses and layer counts all to be assembled in the same shield, say a combination of layer 1mm thick RF modules and 20 layer 3mm thick digital modules and anything in between Figure 69 Some Examples Of Custom Milled RF Enclosures Summary The successful design of today’s complex mixed technology printed circuit boards is a challenging and evolving task There are many things to consider, beyond what was necessary when previously designing circuit boards for essentially a single technology This guideline is presented in an effort to, at the very least, increase layout designers’ awareness of some factors to consider that may not previously have been given significant consideration in previous years Much of this information is readily available from many sources, especially in today’s internet age That information, however, is rarely ever consolidated into a single guideline that attempts to cover all the many facets of the printed circuit board design process Another notable factor in much of that readily available information is the language used and the sometimes overwhelming amount of theory and complex mathematics It has been a major aim of this guideline from the start to present the information as completely and correctly as possible, while still doing so in a language that is easily read and understood by as many layout designers as possible In truth, there is a finite number of things a designer can to improve the overall performance of a circuit board layout and, often regardless of all the mathematics and simulations that may be employed, it is simply a case of doing it right and it will work That statement in no way negates the need for the calculations and simulations It is simply that, even with the results of those efforts, there is often little that can really be done to improve a design, especially a well done design, without needing to go to a full redesign of the board The aim of this guideline is to try to ensure that these designs are done as correctly as they can be in the first place Doing so has been found repeatedly to yield good results from simulations and testing and there should therefore be little need to change the design in any significant way as a result of poor layout techniques being employed Although the guideline attempts to present some background theory for as many of the topics as possible, that theory is deliberately presented without the use of complex mathematics and formulae wherever possible Each major topic presented could easily be at least as long as the entire guideline in its’ own right Readers are therefore encouraged to continue researching all of the topics presented, and more, in an effort to increase their knowledge and capability as a successful designer of mixed technology printed circuit boards The guideline attempts to cover the broad range of topics in a similar order to the layout design process This includes such topics as: - The difference between Analog and Digital design - Low frequency Analog versus RF - Issues to consider, Loss, Noise etc - Skin effect - Power Delivery - Schematics - Mechanical specifications - Dividing the circuit into functional blocks - Slots and splits in planes - Return paths - Fringe fields - Isolation in X, Y and Z axes - Layer usage, especially layer - Single or dual stripline - Example mixed technology fabrication stackups - Materials - Wavelength in the medium of the signal - Processes and cost - Transmission lines - Dispersion - Component selection - Placement strategies and guidelines - Long traces and short traces - Power delivery system - Bypassing - Decoupling - Net classes - Constraints and constraint classes - Routing guidelines - Right angled corners - Vias and stubs Copper floods Shielding, transition and stitching vias It is the hope that readers find the information both useful and easy to read and understand Conclusion Today’s designs are more complex than ever, especially when adding in any combination of mixed signal technologies such as RF, Analog, and Digital Having a better understanding of the differences between them will help the layout designer make appropriate decisions and trade-offs in placement and routing to help ensure a successful design that performs up to its maximum specification parameters The biggest culprits that reduce performance or even cause non-performance are loss and noise By being aware of the detrimental aspects of loss and noise, a designer can create a strategy utilizing the many methods and techniques described in this guideline to reduce them as much as possible At Optimum, our designers have a strong culture of collaboration: Designer to Designer, Designer to Customer, and Designer to the PCB Industry, and this guideline is our contribution to further the art and science of PCB design within our PCB industry ... also storage and retrieval of the analog data on digital media because it is far more reliable, portable, lower cost and much faster than analog storage media like disc records and tapes What’s... designers We all have both common and specific skills and learn from each other Forward This guideline is presented as a practical guide to the physical layout design of RF and, in particular, mixed. .. Disadvantages Stripline Structure Impedance Calculation Advantages Disadvantages Coplanar Waveguide (CPW) Structure Impedance Calculation Notes: Advantages Disadvantages Component Selection A