Download Solution Manual for The Intel Microprocessors 8th Edition by Brey Chapter Two Program visible register are the registers that are directly used in an instruction The 80386 through the Core2 CL, CX, ECX, or RCX INC and DEC Odd 11 The 80386 through the Core2 13 (a) 10000H—1FFFFH (b) 12340H—2233FH (c) 23000H—32FFFH (d) E0000H—EFFFFH (e) AB000H—BAFFFH 15 100000H 17 EAX, EBX, ECX, EDX, EBP, ESI, and EDI 19 Stack 21 (a) 23000H (b) 1C000H (c) CA000H (d) 89000H (e) 1CC90H 23 Any location in the memory system 25 8,192 27 01000000H—0100FFFFH 29 31 Descriptor 20H, local table, a privilege ring 35 GDTR 37 The internal cache is loaded with the base address, offset address, and access rights byte 39 The GDTR address the Global Descriptor Table 41.4,096 43 4M 45 30000000H 49 The flat mode memory system is used with 64-bit operation of the Core2 Chapter Two Program visible register are the registers that are directly used in an instruction The 80386 through the Core2 CL, CX, ECX, or RCX INC and DEC 10 Odd 12 The 80386 through the Core2 14 (a) 10000H—1FFFFH (b) 12340H—2233FH (c) 23000H—32FFFH (d) E0000H—EFFFFH (e) AB000H—BAFFFH 16 100000H 18 EAX, EBX, ECX, EDX, EBP, ESI, and EDI 20 Stack 22 (a) 23000H (b) 1C000H (c) CA000H (d) 89000H (e) 1CC90H 24 Any location in the memory system 26 8,192 28 01000000H—0100FFFFH 30 32 Descriptor 20H, local table, a privilege ring 36 GDTR 38 The internal cache is loaded with the base address, offset address, and access rights byte 40 The GDTR address the Global Descriptor Table 42.4,096 44 4M 46 30000000H 50 The flat mode memory system is used with 64-bit operation of the Core2