Communications in Computer and Information Science 120 Tai-hoon Kim Thanos Vasilakos Kouichi Sakurai Yang Xiao Gansen Zhao ´ ˛zak (Eds.) Dominik Sle Communication and Networking International Conference, FGCN 2010 Held as Part of the Future Generation Information Technology Conference, FGIT 2010 Jeju Island, Korea, December 13-15, 2010 Proceedings, Part II 13 Volume Editors Tai-hoon Kim Hannam University, Daejeon, South Korea E-mail: taihoonn@hnu.kr Thanos Vasilakos University of Western Macedonia, Kozani, Greece E-mail: vasilako@ath.forthnet.gr Kouichi Sakurai Kyushu University, Fukuoka, Japan E-mail: sakurai@csce.kyushu-u.ac.jp Yang Xiao The University of Alabama, Tuscaloosa, AL, USA E-mail: yangxiao@cs.ua.edu Gansen Zhao Sun Yat-sen University, Guangzhou, China E-mail: zhaogansen@gmail.com ´ ˛zak Dominik Sle University of Warsaw & Infobright, Poland E-mail: dominik.slezak@infobright.com Library of Congress Control Number: 2010940170 CR Subject Classification (1998): C.2, H.4, I.2, D.2, H.3, H.5 ISSN ISBN-10 ISBN-13 1865-0929 3-642-17603-8 Springer Berlin Heidelberg New York 978-3-642-17603-6 Springer Berlin Heidelberg New York This work is subject to copyright All rights are reserved, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, re-use of illustrations, recitation, broadcasting, reproduction on microfilms or in any other way, and storage in data banks Duplication of this publication or parts thereof is permitted only under the provisions of the German Copyright Law of September 9, 1965, in its current version, and permission for use must always be obtained from Springer Violations are liable to prosecution under the German Copyright Law springer.com © Springer-Verlag Berlin Heidelberg 2010 Printed in Germany Typesetting: Camera-ready by author, data conversion by Scientific Publishing Services, Chennai, India Printed on acid-free paper 06/3180 Preface Welcome to the proceedings of the 2010 International Conference on Future Generation Communication and Networking (FGCN 2010) – one of the partnering events of the Second International Mega-Conference on Future Generation Information Technology (FGIT 2010) FGCN brings together researchers from academia and industry as well as practitioners to share ideas, problems and solutions relating to the multifaceted aspects of communication and networking, including their links to computational sciences, mathematics and information technology In total, 1,630 papers were submitted to FGIT 2010 from 30 countries, which includes 150 papers submitted to the FGCN 2010 Special Sessions The submitted papers went through a rigorous reviewing process: 395 of the 1,630 papers were accepted for FGIT 2010, while 70 papers were accepted for the FGCN 2010 Special Sessions Of the 70 papers, were selected for the special FGIT 2010 volume published by Springer in LNCS series Fifty-one papers are published in this volume, and 13 papers were withdrawn due to technical reasons We would like to acknowledge the great effort of the FGCN 2010 International Advisory Board and Special Session Co-chairs, as well as all the organizations and individuals who supported the idea of publishing this volume of proceedings, including SERSC and Springer Also, the success of the conference would not have been possible without the huge support from our sponsors and the work of the Organizing Committee We are grateful to the following keynote speakers who kindly accepted our invitation: Hojjat Adeli (Ohio State University), Ruay-Shiung Chang (National Dong Hwa University), and Andrzej Skowron (University of Warsaw) We would also like to thank all plenary speakers for their valuable contributions We would like to express our greatest gratitude to the authors and reviewers of all paper submissions, as well as to all attendees, for their input and participation Last but not least, we give special thanks to Rosslin John Robles and Maricel Balitanas These graduate school students of Hannam University contributed to the editing process of this volume with great passion December 2010 Tai-hoon Kim Thanos Vasilakos Kouichi Sakurai Yang Xiao Gansen Zhao Dominik ĝlĊzak Organization General Co-chairs Alan Chin-Chen Chang Thanos Vasilakos MingChu Li Kouichi Sakurai Chunming Rong National Chung Cheng University, Taiwan University of Western Macedonia, Greece Dalian University of Technology, China Kyushu University, Japan University of Stavanger, Norway Program Co-chairs Yang Xiao Charalampos Z Patrikakis Tai-hoon Kim Gansen Zhao International University of Alabama, USA National Technical University of Athens, Greece Hannam University, Korea Sun Yat-sen University, China Advisory Board Wai-chi Fang Hsiao-Hwa Chen Han-Chieh Chao Gongzhu Hu Byeong-Ho Kang Aboul Ella Hassanien National Chiao Tung University, Taiwan National Sun Yat-sen University, Taiwan National Ilan University, Taiwan Central Michigan University, USA University of Tasmania, Australia Cairo University, Egypt Publicity Co-chairs Ching-Hsien Hsu Houcine Hassan Yan Zhang Damien Sauveron Qun Jin Irfan Awan Muhammad Khurram Khan Chung Hua University, Taiwan Polytechnic University of Valencia, Spain Simula Research Laboratory, Norway University of Limoges, France Waseda University, Japan University of Bradford, UK King Saud University, Saudi Arabia Publication Chair Maria Lee Shih Chien University, Taiwan VIII Organization Special Session Co-chairs Hong Kook Kim Young-uk Chung Suwon Park Kamaljit I Lakhtaria Marjan Kuchaki Rafsanjani Dong Hwa Kim Gwangju Institute of Science and Technology, Korea Kwangwoon University, Korea Kwangwoon University, Korea Atmiya Institute of Technology and Science, India Shahid Bahonar University of Kerman, Iran Hanbat University, Korea Table of Contents – Part II Congestion Avoidance and Energy Efficient Routing Protocol for WSN Healthcare Applications Babak Esmailpour, Abbas Ali Rezaee, and Javad Mohebbi Najm Abad An Efficient Method for Detecting Misbehaving Zone Manager in MANET Marjan Kuchaki Rafsanjani, Farzaneh Pakzad, and Sanaz Asadinia 11 Query Answering Driven by Collaborating Agents Agnieszka Dardzinska 22 Attribute-Based Access Control for Layered Grid Resources Bo Lang, Hangyu Li, and Wenting Ni 31 A Local Graph Clustering Algorithm for Discovering Subgoals in Reinforcement Learning Negin Entezari, Mohammad Ebrahim Shiri, and Parham Moradi 41 Automatic Skill Acquisition in Reinforcement Learning Agents Using Connection Bridge Centrality Parham Moradi, Mohammad Ebrahim Shiri, and Negin Entezari 51 Security Analysis of Liu-Li Digital Signature Scheme Chenglian Liu, Jianghong Zhang, and Shaoyi Deng An Optimal Method for Detecting Internal and External Intrusion in MANET Marjan Kuchaki Rafsanjani, Laya Aliahmadipour, and Mohammad M Javidi SNMP-SI: A Network Management Tool Based on Slow Intelligence System Approach Francesco Colace, Massimo De Santo, and Salvatore Ferrandino Intrusion Detection in Database Systems Mohammad M Javidi, Mina Sohrabi, and Marjan Kuchaki Rafsanjani 63 71 83 93 A Secure Routing Using Reliable 1-Hop Broadcast in Mobile Ad Hoc Networks Seungjin Park and Seong-Moo Yoo 102 A Hybrid Routing Algorithm Based on Ant Colony and ZHLS Routing Protocol for MANET Marjan Kuchaki Rafsanjani, Sanaz Asadinia, and Farzaneh Pakzad 112 Performance Evaluation of FAST TCP Traffic-flows in Multihomed MANETs 457 Fig Throughput achieved by Fast TCP over link2 (with some network failures) in a multihomed MANET with 52 nodes moving randomly in an area of 500mx500m Fig Aggregate throughput of Link1 and Link2 in a multihomed MANET 458 M.U Mudassir and A Akram Conclusions In this paper, we analyzed the performance of FAST TCP protocol in high speed and long latency MANETs The simulation results clearly show that as the number of mobile nodes increase in a MANET the throughput starts increasing also The idea of multihoming with FAST TCP in MANETs is a new idea and the simulations have proved that it can raise the throughput of a session , and in real scenarios the throughput can be increased to almost 60 to 70 percent We are still investigating its performance under different circumstances In future we would like to enhance this research for Vehicular Ad hoc Networks (VANETs) References Wiki on Mobile ad hoc network, http://en.wikipedia.org/wiki/Mobile_ad_hoc_network Ohta, M.: The Architecture of End to End Multihoming Internet-draft, IETF, draft-ohta e2emultihoming-03.txt (November 2002) Arshad, M., Junaid, M.M.: Saleem: Issues of multihoming implementation using Fast TCP: a simulation based analysis IJCSNS International Journal of Computer Science and Network Security 8(9) (September 2008) Braden, R.: Requirements for Internet Hosts – Communication Layers RFC1122, IETF (October 1989) Jin, C., Wei, D., Low, S.H.: FAST TCP: motivation, architecture, algorithms, performance Tech Rep CaltechCSTR: 2003.010, Caltech, Pasadena CA (2003) CMU Monarch project, Computer Science Department, Canergie Mellon University, Pittsburgh.: The CMU Monarch project’s wireless and mobility extensions to ns (1999) Allman, M., Paxson, V., Stevens, W.: TCP Congestion Control RFC2581, IETF (April 1999) Stewart, R., Xie, Q., Morneault, K., Sharp, C., Schwarzbauer, H., Taylor, T., Rytina, I., Kalla, M., Zhang, L., Paxon, V.: Stream Control Transmission Protocol RFC 2960 (October 2000) Calvo, R.A., Campo, J.P.: Adding Multiple Interface Support in NS-2, http://personales.unican.es/aguerocr/files/ ucMultiIfacesSupport.pdf 10 Wang, Q., Zhang, T.: Simulating Wireless Multihomed Node in NS-2 11 VINT Project, Network Simulator ns-2, http://www.isi.edu/nsnam/ns/ 12 Fall, K., Varadhan, K.: The ns Manual The VINT Project, UC Berkeley, LBL, USC/ISI, and Xerox PARC (2006) 13 Cui, T., Andrew, L.: FAST TCP module for ns-2, http://cubinlab.ee.mu.oz.au/ns2fasttcp Fault Tolerant Implementation of Xilinx Vertex FPGA for Sensor Systems through On-Chip System Evolution S.P Anandaraj1, R Naveen Kumar2, S Ravi3, and S.S.V.N Sharma4 Department of CSE, St.Peter’s University, Chennai – 600 054 Dept of Informatics, Kakatiya University, Warangal – 506 011 Department of ECE, Dr M.G.R University, Chennai – 600 095 Dept of Informatics, Kakatiya University, Warangal – 506 011 Abstract Nowadays, majority of applications struggle to achieve good behavior of their subsystems by cooperation of systems, which is independently designed, separately located, but mutually affecting subsystems Such coordinating systems are hard to attain the specific structural models and effective parameters In such cases, the evolved hardware (EHW) methods with evolutionary Algorithms (EA) to achieve sophisticated level of information [2] Numeral systems were introduced with evolvable hardware on a single chip to overcome the lack of flexibility, with the support of modifiable evolutionary algorithm stored in software on a built-in processor This paper proposed the architecture with Xilinx Virtex-II Pro FPGA with interfaced PowerPC processor Due to this speedy processing, time consumption in hardware and also allows other parts to be easily modifiable software The proposed technique will provide more benefits in the future work as regards cost and compactness [1] The system was completely analyzed on physical devices with software executing in parallel with fitness computation in digital logic circuits, and the results determine that the system uses only double the time when compared to a PC running at 10 times faster clock speed[6] Introduction To achieving time in real-time evolvable systems is too difficult Apart from that, cost and compactness is also a vital factor Integration of a system is important on a single chip with these factors More number of techniques was found out earlier Kajitani et al introduced several Large-Scale Integrated Circuits with evolvable hardware This approach provided speedy processing but system has deficiency in flexibility So, many degrees of freedom should be considered while realizing evolvable hardware systems VLSI (Very Large-Scale Integration) Poetic chips have also been described for On-chip evolution [6] A Robot Controller was designed with architecture that contains 32-bit on-chip custom processor and bio-motivated arrays of building blocks So, the chips are dedicated for the implementation of bio-motivated mechanisms [5] This paper exhibits how a general FPGA (Field Programmable Gate Array) provides a medium for OnChip System progression This on-chip system evolved by integrating the software T.-h Kim et al (Eds.): FGCN 2010, Part II, CCIS 120, pp 459–468, 2010 © Springer-Verlag Berlin Heidelberg 2010 460 S.P Anandaraj et al running on a PCprocessor with the evolvable hardware implemented in digital logic with reconfigurable approach So, it allows fast fitness computation normally the time consumption part of evolution by measuring fitness in hardware communicating with processor within same evolved hardware chip Tufte and Haddow proposed FPGA with complete evolution implementation Evolutionary mechanisms are also implemented in the evolving design [8] A similar system is proposed by Perkins et al This system achieved speedup in non-linear filtering when compared to conventional processing Shackle ford et al has introduced many custom accelerators in FPGA for solving a challenged folding problem Then, Sekanina reported Virtex XC2V3000 FPGA with complete running evolution [7] This evolution is implemented in modifiable logic with 3x3 and 3x4 bit multipliers This paper represents the work with XC2VP7 Virtex-II Pro FPGA with reconfigurable logic, a PowerPC 405hard-core processor block, and on-chip RAM and high speed serial links for external interfaces This work is based on the designing of co-processor for analog neural network ASIC In contrast to, evolution of digital circuits and evolutionary system is focused in a single device [3] The balanced software-hardware approach will provide low implementation effort on a single chip design, suited for interfaced real-world applications The most important stimulus of producing single processing unit with On-chip evolution and fitness computations, Which is allowed for real time scalable systems The connection of number of such processing units into a grid, achieves parallel processing [3] Thus, this system architecture will be very scalable and flexible Software plays major role in affording flexibility, in addition the hardware also comparatively easy to modify in the system architecture [2] This paper also discusses about the system performance by taking into many experimentation on evolving small multiplier circuits This document explains the speed of evolution apart from evolution of very large and composite Circuits System Architecture with Virtex-II Pro FPGA with Evolutionary Algorithm 2.1 Xilinx Vertex-II Pro (XC2VP7-FG456-7) FPGA The system is implemented with Xilinx Virtex-II Pro (XC2VP7-FG456-7) FPGA [7], operates with 11,088 Logical Cell Units, 792 Kbit dual-port SRAM – otherwise named as BRAM (Block Select RAM), and PowerPC405 (PPC) processor and shown in Fig.1 The maximum speed of the PowerPc405 Processor is 300MHZ The FPGA is situated on a Memec Design Virtex-II Pro development board, has dual Xilinx XC18V04 with well configured EEPROMs 32MB SDRAM, Rocket I/O ports, as RS232 port, an LCD panel and other useful connections Fault Tolerant Implementation of Xilinx Vertex FPGA for Sensor Systems 461 Fig Virtex –II Pro FPGA 2.2 Evolvable Hardware Architecture with Evolutionary Algorithm on FPGA The Xilinx Virtex-II Pro FPGA has interfacing of Embedded Development Kit (EDK), collection of logical Property (LP) cores and tools for building systems [8] Hardware and Software parts of the system can be specified parametrically through various configuration files, net details and libraries are generated automatically The 3RZHU 'DWD 0HPRU\ 3& 3UR % FHVVRU %5$0 ,QVWUQ 0HPRU\ WƌŽŐƌĂŵ DĞŵŽƌLJ ;ϲϰ (YROYDEOH +DUGZDUH ƌŝĚŐĞ ;W>ϮϬWͿ WĞƌŝƉŚĞƌĂůƐ KW 8$57 56,I >/ͬ& ^ZD DĞŵŽƌLJ /ͬ& Fig System architecture with Evolvable Hardware (EHW) 462 S.P Anandaraj et al system architectural units contain set of modules communicated with buses Two numbers of buses are used to connect on-chip peripherals, namely the Processor Local Bus (PLB) and On-chip Peripheral Bus (OPB) The PLB is a high-performance 64bit data path bus and OPB is a 32-bit wide bus designed for peripherals with lower requirements [5] Both the buses runs at different clock domains and bridge is used to interconnect the buses in the operations and Shown in below Fig.2 The fig.2 shows the interconnection of PLB and OPB with various communication intensive units The PLB is connected with PowerPC processor (CPU) and 64KB BRAM for executing program instructions The PowerPC Processor is embedded with two On-Chip Memories, 16KB BRAM and 8KB instruction Cache(IC) Both of the memories act as interfaces between FPGA and PPC unit The 16KB BRAM in PPC is used for Storage of data-side Memory unit and 8KB BRAM acts as instruction side memory space These interfaces are usually used for executing instructions and data caches, which is already embedded in BRAM The On-Chip memories interface with PLB Bus interconnection is benefited in such a way that no bus arbitration is needed for accessing memory, instruction and data access not have to share the same interfaces The On-chip Memory (OCM) is used for storage for all program data and increases program execution speed, i.e twice the speed for program execution by introducing instruction caching and thrice the speed for accessing all program data through data side interface [1] The On-Chip Peripheral Bus (OPB) is connected with target Evolvable Hardware (EHW) and also with a wide range of On-Chip Peripherals, UART for RS232 interface for serial communications [7], LCD interface and LED interface and made known in Fig.2 2.3 Realization of Genetic Algorithm on PowerPC Processor The PowerPC Processor operates the Genetic Algorithm (GA) by the Program written in C language, it is compiled and linked using PPC405 version of GNU GCC compiler tools [8] When implementing the Genetic Algorithm (GA) on PPC system, some system limitations have to be considered like program memory and floating point operations The program memory is limited one A maximum of 64 KB of BRAM was allowed for the executable size Even though, there exists 32MB of SDRAM on the development board, it was decided to only use BRAM internal to FPGA This BRAM operates in faster manner and allows the program to be loaded directly from the bit stream that configures the FPGA [12] During the execution of parallel processing, large program fitted in BRAM should be loaded into SDRAM using boot loader from external nonvolatile memory during initialization SDRAM acts as data storage, but it will be slower when data cache is used In PPC405 version, floating point operations are not supported Floating point operation in C programs is used, when floating point co-processor is available Recursive floating point is not effective in case of speedy processing, which results the increase in program size [10] This restriction in C language leads us to use C++ language for minimizing the use of standard library functions To achieve the speedy processing, fixed point or integer points should be implemented to reduce the program executable size Fault Tolerant Implementation of Xilinx Vertex FPGA for Sensor Systems 463 The C-Programming in PowerPC Processor abandons the use of library functions, mainly floating point operations, leads us slightly complicated implementation and results in time consumption However, the degree of program flexibility and the speed of algorithm implementation is very high compare to assembly programming or other interactive hardware solutions By considering the restrictions, the program was developed mostly using Microsoft’s Visual Studio, it runs on both PC and FPGA platform Some few source codes of lines have to be written more specifically for the PPC[11] The PC version of the program is equally fast as if it would have been developed for PC only The algorithm implemented in this experiment follows Genetic Programming, defined by Goldberg Fitness computations are used as proportionate selection scheme through the use of roulette wheel mechanism Qsort algorithm is used to sort the individual data inputs For mutation, instead of having one probability of mutation for every bit in the genome, a quicker solution has been adopted [12] The number of mutations n, for the whole genome is calculated by random lookup in a 10-position array Then, n random placed are bit-flipped in genome This calculations are more efficient then checking every bit if mutation takes place or not 2.4 Implementation of Evolvable Hardware for System Flexibility The Fig.2 represents the implementation of target evolvable hardware (EHW) on OPB slave bus Xilinx IP line hub is used to interface OPB bus in simpler way for the user model This interface device is connected in both OPB and PLB buses The adaptation of target EHW to the PLB bus is an easier task due to IP line hub Control and configuration of the EHW is done through register Write operations in C++ Genome values are written to registers which are again connected to the configuration inputs of each functional module Registers are also provided for EHW for getting inputs and for storage of outputs KW KW /ŶƚĞƌĨĂĐĞ /W/ŝͬĨ /ͬW &ƵŶĐƚŝŽŶĂůhŶŝƚ DĞŵŽƌLJ ŽŶĨŝŐ ŽŶƚƌŽů>ŝŶŬƐ Fig EHW design KͬW 464 S.P Anandaraj et al The functional unit in Fig is the core of EHW, which performs all the functionalities like processing inputs, carry out mathematical operation on inputs, and storage of output Each and every functional unit gets three inputs are a time Each of the input signals can be inverted Each input unit can perform all the four functions: BUF, MUX, AND, XOR The functional units and its three inputs are configurable and determined by genetic programming [2] In functional units of the genome string are encoded and shown below Input data1 (4 bits) Input data (4 bits) Input data (4 bits) Function Unit (2 bits) Out of bits each input, one bit can be inverted in toggling, remaining bits used for output from the previous layer For our array consisted for layers with units, the genome string line becomes 672 bit long by calculations[5] The array is built in parallel approach, and registers are interfaced to the output of each layer Only one training vector is calculated at a time 2.5 GA Constraints and Fitness Computations For the system development, constrains are used with size of 20 Exclusive constraints are used for selecting best performing parameter to be carried for next iteration The crossover rate of each individual is 0,5 and replication rate is 0.5 A roulette wheel selection scheme is applied and linear scaling is used as Fitness computations [9] The transformation rate is expressed as probability for number of inputs n The probability for each input is shown in below table Table Input Probabilities No of inputs (X) Probability value P(N) 1/10 6/10 2/10 1/10 6/10 Fault Tolerant Implementation of Xilinx Vertex FPGA for Sensor Systems 465 The Fitness Computation (F) is used for analyzing the input(x) with the following function [3], For the given input, the computed output y is compared to the target output d If y=d, then addition function is generated used GA and is added to fitness function (F) Then, the function sums these values for the output to be displayed and is used stored in truth table vectors Experimental Outcomes In this sector, the system is analyzed and represented with below parameters 3.1 Device Flexibility and Speed Rate The above table.2 represents the amount of device utilization for target evolvable hardware (EHW), contains 8x6 functional memory modules During the execution, utmost 20% of FPGA overall devices are used The entire system device utilization including bus construction and peripherals is 43% The system constitutes Xilinx Vertex-II pro FPGA, relative small when compared with devices up to 1, 42,000 logical units [12] The device utilization specifies the use of large composite FPGAs to increase more system flexibility The utmost clock rate in this system reached 200 MHZ frequency for PowerPC processor and 50 MHZ for the remaining part of the system, which comprises both PLB and OPB modules equally The predicted speed rate for PowerPC processor is 300 MHZ and 100 MHZ for the remaining system This could be overcome by implementing high speed processor Table EHW Device Performance Rate Devices/ Characteristics Used Available System Performance % Chip Flip Parts Flops (FF) 1025 896 4928 9856 Input LUTs 20 12 1231 9856 466 S.P Anandaraj et al 3.2 Evolution Rate Evolution runs were conducted on specified on-chip system and a Pentium 4(P4) terminal is used evaluate speed rate The Pentium4 terminal has a clock speed of 2GHZ For the speed test, 10,000 probability of 20 data which are specified individually The fitness evaluation was for 2x2 bit multiplier, thus 16 input/output units were used Table GA with fitness evaluation speed Design Fitness parameter without GA Fitness Parameter with GA Total % of Fitness Time Power Power4 PC Processor Processor (sec) (sec) 8.3 1.3 20 8.6 59 85 Table.3 indicates the comparison of execution speed of GA parameters without fitness and with fitness The table.3 indicates the use of P4 processor is running at higher clock speed and operates with more well-organized memories interface and caches But in terms of evolution speed, PowerPC processor provides 65%, whereas P4 processor provides 30% evolution speed in case of executing lower instructions per clock cycle 3.3 Circuit Design On-chip system is designed with 2x2 bit multiplier, used after 5702 iterations over 10 progressions Same on-chip was used on PC terminal for testing; it resulted in the average of 5649 iterations [6] The different values can be described by various programs using probability number generators This results were resembled in FPGA implementation, and works perfectly providing on-chip flexibility Future Developments The specified on-chip system design should be examined completely for gaining higher clock speed rate To achieve this, higher bus speed will be resolution for the reconfiguration phase in target evolvable hardware (EHW) If, this bus is interfaced with target EHW to PLB bus, then extensive data path will be achieved [11] The PPC’s data BRAM can be connected with other BRAM, so, dual-ported Data BRAM will be implemented [5] Fault Tolerant Implementation of Xilinx Vertex FPGA for Sensor Systems 467 To increase the speed rate, fitness evaluations should be modified Definite software functions also should be moved into hardware units Mainly for digital systems with labeled training examples, it will be beneficial to formulate the system that inputs the EHW unit with one labeled example per clock cycle Since the functional memory modules are pipelined, the number of cycles needed for one complete GA parameters, which would be approximately equal to the number of training vectors By using more number of EHW units on the same chip, high degree of hardware specialization will be achieved with reduced cost and with higher development work This paper presents the outcome of our primary experiments on the progressed platform on the implementation of PowerPC Processor on the evolving hardware This makes us to achieve real-world applications with on-chip flexibility [11] The most part of the computational time is used for fitness evaluation for small multipliers in small circuits also So, it results in the more data’s to be evaluated with time used for small computations Additionally, more flexibility is significant with evolutionary and bio-inspired techniques This is attained in our platform with PPC consisting the blocks not critical on estimation of time Conclusions This paper discusses the approach of using Evolvable hardware in digital circuit’s results in emerging of technology, On-chip system flexibility using FPGA Mainly, this work centers the prospective of running o EHW on embedded PowerPC processor in FPGA The very initial test on system on evaluating performance is little bit compromising, but, anyway it results in cost effective solution to embedded systems References Hollingsworth, G., Smith, S., Tyrrell, A.: Design of Highly Parallel Edge Detection Nodes using Evolutionary Techniques In: Proceedings of the 7th Euro Micro Workshop on Parallel and Distributed Processing, pp 35–42 IEEE, Los Alamitos (1999) Layzell, P.: Reducing Hardware Evolution’s Dependency on FPGAs In: Proceedings of the Seventh International Conference on Microelectronics for Neural, Fuzzy and BioInspired Systems (Micron euro 1999), pp 171–178 IEEE, Los Alamitos (1999) Clark, G.R.: A Novel Function-Level EHW Architecture within Modern FPGAs In: Proceedings of the Congress on Evolutionary Computation (CEC 1999) IEEE, Los Alamitos (1999); Hollingworth, G., Smith, S., Tyrrell, A.: Safe Intrinsic Evolution of Virtex Devices In: Proceedings of the Second NASA/DoD Workshop on Evolvable Hardware, pp 195–202 IEEE, Los Alamitos (2000) Thompson, A., Harvey, I., Husbands, P.: The natural way to evolve hardware In: Proc IEEE Int Symp Circuits Syst., pp 37–40 (1996) Hereford, J., Pruitt, C.: Robust sensor systems using evolvable hardware In: Proc NASA/DoD Conf Evolvable Hardware, Seattle, WA, pp 161–168 (June 2004) Thompson, A., Harvey, I., Husbands, P.: The natural way to evolve hardware In: Proc IEEE Int Symp Circuits Syst., pp 37–40 (1996) Sun, X., Xu, J., Chan, B., Trouborst, P.: Novel Technique for Built-In Self-Test of FPGA Interconnects In: Proc Of IEEE International Test Conference, pp 795–803 (2000) 468 S.P Anandaraj et al Programmable Data Book, Xilinx Inc (2003) Renovell, M., Portal, J.M., Figuras, J., Zorian, Y.: Testing the Interconnect of RAM-Based FPGAs In: IEEE Designand Test of Computers, pp 45–50 (1998) 10 Feng, W., Chen, X., Meyer, F.J., Lombardi, F.: Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources In: Proc IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp 368–376 (1999) 11 Sekanina, L.: Toward uniform approach to design of evolvable hardware based systems In: Grünbacher, H., Hartenstein, R.W (eds.) FPL 2000 LNCS, vol 1896, pp 814–817 Springer, Heidelberg (2000) 12 Torresen, J.: Possibilities and limitations of applying evolvable hardware to real-world application 13 Hartenstein, R.W., et al (eds.): FPL 2000 LNCS, vol 1896, pp 230–239 Springer, Heidelberg (2000) Author Index Abad, Javad Mohebbi Najm II-1 Abdelli, Abdelkrim I-85 Aboul-Dahab, Mohamed A I-121 Agrawal, K.P II-405 Ahn, Hyosik II-198, II-205 Akram, Adeel II-450 Aliahmadipour, Laya II-71 Anandaraj, S.P II-459 Asadinia, Sanaz II-11, II-112 Back, Sung-Hyun I-217 Bae, Kyeong-Ryeol II-343 Benkaouha, Haroun I-85 Bouyahia, Karima I-85 Busanelli, Stefano I-137, I-188 Cagalaban, Giovanni I-1, II-276 Chandrakant, N II-441 Chang, Hyokyung II-198, II-205, II-214 Chen, Tien-ho I-46 Cheong, Seung-Kook I-132 Cho, Choong Sang II-162 Cho, Kee Seong I-37, I-56 Choi, Euiin II-198, II-205, II-214 Choi, Seong Gon I-37, I-56 Choi, Seong-Yong I-66 Choi, Seung Ho II-138 Choi, Song Ha II-148, II-155 Choi, Sung-Ja II-218 Chu, William C I-227 Chun, Chan Jun II-162 Chun, Myung Geun II-188 Colace, Francesco II-83 Dardzinska, Agnieszka II-22 Deng, Shaoyi II-63 De Santo, Massimo II-83 EL-Badawy, Hesham M I-121 Entezari, Negin II-41, II-51 Esmailpour, Babak II-1 Farahmand, Hossein II-123 Ferrandino, Salvatore II-83 Ferrari, Gianluigi I-137, I-188 Gangarde, Arun D II-347 Garg, Ruchi II-432 Geetha, T.L II-370 Gong, Zhenghu I-15 Ha, Deock-Ho II-311, II-316 Ha, Ok-Kyoon II-227, II-238 Han, Jechan I-112 Han, Jungyoo II-330 Hashim, Rathiah I-237 Hayder, Syed Irfan II-354 Herawan, Tutut I-237 Hsiang, Han-chen I-46 Hsu, Chien-Lung I-23 Ikhmatiar, Mohammad S I-237 Iotti, Nicola I-137 Jadhav, Shrikant.S II-347 Jang, Bokman II-198, II-205 Jang, Bong-Im I-180 Jang, Jong-Wook I-217 Jang, Sei-Jin II-180 Jang, Seok-Woo II-247 Javidi, Mohammad M II-71, II-93 Jeon, HahnEarl I-76, I-104 Jeong, Dong-Gyu II-223 Jeong, Yoon-Su I-164 Jin, Ik Soo II-262, II-284 Jo, Sungdong II-180 Jun, Yong-Kee II-227, II-238 Jung, Min A II-138 Jung, Sungmo I-10, II-276 Kaloune, Yasmina I-85 Kanavalli, Anita II-370 Kang, Byeong Gwon II-335 Kang, Sanggil I-199 .. .Communications in Computer and Information Science 120 Tai-hoon Kim Thanos Vasilakos Kouichi Sakurai Yang Xiao Gansen Zhao ´ ˛zak (Eds.) Dominik Sle Communication and Networking International... together researchers from academia and industry as well as practitioners to share ideas, problems and solutions relating to the multifaceted aspects of communication and networking, including their... +1) As our packets and command are going in the same tout, so in an intermediate node we use this parameter in the algorithm below in upstream data packet and downstream commands to change path